From patchwork Tue Jul 14 11:04:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11662249 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A700913B4 for ; Tue, 14 Jul 2020 10:04:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E15B2220D for ; Tue, 14 Jul 2020 10:04:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XktoSDHv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727786AbgGNKEo (ORCPT ); Tue, 14 Jul 2020 06:04:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726788AbgGNKEh (ORCPT ); Tue, 14 Jul 2020 06:04:37 -0400 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C77C2C061755; Tue, 14 Jul 2020 03:04:36 -0700 (PDT) Received: by mail-ed1-x544.google.com with SMTP id z17so16406616edr.9; Tue, 14 Jul 2020 03:04:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AjG9ZXkNlThAdSsdCQVBfTOrnZyMZnOrLKfSK8ObxrE=; b=XktoSDHvwVEyA2qSIGNOe+27lD8+It+w/oscI06k1+IugxY4fNo2iArgZd7tJ3tb5O RZLCpZitcssWbDWunZax7lwh9Ub95pp+os7YmA1wVFQDvEkawcTNqADWbZKkp6tPST+L 0s2KtGLEv1ioVe3n135P1Uxczafk+qydGAZ3fXM6ExjpuPgazhaCAFxHSbqeWtQhQZYJ UaXEnOhyR07Hvudk1fhTt6QO6f57G7Lu9TsSqwH+516GePqs2elh6vuHaWvsBRyfb9vL ijKUVWQqPdfzp/6LgoJCP0wzjZ1REOKByf9BIwseFbU07cEx/bPJr7KvC+/n6vjQqGQ/ 0zJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AjG9ZXkNlThAdSsdCQVBfTOrnZyMZnOrLKfSK8ObxrE=; b=ku0vuYgkIqG0JhqPOvabSObs2wT4DAd71DoCBCpIKflyVWwPYK1RnJN4TPr3MLVBi9 3d5tNvapVs1tcu93AZl6OwicBAnxs15ajElKK5FhCxR9/nR+9eCy2RDu6bQxn6pQjJ/c afDIrx2Vz9RphrgaY13qCczdNmyRjXHY8J8lvFXnMMYl6gEYf331NakZgF4mF1HWnGQv WNY0efN6o8p5ilnLOob2InpzAnIMpYDTNXTQqtSu5q+UGz6hIumDGuevcw2OcVkRcjeo JW5YDuG2/gQO6NWePoFmC6jaYE/DiFOAv5+lBsUHdlrMwU3tnWSs+jcwYBWSNikkVyRr xXMw== X-Gm-Message-State: AOAM532axULvVGz09qzDcibd+MQX2Ef8FX0jNEym2me4HDJkDrcKrDG/ 8i3X6baKGy+dIi+iX1vWCs4= X-Google-Smtp-Source: ABdhPJw4d+6fAHfArS6YVCLKVPm4T/c8KMuzMlKt/TwrMSjQlmp+/J9pYfzHKZouoVLK/LJ5+omnQQ== X-Received: by 2002:aa7:c305:: with SMTP id l5mr3754952edq.163.1594721075471; Tue, 14 Jul 2020 03:04:35 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id bs18sm14137672edb.38.2020.07.14.03.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2020 03:04:35 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14 v4] PCI: Check return value of pcie_capability_read_*() Date: Tue, 14 Jul 2020 13:04:44 +0200 Message-Id: <20200714110445.32605-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200714110445.32605-1-refactormyself@gmail.com> References: <20200714110445.32605-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_word is checked to confirm success. Check the return value of pcie_capability_read_word() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- v4 changes: Remove unnecessary boolean conversion. drivers/pci/probe.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..3c87a8a1d4b5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1121,10 +1121,11 @@ EXPORT_SYMBOL(pci_add_new_bus); static void pci_enable_crs(struct pci_dev *pdev) { u16 root_cap = 0; + int ret; /* Enable CRS Software Visibility if supported */ - pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); - if (root_cap & PCI_EXP_RTCAP_CRSVIS) + ret = pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); + if (!ret && (root_cap & PCI_EXP_RTCAP_CRSVIS)) pcie_capability_set_word(pdev, PCI_EXP_RTCTL, PCI_EXP_RTCTL_CRSSVE); } @@ -1519,9 +1520,10 @@ void set_pcie_port_type(struct pci_dev *pdev) void set_pcie_hotplug_bridge(struct pci_dev *pdev) { u32 reg32; + int ret; - pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); - if (reg32 & PCI_EXP_SLTCAP_HPC) + ret = pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); + if (!ret && (reg32 & PCI_EXP_SLTCAP_HPC)) pdev->is_hotplug_bridge = 1; } @@ -2057,10 +2059,11 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) { u16 v; + int ret; - pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); - return !!(v & PCI_EXP_DEVCTL_RELAX_EN); + return (!ret && (v & PCI_EXP_DEVCTL_RELAX_EN)); } EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); @@ -2096,16 +2099,17 @@ static void pci_configure_ltr(struct pci_dev *dev) struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); struct pci_dev *bridge; u32 cap, ctl; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_LTR)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_LTR)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); - if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); + if (!ret && (ctl & PCI_EXP_DEVCTL2_LTR_EN)) { if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { dev->ltr_path = 1; return; @@ -2142,12 +2146,13 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) struct pci_dev *bridge; int pcie_type; u32 cap; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) return; pcie_type = pci_pcie_type(dev); From patchwork Tue Jul 14 11:04:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11662247 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F28FC13B1 for ; Tue, 14 Jul 2020 10:04:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D235E22202 for ; Tue, 14 Jul 2020 10:04:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="M6BF8Y/o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725906AbgGNKEk (ORCPT ); Tue, 14 Jul 2020 06:04:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727114AbgGNKEj (ORCPT ); Tue, 14 Jul 2020 06:04:39 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A7B7C061794; Tue, 14 Jul 2020 03:04:38 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id y10so20911044eje.1; Tue, 14 Jul 2020 03:04:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nmxYIVd0VfpP8/5JYBPjSipRO5vcl/2LLzPMpP8Wy5Q=; b=M6BF8Y/ogqjKG1sQerDUjvMfxOJUoQ4IDmRmr6SC25fH9bQDRD3inUDtJo5vIYcYNV GVoJeZM2bHqF6goed8h17WAMzukEsDLoE4TNNFKyRG1ddwH1SUJr+/f1M21TuAaF18ch UVAYrZkacansfdxKmwSTOLsfG97kkLJHlcp9esR2kH2lCyM3ykudairrZM3NAa3ub7Xm k26Cjsp2fcHJ+F62HdVo1yOpAQ6l8sKimgsJbpsdeuMnSSy4JFiFLsB11SRbrDRoVUou sPIMFT17j5DqyoK67Ak9vClBcKbEBgPJ39innRsnu7yalF6xwBV8yhNTe6ehsapABvjg UW6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nmxYIVd0VfpP8/5JYBPjSipRO5vcl/2LLzPMpP8Wy5Q=; b=eFFKDoLnX/xwKbTXoVRfAieaHj7Zf2Nets5EmjZ8ZrltdhrCoUr8E4ZYLFft/FxBL8 +pC0o1eacHacyOLVYLXDAfLg10I8RbW+abK0SQS+SFbTNiRHoHrpB7kRWHjSyL749aXQ iDWG1/3S6wedqWm1xjMkx3NrO+i9shn13GhEeWPgukl+BoXkp37LXguIsHcwbXns/vqK l90Hj9rkhVFfLRHIy7NLpmZbsZoRkR9NsyXR656zXgV36nVM2uPxI+BGYy4Cx79xBoJS buozfyXK7N+SvVTlK7oIitSp5gyCTzPl+jGq1/Ca3re34bfGuWouM67Nnb9/uey9DiNQ +dIw== X-Gm-Message-State: AOAM530C+x8grCeydp7VrAVRA+VpEAh+OuoJ4tb5O8EGDR3zdq+tXosc 7xfZCoO2lyhotjydI/QLF5Y= X-Google-Smtp-Source: ABdhPJyVMd7rZKDdA42Cfz/SHZeT+y7p+5je7Lzrmo3+snFmBiiRwH8ZpcuxopEWCIx9CRqzmiphHw== X-Received: by 2002:a17:906:364e:: with SMTP id r14mr3644852ejb.258.1594721076740; Tue, 14 Jul 2020 03:04:36 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id bs18sm14137672edb.38.2020.07.14.03.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2020 03:04:36 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14 v4] PCI/PM: Check return value of pcie_capability_read_*() Date: Tue, 14 Jul 2020 13:04:45 +0200 Message-Id: <20200714110445.32605-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200714110445.32605-1-refactormyself@gmail.com> References: <20200714110445.32605-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success/failure. This check helps ensure that functions exit only when their post-condition is true. For functions which walks through device heirarchy like pci_enable_atomic_ops_to_root(), this is important. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- v4 changes: Remove unnecessary boolean conversion. Fix bugs introduced by previous changes diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4b2a348576cb..d82b79291742 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3207,6 +3207,7 @@ void pci_configure_ari(struct pci_dev *dev) { u32 cap; struct pci_dev *bridge; + int ret; if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) return; @@ -3215,8 +3216,8 @@ void pci_configure_ari(struct pci_dev *dev) if (!bridge) return; - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_ARI)) + ret = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_ARI)) return; if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { @@ -3606,6 +3607,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) struct pci_bus *bus = dev->bus; struct pci_dev *bridge; u32 cap, ctl2; + int ret; if (!pci_is_pcie(dev)) return -EINVAL; @@ -3629,28 +3631,29 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) while (bus->parent) { bridge = bus->self; - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + ret = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, + &cap); switch (pci_pcie_type(bridge)) { /* Ensure switch ports support AtomicOp routing */ case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + if (ret || !(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) return -EINVAL; break; /* Ensure root port supports all the sizes we care about */ case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & cap_mask) != cap_mask) + if (ret || ((cap & cap_mask) != cap_mask)) return -EINVAL; break; } /* Ensure upstream ports don't block AtomicOps on egress */ if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { - pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, - &ctl2); - if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) + ret = pcie_capability_read_dword(bridge, + PCI_EXP_DEVCTL2, &ctl2); + if (!ret && (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) return -EINVAL; } @@ -4507,12 +4510,13 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); bool pcie_has_flr(struct pci_dev *dev) { u32 cap; + int ret; if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return false; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + return (!ret && (cap & PCI_EXP_DEVCAP_FLR)); } EXPORT_SYMBOL_GPL(pcie_has_flr); @@ -4646,7 +4650,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay) { - int timeout = 1000; + int rc, timeout = 1000; bool ret; u16 lnk_status; @@ -4671,9 +4675,9 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, if (active) msleep(20); for (;;) { - pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); - ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); - if (ret == active) + rc = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); + ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); + if (!rc && (ret == active)) break; if (timeout <= 0) break; @@ -4682,10 +4686,10 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, } if (active && ret && delay) msleep(delay); - else if (ret != active) + else if (rc || (ret != active)) pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", active ? "set" : "cleared"); - return ret == active; + return (!rc && (ret == active)); } /** @@ -5774,6 +5778,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed next_speed; enum pcie_link_width next_width; u32 bw, next_bw; + int ret; if (speed) *speed = PCI_SPEED_UNKNOWN; @@ -5783,7 +5788,12 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, bw = 0; while (dev) { - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + + if (ret) { + dev = pci_upstream_bridge(dev); + continue; + } next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> @@ -5820,6 +5830,7 @@ EXPORT_SYMBOL(pcie_bandwidth_available); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) { u32 lnkcap2, lnkcap; + int ret; /* * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The @@ -5830,16 +5841,18 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) * should use the Supported Link Speeds field in Link Capabilities, * where only 2.5 GT/s and 5.0 GT/s speeds were defined. */ - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); /* PCIe r3.0-compliant */ - if (lnkcap2) + if (!ret && lnkcap2) return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!ret && + ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)) return PCIE_SPEED_5_0GT; - else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) + else if (!ret && + ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)) return PCIE_SPEED_2_5GT; return PCI_SPEED_UNKNOWN; @@ -5856,9 +5869,10 @@ EXPORT_SYMBOL(pcie_get_speed_cap); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) { u32 lnkcap; + int ret; - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!ret && lnkcap) return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; return PCIE_LNK_WIDTH_UNKNOWN;