From patchwork Tue Jul 14 16:12:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663163 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6159B722 for ; Tue, 14 Jul 2020 16:13:38 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 5ABE62251F; Tue, 14 Jul 2020 16:13:38 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2CA432075B; Tue, 14 Jul 2020 16:13:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2CA432075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: /e4NUEd4qktY2w++r3tdVC8cDfg7UEJgdfSuGaTVpkICpUtXcM75wxZfADhZCB09hN35yre2LB ymgJCk4j876g== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738100" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738100" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:37 -0700 IronPort-SDR: QcyaP3jmR+RLjEngeSzDHCAO1ftKwgqziLRElxLSVGyWU+jwZTYYffEv4eJQO3cE3/k7OOPA+c jv8wajkqibtw== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930514" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:33 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 1/7] arm64: Add config for Keem Bay SoC Date: Tue, 14 Jul 2020 17:12:59 +0100 Message-Id: <20200714161305.836348-2-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC code-named Keem Bay. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8dd05b2a925c..95c1b9042009 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -121,6 +121,11 @@ config ARCH_HISI help This enables support for Hisilicon ARMv8 SoC family +config ARCH_KEEMBAY + bool "Keem Bay SoC" + help + This enables support for Intel Movidius SoC code-named Keem Bay. + config ARCH_MEDIATEK bool "MediaTek SoC Family" select ARM_GIC From patchwork Tue Jul 14 16:13:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46C3E60D for ; Tue, 14 Jul 2020 16:13:42 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 413D92251E; Tue, 14 Jul 2020 16:13:42 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1EFA42075B; Tue, 14 Jul 2020 16:13:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1EFA42075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: 9BCykvFWozi0howRxUkqizXEgQrpNmZVWzKBC7FBP4D63eYF12Ju288UcACSDXws3T8lrGgxsL 2AZtmv/T5ENw== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738112" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738112" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:41 -0700 IronPort-SDR: 9Bl9P9Y+aWNaqDEUIT7BSqU/2AoejTv8gbq6znqsScl92LmskYyE/mspM7/txa+Ns3DWuWbRwZ lywtY2sg9Tgw== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930533" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:38 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 2/7] dt-bindings: arm: Add Keem Bay bindings Date: Tue, 14 Jul 2020 17:13:00 +0100 Message-Id: <20200714161305.836348-3-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay EVM board. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/keembay.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml diff --git a/Documentation/devicetree/bindings/arm/keembay.yaml b/Documentation/devicetree/bindings/arm/keembay.yaml new file mode 100644 index 000000000000..f81b110046ca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keembay.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Keem Bay platform device tree bindings + +maintainers: + - Paul J. Murphy + - Daniele Alessandrelli + +properties: + compatible: + items: + - enum: + - intel,keembay-evm + - const: intel,keembay +... From patchwork Tue Jul 14 16:13:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 292C860D for ; Tue, 14 Jul 2020 16:13:46 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 224842253D; Tue, 14 Jul 2020 16:13:46 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 00BE52075B; Tue, 14 Jul 2020 16:13:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 00BE52075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: 7OQc+w7H++K1yyXl4aEHmvQIql7bxJDpSbDzxHLppU4sVDamvOzglt9hocLdqDNNvI4fw8sz2g QxsrivmrGXTQ== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738122" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738122" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:45 -0700 IronPort-SDR: JS6+rD7t2ni19gzPe59pM5E/WFoyOHixccFbuMzfUrOjK1XB3x5KZ9QaXbRJnlor8kqVVXd1c6 GmiABp1ZwHEQ== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930553" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:42 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 3/7] dt-bindings: clock: Add Keem Bay clock IDs Date: Tue, 14 Jul 2020 17:13:01 +0100 Message-Id: <20200714161305.836348-4-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add clock dt-bindings for Keem Bay SoC. Signed-off-by: Daniele Alessandrelli --- include/dt-bindings/clock/keembay-clocks.h | 188 +++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 include/dt-bindings/clock/keembay-clocks.h diff --git a/include/dt-bindings/clock/keembay-clocks.h b/include/dt-bindings/clock/keembay-clocks.h new file mode 100644 index 000000000000..4ad6616ee8e0 --- /dev/null +++ b/include/dt-bindings/clock/keembay-clocks.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2020 Intel Corporation. + * + * Device tree defines for clocks in Keem Bay. + */ + +#ifndef __DT_BINDINGS_KEEMBAY_CLOCKS_H +#define __DT_BINDINGS_KEEMBAY_CLOCKS_H + +/* CPR_PLL region. CLK_ID: 0 - 11 */ +#define KEEM_BAY_A53_PLL_START_ID (0) +#define KEEM_BAY_A53_PLL_0_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 0) +#define KEEM_BAY_A53_PLL_0_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 1) +#define KEEM_BAY_A53_PLL_0_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 2) +#define KEEM_BAY_A53_PLL_0_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 3) +#define KEEM_BAY_A53_PLL_1_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 4) +#define KEEM_BAY_A53_PLL_1_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 5) +#define KEEM_BAY_A53_PLL_1_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 6) +#define KEEM_BAY_A53_PLL_1_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 7) +#define KEEM_BAY_A53_PLL_2_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 8) +#define KEEM_BAY_A53_PLL_2_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 9) +#define KEEM_BAY_A53_PLL_2_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 10) +#define KEEM_BAY_A53_PLL_2_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 11) +#define KEEM_BAY_A53_PLL_MAX_ID (KEEM_BAY_A53_PLL_2_OUT_3) + +/* A53_CPR region. CLK_ID: 12 - 30 */ +#define KEEM_BAY_A53_START_ID (KEEM_BAY_A53_PLL_MAX_ID + 1) +#define KEEM_BAY_A53_AON (KEEM_BAY_A53_START_ID + 0) +#define KEEM_BAY_A53_NOC (KEEM_BAY_A53_START_ID + 1) +#define KEEM_BAY_A53_FUSE (KEEM_BAY_A53_START_ID + 2) +#define KEEM_BAY_A53_ROM (KEEM_BAY_A53_START_ID + 3) +#define KEEM_BAY_A53_ICB (KEEM_BAY_A53_START_ID + 4) +#define KEEM_BAY_A53_GIC (KEEM_BAY_A53_START_ID + 5) +#define KEEM_BAY_A53_TIM (KEEM_BAY_A53_START_ID + 6) +#define KEEM_BAY_A53_GPIO (KEEM_BAY_A53_START_ID + 7) +#define KEEM_BAY_A53_JTAG (KEEM_BAY_A53_START_ID + 8) +#define KEEM_BAY_A53_MBIST_0 (KEEM_BAY_A53_START_ID + 9) +#define KEEM_BAY_A53_DSS (KEEM_BAY_A53_START_ID + 10) +#define KEEM_BAY_A53_MSS (KEEM_BAY_A53_START_ID + 11) +#define KEEM_BAY_A53_PSS (KEEM_BAY_A53_START_ID + 12) +#define KEEM_BAY_A53_PCIE (KEEM_BAY_A53_START_ID + 13) +#define KEEM_BAY_A53_VENC (KEEM_BAY_A53_START_ID + 14) +#define KEEM_BAY_A53_VDEC (KEEM_BAY_A53_START_ID + 15) +#define KEEM_BAY_A53_MBIST_1 (KEEM_BAY_A53_START_ID + 16) +#define KEEM_BAY_A53_MBIST_2 (KEEM_BAY_A53_START_ID + 17) +#define KEEM_BAY_A53_MBIST_3 (KEEM_BAY_A53_START_ID + 18) +#define KEEM_BAY_A53_MAX_ID (KEEM_BAY_A53_MBIST_3) + +/* A53_CPR_AUX region. CLK_ID: 31 - 57 */ +#define KEEM_BAY_A53_AUX_START_ID (KEEM_BAY_A53_MAX_ID + 1) +#define KEEM_BAY_A53_AUX_32KHZ (KEEM_BAY_A53_AUX_START_ID + 0) +#define KEEM_BAY_A53_AUX_CPR (KEEM_BAY_A53_AUX_START_ID + 1) +#define KEEM_BAY_A53_AUX_TSENS (KEEM_BAY_A53_AUX_START_ID + 2) +#define KEEM_BAY_A53_AUX_GPIO0 (KEEM_BAY_A53_AUX_START_ID + 3) +#define KEEM_BAY_A53_AUX_GPIO1 (KEEM_BAY_A53_AUX_START_ID + 4) +#define KEEM_BAY_A53_AUX_GPIO2 (KEEM_BAY_A53_AUX_START_ID + 5) +#define KEEM_BAY_A53_AUX_GPIO3 (KEEM_BAY_A53_AUX_START_ID + 6) +#define KEEM_BAY_A53_AUX_DDR_REF (KEEM_BAY_A53_AUX_START_ID + 7) +#define KEEM_BAY_A53_AUX_DDR_REF_BYPASS (KEEM_BAY_A53_AUX_START_ID + 8) +#define KEEM_BAY_A53_AUX_RESERVED1 (KEEM_BAY_A53_AUX_START_ID + 9) +#define KEEM_BAY_A53_AUX_VENC (KEEM_BAY_A53_AUX_START_ID + 10) +#define KEEM_BAY_A53_AUX_VDEC (KEEM_BAY_A53_AUX_START_ID + 11) +#define KEEM_BAY_A53_AUX_USOC_USB_CTRL (KEEM_BAY_A53_AUX_START_ID + 12) +#define KEEM_BAY_A53_AUX_USB (KEEM_BAY_A53_AUX_START_ID + 13) +#define KEEM_BAY_A53_AUX_USB_REF (KEEM_BAY_A53_AUX_START_ID + 14) +#define KEEM_BAY_A53_AUX_USB_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 15) +#define KEEM_BAY_A53_AUX_USB_SUSPEND (KEEM_BAY_A53_AUX_START_ID + 16) +#define KEEM_BAY_A53_AUX_RESERVED2 (KEEM_BAY_A53_AUX_START_ID + 17) +#define KEEM_BAY_A53_AUX_PCIE (KEEM_BAY_A53_AUX_START_ID + 18) +#define KEEM_BAY_A53_AUX_DBG_CLK (KEEM_BAY_A53_AUX_START_ID + 19) +#define KEEM_BAY_A53_AUX_DBG_TRACE (KEEM_BAY_A53_AUX_START_ID + 20) +#define KEEM_BAY_A53_AUX_DBG_DAP (KEEM_BAY_A53_AUX_START_ID + 21) +#define KEEM_BAY_A53_AUX_ARM_CLKIN (KEEM_BAY_A53_AUX_START_ID + 22) +#define KEEM_BAY_A53_AUX_ARM_AXI (KEEM_BAY_A53_AUX_START_ID + 23) +#define KEEM_BAY_A53_AUX_USOC (KEEM_BAY_A53_AUX_START_ID + 24) +#define KEEM_BAY_A53_AUX_USOC_REF (KEEM_BAY_A53_AUX_START_ID + 25) +#define KEEM_BAY_A53_AUX_USOC_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 26) +#define KEEM_BAY_A53_AUX_MAX_ID (KEEM_BAY_A53_AUX_USOC_ALT_REF) + +/* PSS_CPR region CLK_ID: CLK_ID: 58 - 82 */ +#define KEEM_BAY_PSS_START_ID (KEEM_BAY_A53_AUX_MAX_ID + 1) +#define KEEM_BAY_PSS_I2C0 (KEEM_BAY_PSS_START_ID + 0) +#define KEEM_BAY_PSS_I2C1 (KEEM_BAY_PSS_START_ID + 1) +#define KEEM_BAY_PSS_I2C2 (KEEM_BAY_PSS_START_ID + 2) +#define KEEM_BAY_PSS_I2C3 (KEEM_BAY_PSS_START_ID + 3) +#define KEEM_BAY_PSS_I2C4 (KEEM_BAY_PSS_START_ID + 4) +#define KEEM_BAY_PSS_SD0 (KEEM_BAY_PSS_START_ID + 5) +#define KEEM_BAY_PSS_SD1 (KEEM_BAY_PSS_START_ID + 6) +#define KEEM_BAY_PSS_EMMC (KEEM_BAY_PSS_START_ID + 7) +#define KEEM_BAY_PSS_AXI_DMA (KEEM_BAY_PSS_START_ID + 8) +#define KEEM_BAY_PSS_SPI0 (KEEM_BAY_PSS_START_ID + 9) +#define KEEM_BAY_PSS_SPI1 (KEEM_BAY_PSS_START_ID + 10) +#define KEEM_BAY_PSS_SPI2 (KEEM_BAY_PSS_START_ID + 11) +#define KEEM_BAY_PSS_SPI3 (KEEM_BAY_PSS_START_ID + 12) +#define KEEM_BAY_PSS_I2S0 (KEEM_BAY_PSS_START_ID + 13) +#define KEEM_BAY_PSS_I2S1 (KEEM_BAY_PSS_START_ID + 14) +#define KEEM_BAY_PSS_I2S2 (KEEM_BAY_PSS_START_ID + 15) +#define KEEM_BAY_PSS_I2S3 (KEEM_BAY_PSS_START_ID + 16) +#define KEEM_BAY_PSS_UART0 (KEEM_BAY_PSS_START_ID + 17) +#define KEEM_BAY_PSS_UART1 (KEEM_BAY_PSS_START_ID + 18) +#define KEEM_BAY_PSS_UART2 (KEEM_BAY_PSS_START_ID + 19) +#define KEEM_BAY_PSS_UART3 (KEEM_BAY_PSS_START_ID + 20) +#define KEEM_BAY_PSS_I3C0 (KEEM_BAY_PSS_START_ID + 21) +#define KEEM_BAY_PSS_I3C1 (KEEM_BAY_PSS_START_ID + 22) +#define KEEM_BAY_PSS_I3C2 (KEEM_BAY_PSS_START_ID + 23) +#define KEEM_BAY_PSS_GBE (KEEM_BAY_PSS_START_ID + 24) +#define KEEM_BAY_PSS_MAX_ID (KEEM_BAY_PSS_GBE) + +/* PSS_CPR_AUX region. CLK_ID: 83 - 97 */ +#define KEEM_BAY_PSS_AUX_START_ID (KEEM_BAY_PSS_MAX_ID + 1) +#define KEEM_BAY_PSS_AUX_I2S0 (KEEM_BAY_PSS_AUX_START_ID + 0) +#define KEEM_BAY_PSS_AUX_I2S1 (KEEM_BAY_PSS_AUX_START_ID + 1) +#define KEEM_BAY_PSS_AUX_I2S2 (KEEM_BAY_PSS_AUX_START_ID + 2) +#define KEEM_BAY_PSS_AUX_I2S3 (KEEM_BAY_PSS_AUX_START_ID + 3) +#define KEEM_BAY_PSS_AUX_UART0 (KEEM_BAY_PSS_AUX_START_ID + 4) +#define KEEM_BAY_PSS_AUX_UART1 (KEEM_BAY_PSS_AUX_START_ID + 5) +#define KEEM_BAY_PSS_AUX_UART2 (KEEM_BAY_PSS_AUX_START_ID + 6) +#define KEEM_BAY_PSS_AUX_UART3 (KEEM_BAY_PSS_AUX_START_ID + 7) +#define KEEM_BAY_PSS_AUX_SD0 (KEEM_BAY_PSS_AUX_START_ID + 8) +#define KEEM_BAY_PSS_AUX_SD1 (KEEM_BAY_PSS_AUX_START_ID + 9) +#define KEEM_BAY_PSS_AUX_EMMC (KEEM_BAY_PSS_AUX_START_ID + 10) +#define KEEM_BAY_PSS_AUX_TRNG (KEEM_BAY_PSS_AUX_START_ID + 11) +#define KEEM_BAY_PSS_AUX_OCS (KEEM_BAY_PSS_AUX_START_ID + 12) +#define KEEM_BAY_PSS_AUX_GBE_PTP (KEEM_BAY_PSS_AUX_START_ID + 13) +#define KEEM_BAY_PSS_AUX_GBE_TX (KEEM_BAY_PSS_AUX_START_ID + 14) +#define KEEM_BAY_PSS_AUX_MAX_ID (KEEM_BAY_PSS_AUX_GBE_TX) + +/* DSS_CPR region. CLK_ID: 98 - 109 */ +#define KEEM_BAY_DSS_START_ID (KEEM_BAY_PSS_AUX_MAX_ID + 1) +#define KEEM_BAY_DSS_SYS (KEEM_BAY_DSS_START_ID + 0) +#define KEEM_BAY_DSS_DEC400 (KEEM_BAY_DSS_START_ID + 1) +#define KEEM_BAY_DSS_TSENSE (KEEM_BAY_DSS_START_ID + 2) +#define KEEM_BAY_DSS_BUS_0 (KEEM_BAY_DSS_START_ID + 3) +#define KEEM_BAY_DSS_CORE_0 (KEEM_BAY_DSS_START_ID + 4) +#define KEEM_BAY_DSS_REF_0 (KEEM_BAY_DSS_START_ID + 5) +#define KEEM_BAY_DSS_REF_BYP_0 (KEEM_BAY_DSS_START_ID + 6) +#define KEEM_BAY_DSS_BUS_1 (KEEM_BAY_DSS_START_ID + 7) +#define KEEM_BAY_DSS_CORE_1 (KEEM_BAY_DSS_START_ID + 8) +#define KEEM_BAY_DSS_REF_1 (KEEM_BAY_DSS_START_ID + 9) +#define KEEM_BAY_DSS_REF_BYP_1 (KEEM_BAY_DSS_START_ID + 10) +#define KEEM_BAY_DSS_MMU500 (KEEM_BAY_DSS_START_ID + 11) +#define KEEM_BAY_DSS_MAX_ID (KEEM_BAY_DSS_MMU500) + +/* USS_CPR region. CLK_ID: 110 - 116 */ +#define KEEM_BAY_USS_START_ID (KEEM_BAY_DSS_MAX_ID + 1) +#define KEEM_BAY_USS_SYS (KEEM_BAY_USS_START_ID + 0) +#define KEEM_BAY_USS_REF (KEEM_BAY_USS_START_ID + 1) +#define KEEM_BAY_USS_ALT_REF (KEEM_BAY_USS_START_ID + 2) +#define KEEM_BAY_USS_SUSPEND (KEEM_BAY_USS_START_ID + 3) +#define KEEM_BAY_USS_CORE (KEEM_BAY_USS_START_ID + 4) +#define KEEM_BAY_USS_LOW_JIT (KEEM_BAY_USS_START_ID + 5) +#define KEEM_BAY_USS_PHY_TST (KEEM_BAY_USS_START_ID + 6) +#define KEEM_BAY_USS_MAX_ID (KEEM_BAY_USS_PHY_TST) + +/* MSS_CPR region. CLK_ID: 117 - 129 */ +#define KEEM_BAY_MSS_START_ID (KEEM_BAY_USS_MAX_ID + 1) +#define KEEM_BAY_MSS_CPU (KEEM_BAY_MSS_START_ID + 0) +#define KEEM_BAY_MSS_CPU_DSU (KEEM_BAY_MSS_START_ID + 1) +#define KEEM_BAY_MSS_CPU_L2C (KEEM_BAY_MSS_START_ID + 2) +#define KEEM_BAY_MSS_CPU_ICB (KEEM_BAY_MSS_START_ID + 3) +#define KEEM_BAY_MSS_CPU_TIM (KEEM_BAY_MSS_START_ID + 4) +#define KEEM_BAY_MSS_JPGENC (KEEM_BAY_MSS_START_ID + 5) +#define KEEM_BAY_MSS_DTB (KEEM_BAY_MSS_START_ID + 6) +#define KEEM_BAY_MSS_BLT (KEEM_BAY_MSS_START_ID + 7) +#define KEEM_BAY_MSS_UPA (KEEM_BAY_MSS_START_ID + 8) +#define KEEM_BAY_MSS_NCE (KEEM_BAY_MSS_START_ID + 9) +#define KEEM_BAY_MSS_CV (KEEM_BAY_MSS_START_ID + 10) +#define KEEM_BAY_MSS_ISP (KEEM_BAY_MSS_START_ID + 11) +#define KEEM_BAY_MSS_CAM (KEEM_BAY_MSS_START_ID + 12) +#define KEEM_BAY_MSS_MAX_ID (KEEM_BAY_MSS_CAM) + +/* MSS_CPR_AUX region. CLK_ID: 130 - 138 */ +#define KEEM_BAY_MSS_AUX_START_ID (KEEM_BAY_MSS_MAX_ID + 1) +#define KEEM_BAY_MSS_AUX_CIF (KEEM_BAY_MSS_AUX_START_ID + 0) +#define KEEM_BAY_MSS_AUX_LCD (KEEM_BAY_MSS_AUX_START_ID + 1) +#define KEEM_BAY_MSS_AUX_SLVDS0 (KEEM_BAY_MSS_AUX_START_ID + 2) +#define KEEM_BAY_MSS_AUX_SLVDS1 (KEEM_BAY_MSS_AUX_START_ID + 3) +#define KEEM_BAY_MSS_AUX_MIPI_TX0 (KEEM_BAY_MSS_AUX_START_ID + 4) +#define KEEM_BAY_MSS_AUX_MIPI_TX1 (KEEM_BAY_MSS_AUX_START_ID + 5) +#define KEEM_BAY_MSS_AUX_MIPI_ECFG (KEEM_BAY_MSS_AUX_START_ID + 6) +#define KEEM_BAY_MSS_AUX_MIPI_CFG (KEEM_BAY_MSS_AUX_START_ID + 7) +#define KEEM_BAY_MSS_AUX_JPGENC (KEEM_BAY_MSS_AUX_START_ID + 8) +#define KEEM_BAY_MSS_AUX_MAX_ID (KEEM_BAY_MSS_AUX_JPGENC) + +#define KEEM_BAY_NUM_CLOCKS (KEEM_BAY_MSS_AUX_MAX_ID + 1) + +#endif /* __DT_BINDINGS_KEEMBAY_CLOCKS_H */ From patchwork Tue Jul 14 16:13:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB72860D for ; Tue, 14 Jul 2020 16:13:49 +0000 (UTC) Received: by mail.kernel.org (Postfix) id A5D9E2251E; Tue, 14 Jul 2020 16:13:49 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 844982075B; Tue, 14 Jul 2020 16:13:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 844982075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: t3ZFXr+cWOJ55BiTQvjrPDgB2isca0D9pkq18HYv1yE5jZQpEQAqfJNCST5+pTWfUM7O+/IbTn zUTIs5yyNmCQ== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738135" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738135" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:49 -0700 IronPort-SDR: w02oRpL+zy/c4+nw16rV03VnHTGrSz40xWcmPlrviQAykU91o0+Mtr+DbOtNcYjXFn8CwLJexJ Ii7zVmI/uHug== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930577" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:45 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 4/7] dt-bindings: power: Add Keem Bay power domains Date: Tue, 14 Jul 2020 17:13:02 +0100 Message-Id: <20200714161305.836348-5-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add power domain dt-bindings for Keem Bay SoC. Signed-off-by: Daniele Alessandrelli --- include/dt-bindings/power/keembay-power.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/power/keembay-power.h diff --git a/include/dt-bindings/power/keembay-power.h b/include/dt-bindings/power/keembay-power.h new file mode 100644 index 000000000000..1385c42f897d --- /dev/null +++ b/include/dt-bindings/power/keembay-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2020 Intel Corporation. + * + * Device tree defines for power domains in Keem Bay. + */ + +#ifndef __DT_BINDINGS_KEEMBAY_POWER_H +#define __DT_BINDINGS_KEEMBAY_POWER_H + +#define KEEM_BAY_PSS_POWER_DOMAIN 0 +#define KEEM_BAY_MSS_CPU_POWER_DOMAIN 1 +#define KEEM_BAY_VDEC_POWER_DOMAIN 2 +#define KEEM_BAY_VENC_POWER_DOMAIN 3 +#define KEEM_BAY_PCIE_POWER_DOMAIN 4 +#define KEEM_BAY_USS_POWER_DOMAIN 5 +#define KEEM_BAY_MSS_CAM_POWER_DOMAIN 6 + +#endif /* __DT_BINDINGS_KEEMBAY_POWER_H */ From patchwork Tue Jul 14 16:13:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31717722 for ; Tue, 14 Jul 2020 16:13:54 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 2D3682253A; Tue, 14 Jul 2020 16:13:54 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 02B412075B; Tue, 14 Jul 2020 16:13:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 02B412075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: SkoJ2QUwgimzB4ZqrX/UyDL3BfOd16scMu50H+9sGP4Qm1uO+6Ln1j5PRjrjSfXFJPo8sHsw1W HKrzWDMEHvvw== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738151" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738151" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:53 -0700 IronPort-SDR: v6TE1gIQVEZ9VPhhOjH/H2OxprPTbe0IVhPdt7ialG5gyYQbE4G7GMYeOj9NnkrfcNi4uw1/HN 3WLZyjFaflFw== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930605" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:49 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 5/7] MAINTAINERS: Add maintainers for Keem Bay SoC Date: Tue, 14 Jul 2020 17:13:03 +0100 Message-Id: <20200714161305.836348-6-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add maintainers for the new Intel Movidius SoC code-named Keem Bay. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b4a43a9e7fbc..b151d0fc0588 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1954,6 +1954,14 @@ F: drivers/irqchip/irq-ixp4xx.c F: include/linux/irqchip/irq-ixp4xx.h F: include/linux/platform_data/timer-ixp4xx.h +ARM/INTEL KEEMBAY ARCHITECTURE +M: Paul J. Murphy +M: Daniele Alessandrelli +S: Maintained +F: Documentation/devicetree/bindings/arm/keembay.yaml +F: include/dt-bindings/clock/keembay-clocks.h +F: include/dt-bindings/power/keembay-power.h + ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT M: Jonathan Cameron L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) From patchwork Tue Jul 14 16:13:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6923F60D for ; Tue, 14 Jul 2020 16:13:58 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6249F2077D; Tue, 14 Jul 2020 16:13:58 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 373F42075B; Tue, 14 Jul 2020 16:13:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 373F42075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: kATczkTALWGnAA6sjXceppjaehsDoct4L7UQXzrBORxvY7tyHcOoTZ2orhin3v/BVtYeumSr9R 8YyK+RTKVKSA== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738162" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738162" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:57 -0700 IronPort-SDR: F1mVtnAzisnmV70Pv7CVDD1755nVp3KgQKYxi/unxQaaDlySYph8n4NjcQlOVEq1M4MDymjbiw LmSD7683LDLQ== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930637" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:53 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 6/7] arm64: dts: keembay: Add device tree for Keem Bay SoC Date: Tue, 14 Jul 2020 17:13:04 +0100 Message-Id: <20200714161305.836348-7-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add initial device tree for Intel Movidius SoC code-named Keem Bay. This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI, and PMU. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/keembay-soc.dtsi | 125 +++++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index b151d0fc0588..e5019c8487c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-soc.dtsi F: include/dt-bindings/clock/keembay-clocks.h F: include/dt-bindings/power/keembay-power.h diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi new file mode 100644 index 000000000000..57c67621ed63 --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation. + * + * Device tree describing Keem Bay SoC. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@20500000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ + <0x0 0x20580000 0x0 0x80000>; /* GICR */ + /* VGIC maintenance interrupt */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Secure, non-secure, virtual, and hypervisor */ + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@20150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20150000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@20160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20160000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20170000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@20180000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20180000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; From patchwork Tue Jul 14 16:13:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4946860D for ; Tue, 14 Jul 2020 16:14:02 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 440162256C; Tue, 14 Jul 2020 16:14:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 202502075B; Tue, 14 Jul 2020 16:14:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 202502075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: eMt4pwDdZKjjKAyu9u0vqbDbvC7wnvJl/l/LjhGEcfSa3aDs1i2HUSYQvgZvGJLkDeM9w19VbG S4ITwv0uEfeQ== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738175" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738175" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:14:01 -0700 IronPort-SDR: YoYpBnEiN3Dfedauaiu+6j3BNJQGN3i61PoL1iDQZLUkDe3JUpmP99k830N2VRoHiT9Op8nd5u vUg/MCV4vSRA== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930668" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:58 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 7/7] arm64: dts: keembay: Add device tree for Keem Bay EVM board Date: Tue, 14 Jul 2020 17:13:05 +0100 Message-Id: <20200714161305.836348-8-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add initial device tree for Keem Bay EVM board. With this minimal device tree the board boots fine using an initramfs image. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/keembay-evm.dts | 39 +++++++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts diff --git a/MAINTAINERS b/MAINTAINERS index e5019c8487c8..bcda93691026 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi F: include/dt-bindings/clock/keembay-clocks.h F: include/dt-bindings/power/keembay-power.h diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 40cb16e8c814..296eceec4276 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb +dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts new file mode 100644 index 000000000000..347debb9c269 --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-evm.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation + * + * Device tree describing Keem Bay EVM board. + */ + +/dts-v1/; + +#include "keembay-soc.dtsi" +#include +#include + +/ { + model = "Keem Bay EVM"; + compatible = "intel,keembay-evm", "intel,keembay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2GB of DDR memory. */ + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + +}; + +&uart3 { + status = "okay"; +};