From patchwork Thu Jul 16 02:28:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666515 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6462A60D for ; Thu, 16 Jul 2020 02:28:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BD9520663 for ; Thu, 16 Jul 2020 02:28:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sQUaD3sx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727891AbgGPC22 (ORCPT ); Wed, 15 Jul 2020 22:28:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726479AbgGPC20 (ORCPT ); Wed, 15 Jul 2020 22:28:26 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE19AC061755; Wed, 15 Jul 2020 19:28:25 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id c80so8102502wme.0; Wed, 15 Jul 2020 19:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yQxWpRgQb3Xq+P5ehR8ew7q9vK97Ab3OJ4StJNb/DKE=; b=sQUaD3sxXAOsgpgXKFdUKklgmD4CXtwOkV7jyW3ViR7K1en83so42tP33suhyvxZV4 6UBoH/sec3Mh3IfEqQZ4cDZj2Aiq1kvH0BlftUAHU1mkW6Mzcw393JB0LXs8/8M2YKqd Y2/MwZisQQciHc7lvhD2hKOyHmlAfJjiVrs/FeqLQmZtCZXz3IXvfqgSXQIj4tNCj/P7 rwvYtzwzvAo4Fh/Q6iSwc3sKPwo3d+ZhTbygMA342wsY4IadEb6IHE4oBKBRvU8YjfoP VN31huP7ZMYfkV3wtq1qb8k46cIOB3IBGKI4hLYngVmax2rnEjJ14qTKVBr5evDeusZn 8O4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yQxWpRgQb3Xq+P5ehR8ew7q9vK97Ab3OJ4StJNb/DKE=; b=r2sVLSKH9XFCUVxkr937Eqe+jFSXVC1qG/9J29k97hbJ0p4oEL/4Vfne4AQDrUPGjE H2WKQJ95xNRqOzLLdLRwLwizxd5ojXT9GGIPXqH77jmFEx3lCbyZ2mj3Ao1afgBp/F09 ZomqNtnaGPJVuzvUIwV14SPOQ4MuSRH3xhWAzdII/FMLgtkusLQRBjPX72UmWPrexZkD WVqadiK2gAPDyYPKcK2rr/EdGdZRIiFygmGELAz6n8kvLxiOAU/86n6hYcYTOej2tY2P uC0iqB6e6ySj5PiOyV2ZNnq+NRQzvB3RtyCxMK7LjsFaTYc1C1iWnpl2RKXcuOV5HJYe 4tbA== X-Gm-Message-State: AOAM530jYze2trPYSL860W5PmPkxNN5TbeHfak2+eLQNAa2gcb4Su+YW n5DNLcpy3lrziDdtHUnHn5cgvssmYYOn2g== X-Google-Smtp-Source: ABdhPJxAua1mxkgJpGb2tuSl/qOly9wfNZ+5kc8eLGAa+eDIfH2KrQTsZPHVf7buVqvTfZOlRaX6/Q== X-Received: by 2002:a1c:7c19:: with SMTP id x25mr2201470wmc.176.1594866504470; Wed, 15 Jul 2020 19:28:24 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:23 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 1/7] ipq806x: gcc: add support for child probe Date: Thu, 16 Jul 2020 04:28:10 +0200 Message-Id: <20200716022817.30439-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for child probing needed for tsens driver that share the seme regs of gcc for this platform. Signed-off-by: Ansuel Smith Reviewed-by: Amit Kucheria --- drivers/clk/qcom/gcc-ipq806x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a8456e09c44d..d6b7adb4be38 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3089,7 +3089,7 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) regmap_write(regmap, 0x3cf8, 8); regmap_write(regmap, 0x3d18, 8); - return 0; + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); } static struct platform_driver gcc_ipq806x_driver = { From patchwork Thu Jul 16 02:28:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666511 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C02F60D for ; Thu, 16 Jul 2020 02:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8435C20791 for ; Thu, 16 Jul 2020 02:28:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l8cR4NU5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727981AbgGPC2d (ORCPT ); Wed, 15 Jul 2020 22:28:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727883AbgGPC22 (ORCPT ); Wed, 15 Jul 2020 22:28:28 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AE9EC061755; Wed, 15 Jul 2020 19:28:28 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id a6so5249936wrm.4; Wed, 15 Jul 2020 19:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NMGpsGsTomyvbhuxUBbF2KBZ5U7/Gj4W0Zm7Cz/Tuck=; b=l8cR4NU56aOZ3mHbYkRDNMhvVeRyLGj1gne9YoLCdF45QWddvdGfSTQoVMt4jSHnan sD1BLjXjlUbcUyWf9KYEzw7XkXdBpsv/zXhJ4UZo+23E8TX9y7iWGrxxPviqy76fCR20 an/vgp6jlxa1LmK+X6s6ZfZxdkqae5svzQAb33Po1C8G8E98cUFjxVomblId6v8P+LtI ppkeAMnCIc6DNCYcG3RLxrqglDo/pD1AxP4IgXlwr7CNu8Z92t0C52OnRYLi/PLpbgV/ tGMlzNoEoIyBrghcBIAZYgrUFK8AOzG05tFHDd4bh/rfq83JNqZI1JwpQbRSJBG65sO7 DQDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NMGpsGsTomyvbhuxUBbF2KBZ5U7/Gj4W0Zm7Cz/Tuck=; b=OckZ1HD/sZke8VDowamon4DymowUkxPa5TSZguOYNffk/OiGoA0RLeED17kQN0KZXM qG28hqax8BSLURGhoDc5MVEZsVRMfGmhanrCrlowtsc0MHdoni/hEgWRZJvBslYDKdr7 q3Za3RUtG7+ZibHznouhhPqFWSgPMbx0LSAxgiJo8ZNmZuh67ZUPa6SHYbriUJIxJprF Cv1ysY+l23cOCzSIS7wxvUGz0shbOquzn4K8KoITjzeU7ZrAKb+Oq7eS6nZDYSktYyoo nHHuEsApfTP0fYouAfv8MaO6RWJgLJfZxLMXTL+YHr3LXrMhVh87y9ZbNK4IdvZ/o6gt MHYg== X-Gm-Message-State: AOAM531w4MR8OblfKA2biQSrU9KJa/qwK53cQNwuKSznq5dkquVEVPRf CFblrJvfo6KqITVtj7UyuZU= X-Google-Smtp-Source: ABdhPJxJAsBtiMpZ3+Al418gUaONCeToX/sTi4riGXieRkPadBAWYCNCqBF6C+rfo4Gp8wicLCmFNg== X-Received: by 2002:adf:e9c4:: with SMTP id l4mr2644495wrn.9.1594866506692; Wed, 15 Jul 2020 19:28:26 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:26 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 2/7] drivers: thermal: tsens: try load regmap from parent for 8960 Date: Thu, 16 Jul 2020 04:28:11 +0200 Message-Id: <20200716022817.30439-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Devices based on 8060 tsens driver (ipq8064) use the reg of the gcc driver. Try to load the regmap of the parent as they share the same regs. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2a28a5af209e..45788eb3c666 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -168,8 +169,17 @@ static int init_8960(struct tsens_priv *priv) u32 reg_cntl; priv->tm_map = dev_get_regmap(priv->dev, NULL); - if (!priv->tm_map) + if (!priv->tm_map) { + struct device *parent = priv->dev->parent; + + if (parent) + priv->tm_map = syscon_node_to_regmap(parent->of_node); + } + + if (!priv->tm_map || IS_ERR(priv->tm_map)) { + dev_err(priv->dev, "failed to get tsens regmap\n"); return -ENODEV; + } /* * The status registers for each sensor are discontiguous From patchwork Thu Jul 16 02:28:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11A0113B1 for ; Thu, 16 Jul 2020 02:28:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE5C320787 for ; Thu, 16 Jul 2020 02:28:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BJCEiCgj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728116AbgGPC2y (ORCPT ); Wed, 15 Jul 2020 22:28:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726479AbgGPC2b (ORCPT ); Wed, 15 Jul 2020 22:28:31 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F6E9C061755; Wed, 15 Jul 2020 19:28:30 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id 22so8096058wmg.1; Wed, 15 Jul 2020 19:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jsnFEaPOATe0rU74z4wmdx5Snp9SyB/gn+FbmEyk+5U=; b=BJCEiCgjoizQk0MuwZnjC++IpUrRbuW2pdRAaA62MIRcfaclEvyOXR/tD9ejUx8GMS mF90akZODSnNpjz6Uv4bahWA3cNTRYJUF2aXKAsCNiWNRsllo/6WH5fXcXS2s0t4XrHX lzcNf/9rpffayJ8OKYukNpZHVJO/m1A8HBwouPwdkhMZlHWunkMej7lXrK1gJc8o+H5d URbglFqcIogn5Oj3ZKJdVO5cTaZMaQk5jGAP1KB+VVWMaCatsUOq+tyaQ99Bg78Jju41 wMxTLmnysHeG8DpPr9a0EHs1ezob1S+rOScTOxEALW9jw4oZfjilpq28K6UoEwCafva6 JGHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jsnFEaPOATe0rU74z4wmdx5Snp9SyB/gn+FbmEyk+5U=; b=NPAHDXY218eCwiUwzLshGJ4bp0tvHWjhcEvTCnFHTfuIRYNH8zHgi791DgJK3Hdjcz QNsKPu5czYgTXyNGsyJoEild7alFUzrQujAMmcxdbVDhuB0VKmwvSeH0Dbb+9U6PzcSc sqL3Uvm4041NRd3PyNOXSyLOXQonazQkWCXceYqD92+OgAWcsBehtkFSIdOvHLp9tHoB S4G2auskHd+HodUciACZcGrGnMQkdhe2taZhKPqW5JD91uShjHL9pgvxmLGtsb0XYxN1 mVzAs+Uj53U/Sega/4Xe2B/Lh0GeImZGmFUYYHyC+/S8o7oU3hKCjtt8bA2fNZRFfETd Q/vw== X-Gm-Message-State: AOAM530tTvTNceZdCm3jwrvgEeakYMLel1J2T20JU8JA0ySjpp0GZ71F GSBvWuDms3TQxwLYVcK1EHw= X-Google-Smtp-Source: ABdhPJzCJ+vAQ/QeXIWzlb11w/o7pwBiMD7vR0FI/Iqs4NB5SM67+6BkbQd4gbRfAjNy7ipBfFR+ig== X-Received: by 2002:a05:600c:2050:: with SMTP id p16mr2179009wmg.44.1594866508949; Wed, 15 Jul 2020 19:28:28 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:28 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 3/7] drivers: thermal: tsens: add ipq8064 support Date: Thu, 16 Jul 2020 04:28:12 +0200 Message-Id: <20200716022817.30439-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8064 SoCs based use the same 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 39c4462e38f6..23f63dfbf13d 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -906,6 +906,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,ipq8064-tsens", + .data = &data_8960, }, { .compatible = "qcom,tsens-v1", .data = &data_tsens_v1, From patchwork Thu Jul 16 02:28:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666509 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C59260D for ; Thu, 16 Jul 2020 02:28:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E759C20787 for ; Thu, 16 Jul 2020 02:28:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NUJwbD4b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727992AbgGPC2d (ORCPT ); Wed, 15 Jul 2020 22:28:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727953AbgGPC2d (ORCPT ); Wed, 15 Jul 2020 22:28:33 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71AA0C08C5CE; Wed, 15 Jul 2020 19:28:32 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id f2so5220944wrp.7; Wed, 15 Jul 2020 19:28:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ouNkdpPb5LfjBppsBgr8ZNpXkvCcGxxnoBprAfZ1JeY=; b=NUJwbD4b48yA748qorNGk8mt5nsIXUHIyHpnoxmWIRinCZ6FBETMVRSD5gIOnZXEOY rUcPq0zdodgSZqMsuqBjJmjqp9UrpaVHylgzNzhuQUEXSjQotQyiV9JZxRNWIvtLVKUV TOI14l3xGid7fvxKeqdHAFAUt4oW6PKTld7qK0XbbR2JcYQCbedypAyHFVcbXXSHM7af jp2mmvD7UPZ/lRE/i8jHCTN3REzZKfKanAKNrSbXa9a7mEVFaVPQn7mFDcLaw1mamx3C GqNN0LQGptOCrP4ug3au79t+bmzl3W47PfBS5eectliigSNqGF1hzUQrYCU9zlH0qf2C h27A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ouNkdpPb5LfjBppsBgr8ZNpXkvCcGxxnoBprAfZ1JeY=; b=i/RpcnzeOD3+j1GKhCHQyBCvaXOgUp4Pucay7T2P8OBwJQJrzkchf8GKZWu4GL8k7P 9hPUzl5qPS2X0DYWyg4aZPwchDTbMDr7fRZ9aM3h+MOAgeyiU/YzwR3tmGKI2XIody6y /EC8xbVQ9/PhvWyYMZ0P09GQ+QcUcOTLal3nFM1k03Yvj3sv8b5o0eiURAyu9mpIX/J8 YGTl327Z0A5GBiEiKnAa+OX4ZEYC9JH2nEn4WcfeshvH11YQbUqlwMdkJ0iKw7Qonm29 VvlxbyWf5uPqE006h3z+YmbS63+sPX39j5jrFDX7nt7slqIjHHfYzVfU0j0Di9JU7c2c mPnA== X-Gm-Message-State: AOAM5339bpPsPEK4KBjHKijl/saMKnq04WWljjdH/wuTCPL6Qr6+R6tC HCP73nBOGMZpFpX5L2zrCEU= X-Google-Smtp-Source: ABdhPJysNLgbJu3gRayL8Us7KD5d8xyX0ogQIzyEFvTbZesH0MDVoIytceedClvHrEbThBKzWZfvSQ== X-Received: by 2002:adf:fa8f:: with SMTP id h15mr2536857wrr.211.1594866511110; Wed, 15 Jul 2020 19:28:31 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:30 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 4/7] dt-bindings: thermal: tsens: document ipq8064 bindings Date: Thu, 16 Jul 2020 04:28:13 +0200 Message-Id: <20200716022817.30439-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the use of bindings used for ipq8064 SoCs tsens. ipq8064 use the same gcc regs and is set as a child of the qcom gcc. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- .../bindings/thermal/qcom-tsens.yaml | 50 ++++++++++++++++--- 1 file changed, 43 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index d7be931b42d2..9d480e3943a2 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -19,6 +19,11 @@ description: | properties: compatible: oneOf: + - description: msm9860 TSENS based + items: + - enum: + - qcom,ipq8064-tsens + - description: v0.1 of TSENS items: - enum: @@ -85,12 +90,18 @@ properties: Number of cells required to uniquely identify the thermal sensors. Since we have multiple sensors this is set to 1 +required: + - compatible + - interrupts + - "#thermal-sensor-cells" + allOf: - if: properties: compatible: contains: enum: + - qcom,ipq8064-tsens - qcom,msm8916-tsens - qcom,msm8974-tsens - qcom,msm8976-tsens @@ -111,17 +122,42 @@ allOf: interrupt-names: minItems: 2 -required: - - compatible - - reg - - "#qcom,sensors" - - interrupts - - interrupt-names - - "#thermal-sensor-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,tsens-v0_1 + - qcom,tsens-v1 + - qcom,tsens-v2 + + then: + required: + - reg + - interrupt-names + - "#qcom,sensors" additionalProperties: false examples: + - | + #include + // Example msm9860 based SoC (ipq8064): + gcc: clock-controller { + + /* ... */ + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + - | #include // Example 1 (legacy: for pre v1 IP): From patchwork Thu Jul 16 02:28:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666487 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32CC460D for ; Thu, 16 Jul 2020 02:28:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0DCDE20663 for ; Thu, 16 Jul 2020 02:28:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pZhYlrtB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728042AbgGPC2g (ORCPT ); Wed, 15 Jul 2020 22:28:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727953AbgGPC2f (ORCPT ); Wed, 15 Jul 2020 22:28:35 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7F24C061755; Wed, 15 Jul 2020 19:28:34 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id j4so5202686wrp.10; Wed, 15 Jul 2020 19:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mSvlat9xORR6lrMNI6X8ooEaAYNoChgOCjYIrjjizow=; b=pZhYlrtBh/x44ftft37uNFGNb0ubCCIuvaKS2qkGxu9LkOl5IzYqsSuhdvK0fUqmhL zkSlizK4x1TqWMXcaUPD06anfAei9Rj9lIfQ53izn0CbbTMUycPKHy7PeIWJ0AHrKaht o4ATfRU0vOoST2Le3fVl15CgN51mrZ5g2sXEnQ4TPqO6SQ7jnMWzIN82IS+cqRSlYQke 4ZSpLP8ODfaAcxo20Hslmo06gm4w0MyGithHB9KBGryHQgS898ihq9gCXNdAzPS455qb 7Lp5cO+ZgdrlsLhQIASUUBQhC9zFfIkafsnEvO6zOzxJqqXRhI6o9DzleRX2ZkGH0eME ccww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mSvlat9xORR6lrMNI6X8ooEaAYNoChgOCjYIrjjizow=; b=qSiCFbp8byEHZtYxhNzfIj6GWm4XWalAtYeu2IOYQ7LVRnvQe+42YLiOavEViAR4iy dgfC8jGQOYKqZfSclZjkuILqoFmpbt/yxTImYfJVIXeXa3PUpps1+miJINWDkaANo0Vb 6OCZZRtITb0YPC6cfBGLdrUaKpIZbh9P37jYiDcU5WD4Nlc0Cs4SbD4kCtV7lDyFi62w DTQhjVFIITOXXyqLOQkaKD6aZ38qSGYQd9YFD5BZm2gHr/deG/BhPKYhcrCscSocC9zD q8FAAKH9FW7tWXkFpoCQgcvSFOTBCbPXWI/T7KFWkhPIA1x94ZUBi0kKwtl/cVuS8mgS tQrA== X-Gm-Message-State: AOAM530XjX7JxZaXp09mBpPwZLGAeTgLku3+/m6Kd/e/eqCUZhLwXt/q jInISPAAtCf6n+A79k+iNvU= X-Google-Smtp-Source: ABdhPJyY4lU4a5JpAxE7eApHgQF4F34KKaceKqFTlzcJdAkE1XIHJwhb5ioIUDj1Jcc9KGsfwTTInA== X-Received: by 2002:a5d:608f:: with SMTP id w15mr2472701wrt.136.1594866513351; Wed, 15 Jul 2020 19:28:33 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:32 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 5/7] drivers: thermal: tsens: add interrupt support for 9860 driver Date: Thu, 16 Jul 2020 04:28:14 +0200 Message-Id: <20200716022817.30439-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt support for 9860 tsens driver used to set thermal trip point for the system. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 197 +++++++++++++++++++++++++++--- drivers/thermal/qcom/tsens.h | 3 + 2 files changed, 186 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 45788eb3c666..20d0bfb10f1f 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -27,7 +28,6 @@ /* CNTL_ADDR bitmasks */ #define EN BIT(0) #define SW_RST BIT(1) -#define SENSOR0_EN BIT(3) #define SLP_CLK_ENA BIT(26) #define SLP_CLK_ENA_8660 BIT(24) #define MEASURE_PERIOD 1 @@ -41,14 +41,26 @@ #define THRESHOLD_ADDR 0x3624 /* THRESHOLD_ADDR bitmasks */ +#define THRESHOLD_MAX_CODE 0x20000 +#define THRESHOLD_MIN_CODE 0 #define THRESHOLD_MAX_LIMIT_SHIFT 24 #define THRESHOLD_MIN_LIMIT_SHIFT 16 #define THRESHOLD_UPPER_LIMIT_SHIFT 8 #define THRESHOLD_LOWER_LIMIT_SHIFT 0 +#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MAX_LIMIT_SHIFT) +#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MIN_LIMIT_SHIFT) +#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_UPPER_LIMIT_SHIFT) +#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_LOWER_LIMIT_SHIFT) /* Initial temperature threshold values */ -#define LOWER_LIMIT_TH 0x50 -#define UPPER_LIMIT_TH 0xdf +#define LOWER_LIMIT_TH_8960 0x50 +#define UPPER_LIMIT_TH_8960 0xdf +#define LOWER_LIMIT_TH_8064 0x9d /* 95C */ +#define UPPER_LIMIT_TH_8064 0xa6 /* 105C */ #define MIN_LIMIT_TH 0x0 #define MAX_LIMIT_TH 0xff @@ -57,6 +69,170 @@ #define TRDY_MASK BIT(7) #define TIMEOUT_US 100 +#define TSENS_EN BIT(0) +#define TSENS_SW_RST BIT(1) +#define TSENS_ADC_CLK_SEL BIT(2) +#define SENSOR0_EN BIT(3) +#define SENSOR1_EN BIT(4) +#define SENSOR2_EN BIT(5) +#define SENSOR3_EN BIT(6) +#define SENSOR4_EN BIT(7) +#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \ + SENSOR2_EN | SENSOR3_EN | SENSOR4_EN) +#define TSENS_8064_SENSOR5_EN BIT(8) +#define TSENS_8064_SENSOR6_EN BIT(9) +#define TSENS_8064_SENSOR7_EN BIT(10) +#define TSENS_8064_SENSOR8_EN BIT(11) +#define TSENS_8064_SENSOR9_EN BIT(12) +#define TSENS_8064_SENSOR10_EN BIT(13) +#define TSENS_8064_SENSORS_EN (SENSORS_EN | \ + TSENS_8064_SENSOR5_EN | \ + TSENS_8064_SENSOR6_EN | \ + TSENS_8064_SENSOR7_EN | \ + TSENS_8064_SENSOR8_EN | \ + TSENS_8064_SENSOR9_EN | \ + TSENS_8064_SENSOR10_EN) + +u32 tsens_8960_slope[] = { + 1176, 1176, 1154, 1176, + 1111, 1132, 1132, 1199, + 1132, 1199, 1132 + }; + +/* Temperature on y axis and ADC-code on x-axis */ +static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return adc_code * slope + offset; +} + +static void notify_uspace_tsens_fn(struct work_struct *work) +{ + struct tsens_sensor *s = container_of(work, struct tsens_sensor, + notify_work); + + sysfs_notify(&s->tzd->device.kobj, NULL, "type"); +} + +static void tsens_scheduler_fn(struct work_struct *work) +{ + struct tsens_priv *priv = + container_of(work, struct tsens_priv, tsens_work); + unsigned int threshold, threshold_low, code, reg, sensor; + unsigned long mask; + bool upper_th_x, lower_th_x; + int ret; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR; + ret = regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg); + if (ret) + return; + + mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR); + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold); + if (ret) + return; + threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK) >> + THRESHOLD_LOWER_LIMIT_SHIFT; + threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK) >> + THRESHOLD_UPPER_LIMIT_SHIFT; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + + ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor); + if (ret) + return; + sensor &= (uint32_t)TSENS_8064_SENSORS_EN; + sensor >>= SENSOR0_SHIFT; + + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + + /* Skip if the sensor is disabled */ + if (sensor & 1) { + ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code); + if (ret) + return; + upper_th_x = code >= threshold; + lower_th_x = code <= threshold_low; + if (upper_th_x) + mask |= UPPER_STATUS_CLR; + if (lower_th_x) + mask |= LOWER_STATUS_CLR; + if (upper_th_x || lower_th_x) { + /* Notify user space */ + schedule_work(&priv->sensor[0].notify_work); + pr_debug("Trigger (%d degrees) for sensor %d\n", + code_to_mdegC(code, &priv->sensor[0]), 0); + } + } + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg & mask); +} + +static irqreturn_t tsens_isr(int irq, void *data) +{ + struct tsens_priv *priv = data; + + schedule_work(&priv->tsens_work); + return IRQ_HANDLED; +} + +static void hw_init(struct tsens_priv *priv) +{ + int ret; + unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0; + unsigned int reg_status_cntl = 0; + + regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST); + + reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18) | + (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_status_cntl); + reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR | + MIN_STATUS_MASK | MAX_STATUS_MASK; + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg_status_cntl); + reg_cntl |= TSENS_EN; + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + + regmap_read(priv->tm_map, CONFIG_ADDR, ®_cfg); + if (priv->num_sensors > 1) + reg_cfg = (reg_cfg & ~CONFIG_MASK) | CONFIG; + else + reg_cfg = (reg_cfg & ~CONFIG_MASK) | + (CONFIG << CONFIG_SHIFT_8660); + regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg); + + reg_thr |= (LOWER_LIMIT_TH_8064 << THRESHOLD_LOWER_LIMIT_SHIFT) | + (UPPER_LIMIT_TH_8064 << THRESHOLD_UPPER_LIMIT_SHIFT) | + (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT) | + (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT); + + regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr); + + ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr, + IRQF_TRIGGER_RISING, "tsens_interrupt", priv); + if (ret < 0) { + dev_err(priv->dev, "request_irq FAIL: %d", ret); + return; + } + + INIT_WORK(&priv->tsens_work, tsens_scheduler_fn); +} + static int suspend_8960(struct tsens_priv *priv) { int ret; @@ -191,6 +367,8 @@ static int init_8960(struct tsens_priv *priv) if (i >= 5) priv->sensor[i].status = S0_STATUS_ADDR + 40; priv->sensor[i].status += i * 4; + priv->sensor[i].slope = tsens_8960_slope[i]; + INIT_WORK(&priv->sensor[i].notify_work, notify_uspace_tsens_fn); } reg_cntl = SW_RST; @@ -241,18 +419,9 @@ static int calibrate_8960(struct tsens_priv *priv) kfree(data); - return 0; -} - -/* Temperature on y axis and ADC-code on x-axis */ -static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) -{ - int slope, offset; + hw_init(priv); - slope = thermal_zone_get_slope(s->tzd); - offset = CAL_MDEGC - slope * s->offset; - - return adc_code * slope + offset; + return 0; } static int get_temp_8960(const struct tsens_sensor *s, int *temp) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 59d01162c66a..e66048fabcc7 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -48,6 +48,7 @@ enum tsens_irq_type { struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; + struct work_struct notify_work; int offset; unsigned int hw_id; int slope; @@ -559,6 +560,7 @@ struct tsens_priv { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + u32 tsens_irq; /* lock for upper/lower threshold interrupts */ spinlock_t ul_lock; @@ -568,6 +570,7 @@ struct tsens_priv { struct tsens_features *feat; const struct reg_field *fields; const struct tsens_ops *ops; + struct work_struct tsens_work; struct dentry *debug_root; struct dentry *debug; From patchwork Thu Jul 16 02:28:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666499 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AAA213A4 for ; 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[87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:35 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 6/7] drivers: thermal: tsens: add support for custom set_trip function Date: Thu, 16 Jul 2020 04:28:15 +0200 Message-Id: <20200716022817.30439-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 8960 tsens driver have a custom implementation to set set_trip function. Permit the generic driver to use the custom function if provided. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 4 ++++ drivers/thermal/qcom/tsens.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 23f63dfbf13d..5f49f4117610 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -530,6 +530,10 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + // Use the driver set_trips if present + if (priv->ops->set_trip_temp) + return priv->ops->set_trip_temp(_sensor, low, high); + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index e66048fabcc7..4f0ab4aa5fd1 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -65,6 +65,7 @@ struct tsens_sensor { * @suspend: Function to suspend the tsens device * @resume: Function to resume the tsens device * @get_trend: Function to get the thermal/temp trend + * @set_trip_temp: Function to get trip temp */ struct tsens_ops { /* mandatory callbacks */ @@ -77,6 +78,7 @@ struct tsens_ops { int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); + int (*set_trip_temp)(void *data, int trip, int temp); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ From patchwork Thu Jul 16 02:28:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666495 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC1E260D for ; Thu, 16 Jul 2020 02:28:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D89320787 for ; Thu, 16 Jul 2020 02:28:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IqzVrO6b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728097AbgGPC2k (ORCPT ); Wed, 15 Jul 2020 22:28:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727953AbgGPC2j (ORCPT ); Wed, 15 Jul 2020 22:28:39 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80B05C061755; Wed, 15 Jul 2020 19:28:39 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id 17so8699533wmo.1; Wed, 15 Jul 2020 19:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ESxPvjOg/M0b94Gq1OGqi1pUcN1nE3zYRLLlIkcJLwU=; b=IqzVrO6bpFVJMnKF2Iy149n7Mgr+SnjSUNZjbbTDQENDIMhpAVei/3t/9kzQdXzyqF xIkY5biSBqPjVD46aTsOWllm34DxiezGe+KNDf5vWNPuy0HdRmhfMHzYnpoY8sYG3V1U yKCnUG+IYmkIOIYQ7ZuXcO0qWcn7isGFvCkdQbplnbOr5dkC84McFxAxY6N/eDmeMNzf oKdvs0SseOkLD9okfGLuNKh+ZIqI/CNnetsYAaFm4RRXt0mqByA5VK+3KKVvqVnGaKcX 7WINjQRjF2J7akzU21GZhv9MR4AWDiYrZksfG82Jm7SWdMbXutCxjNbANM9Dy4mVUBSG Xuog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ESxPvjOg/M0b94Gq1OGqi1pUcN1nE3zYRLLlIkcJLwU=; b=jBDmgEOWYQLiJT3idNFnvasexj/32GsSByPNhJtIZOdGo6mPeAVLCUFw6KzCV4hUUr 0YdouUxDcBks5R4sVJ/YYc0QX0W/Igb8LfmeUgNLMIgA1lGWWfuOckp2qWpisxtg4sF2 fVMgKNvZtp5a5jfGzAx9dzQZ6v3OxsIro3odgMRglMTa6w2dnTjM6nuUlpODrqb8RnGv T5WbdV4iHgkF11I+IZ3GVeO0OqvXVuxXjENPUeAD6c9x8zGcOeFD0X6Gw3jg0g4kGtqL W87yu5+f8VafBwdLKdpb4j57yfxcQ62knv/V1+qxa27EwFu+Ym0GsHhRRMkZPgfDOzRT fjIA== X-Gm-Message-State: AOAM530pyGgB6sq/6x3kLV/tXb8L/gOhhdrc3JO5Rs5eyJhGMH7DBrUv Tok9MLa9eRoCMghBx6cQpag= X-Google-Smtp-Source: ABdhPJxKEIBLPZoqyV04U9TIOoADK3i9+srFiq66flMSuILK932X+QGrfSNjtvMsCX01JN7SgV/sUw== X-Received: by 2002:a1c:7d85:: with SMTP id y127mr2277029wmc.181.1594866518123; Wed, 15 Jul 2020 19:28:38 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id u1sm7477611wrb.78.2020.07.15.19.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 19:28:37 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 7/7] drivers: thermal: tsens: add set_trip support for 8960 Date: Thu, 16 Jul 2020 04:28:16 +0200 Message-Id: <20200716022817.30439-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716022817.30439-1-ansuelsmth@gmail.com> References: <20200716022817.30439-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add custom set_trip function for 8960 needed to set trip point to the tsens driver for 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 20d0bfb10f1f..4ad65ab3fd18 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -93,6 +93,15 @@ TSENS_8064_SENSOR9_EN | \ TSENS_8064_SENSOR10_EN) +/* Trips: from very hot to very cold */ +enum tsens_trip_type { + TSENS_TRIP_STAGE3 = 0, + TSENS_TRIP_STAGE2, + TSENS_TRIP_STAGE1, + TSENS_TRIP_STAGE0, + TSENS_TRIP_NUM, +}; + u32 tsens_8960_slope[] = { 1176, 1176, 1154, 1176, 1111, 1132, 1132, 1199, @@ -110,6 +119,16 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } +static int mdegC_to_code(int degC, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return degC / slope - offset; +} + static void notify_uspace_tsens_fn(struct work_struct *work) { struct tsens_sensor *s = container_of(work, struct tsens_sensor, @@ -448,6 +467,64 @@ static int get_temp_8960(const struct tsens_sensor *s, int *temp) return -ETIMEDOUT; } +static int set_trip_temp_ipq8064(void *data, int trip, int temp) +{ + unsigned int reg_th, reg_cntl; + int ret, code, code_chk, hi_code, lo_code; + const struct tsens_sensor *s = data; + struct tsens_priv *priv = s->priv; + + code = mdegC_to_code(temp, s); + code_chk = code; + + if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE) + return -EINVAL; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_cntl); + if (ret) + return ret; + + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, ®_th); + if (ret) + return ret; + + hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK) + >> THRESHOLD_UPPER_LIMIT_SHIFT; + lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK) + >> THRESHOLD_LOWER_LIMIT_SHIFT; + + switch (trip) { + case TSENS_TRIP_STAGE3: + code <<= THRESHOLD_MAX_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MAX_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE2: + if (code_chk <= lo_code) + return -EINVAL; + code <<= THRESHOLD_UPPER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE1: + if (code_chk >= hi_code) + return -EINVAL; + code <<= THRESHOLD_LOWER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE0: + code <<= THRESHOLD_MIN_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MIN_LIMIT_MASK; + break; + default: + return -EINVAL; + } + + ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code); + if (ret) + return ret; + + return 0; +} + static const struct tsens_ops ops_8960 = { .init = init_8960, .calibrate = calibrate_8960, @@ -456,6 +533,7 @@ static const struct tsens_ops ops_8960 = { .disable = disable_8960, .suspend = suspend_8960, .resume = resume_8960, + .set_trip_temp = set_trip_temp_ipq8064, }; struct tsens_plat_data data_8960 = {