From patchwork Fri Jul 17 17:53:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 11671005 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A67F413B4 for ; Fri, 17 Jul 2020 17:54:01 +0000 (UTC) Received: by mail.kernel.org (Postfix) id A1B692064C; Fri, 17 Jul 2020 17:54:01 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 555B9206BE for ; Fri, 17 Jul 2020 17:54:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="wM01pNSz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 555B9206BE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=khilman@baylibre.com Received: by mail-pg1-f195.google.com with SMTP id g67so7041470pgc.8 for ; Fri, 17 Jul 2020 10:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version; bh=E9hq8CqUTj530zDCzvMGDTVcdgafjGzDVPGnVfYH7VY=; b=wM01pNSzjiRmCpYS7G3KVJ+XvBgMHNXAWWu/0Xl/rx7gD0Pm8lItpCfdi+PwMD7q0Y xCbIdARnGbtuTYL+62Es6FNu4aaRQuvuRwGURnT7zH3x45lgVqUNJ2RHduQ7K/ueyaQo e+jlCZzDtQL4o9/se4IihN8GDxXDF7IPpLyHUYLazUgmHSvEUBeD8nxwdQUxwq3XWQ4w fLSzCMvyabaGiAaI2wUER/L5keUnkBLcqxQ14WLtaM2x0ILhwLW0O74fCIEgtg5+GOc8 L1NZVMaK6Ez3bep2B6exKpLFnYZoGoupnmHNJH8LuJo133EchbIwvCB6FVJN9HJTl8eV NYDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version; bh=E9hq8CqUTj530zDCzvMGDTVcdgafjGzDVPGnVfYH7VY=; b=iALarFkMbw2jBfMw/P8/0V1SvGbu5ekO5dGXLW0apm4UCyu5P5ZwmvkO1tutUFkFIE PS8ktiL0I7M9zORwlHSqVt7vSsUo/yKnTzqYEB8Mfjx3bd/PtzI1ZJ3eOHWIdEB6a8nc mYsBIMUoHhgz3Wqfy4d0/SNY3gUCMAn6KHD5SBjEHZ2qERRwBeY0efZMvZRG4jBMMWbh L+s1jc/FdPa4gDj9teLy9h05TH3FfbCch7vcF2ADcSAJclqGJdJwMtjQmN1c1hzEve0C L3MtgUAJKp9zuU6E+hH8OawlCb8LsBu/+8RlNfP1t2wyW7yNXDBRSEVblZIAGqqGUTvx rS+g== X-Gm-Message-State: AOAM530YobvcfJdEsrMftgMJmThnUXjt8DxlrbeCUsiichpDcCnPNext otDEBhWs4UuQssznKqOE5mYeeKEGws8RrA== X-Google-Smtp-Source: ABdhPJydbT+xhJ7q3Cu7yRpCP0d6TnCk2BSkQo9w1zj27UCfThHXvFdWFIgX53CZbdu6F77JC5F8RA== X-Received: by 2002:aa7:98c6:: with SMTP id e6mr9150871pfm.17.1595008440370; Fri, 17 Jul 2020 10:54:00 -0700 (PDT) Received: from localhost (c-71-197-186-152.hsd1.wa.comcast.net. [71.197.186.152]) by smtp.gmail.com with ESMTPSA id y7sm3376435pjp.47.2020.07.17.10.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2020 10:53:59 -0700 (PDT) From: Kevin Hilman List-Id: To: soc@kernel.org, arm@kernel.org Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL] ARM: dts: amlogic updates for v5.9 Date: Fri, 17 Jul 2020 10:53:59 -0700 Message-ID: <7hd04uf2o8.fsf@baylibre.com> MIME-Version: 1.0 The following changes since commit b3a9e3b9622ae10064826dccb4f7a52bd88c7407: Linux 5.8-rc1 (2020-06-14 12:45:04 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-dt for you to fetch changes up to d6a3873c7be6d58914ea5584dc7875f2045d6721: ARM: dts: meson8b: odroidc1: enable the SDHC controller (2020-07-13 11:58:15 -0700) ---------------------------------------------------------------- ARM: dts: amlogic updates for v5.9 - power-domain and MMC updates ---------------------------------------------------------------- Martin Blumenstingl (6): ARM: dts: meson8: add power domain controller ARM: dts: meson8m2: add resets for the power domain controller ARM: dts: meson8b: add power domain controller ARM: dts: meson: add the SDHC MMC controller ARM: dts: meson8b: ec100: enable the SDHC controller ARM: dts: meson8b: odroidc1: enable the SDHC controller arch/arm/boot/dts/meson.dtsi | 7 +++++ arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++++++++ arch/arm/boot/dts/meson8b-ec100.dts | 25 ++++++++++++++++++ arch/arm/boot/dts/meson8b-odroidc1.dts | 26 ++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 47 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson8m2.dtsi | 23 ++++++++++++++++ 6 files changed, 160 insertions(+)