From patchwork Wed Jul 29 12:00:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51B0E6C1 for ; Wed, 29 Jul 2020 12:01:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A8512173E for ; Wed, 29 Jul 2020 12:01:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="n07AGrTU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726799AbgG2MBJ (ORCPT ); Wed, 29 Jul 2020 08:01:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbgG2MBG (ORCPT ); Wed, 29 Jul 2020 08:01:06 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA8CEC061794; Wed, 29 Jul 2020 05:01:05 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id p14so2490210wmg.1; Wed, 29 Jul 2020 05:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffWqQU26EKVHaH4j5TG8VdhwKZhWQGA8HNUdkfskr1g=; b=n07AGrTUY4ZeBZzgsUrEEayU6p3xaMblwE8U62fxRMRJ4OFsGX3bGqH140wFA2tjSg WGmfZqFZIF+V1jKynRUbH61VsDaRD09T5W085ZUjcg3IG0XeYRnqp/AYaxis0ue2jDNJ Fev4kbMVnFXiudzsB/YZyGIQ4kGrMsdkzqRiqVHf8F3mtYwANxON1imLOwwdR5x8Zkpb Coc/hpKgdZIsQriiD8GQHd/PN1ZQ9q3z33e7ixenNpAtSO7Nzx8zmbgfgwvSYybiyp5T SAZwBB4YZ2oLCZ/tEy5d6gA8T95SRbqE7VPHaTkt9JcUkigEILSCSzxiR+lNiafToP7j PGOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffWqQU26EKVHaH4j5TG8VdhwKZhWQGA8HNUdkfskr1g=; b=ms1zGPu0SPvL9CIlokQc3dubhfb5VYup0f8F6nGnzupz14Vg5rN7d3FvW6otzC2wv2 DLKFHcas/JLHmxhWl8c2O6lFZrcHnQju64rfVjHu1KCdxNWUmjLxi2Y0BIG/GmXS3gBn fk6Ic3JtVN4ljYiiNbnCtqw2xp7KzGHrUYhe8X6JKXdK5Bo4E3jQEmaSG+Qufqh4Tz23 XP8rqcF8wsgaJXImDjilN6vW9qtIIj2t86t2HW2aPL3eH2V+shEXQJemkbWsmen905tr OqFdX+M5mwi82qJlN3qqfdrkrtlQDXb3EMyY72hlt+xYcEAqHLT0lY0Y9oecvbrgzX/1 kcFg== X-Gm-Message-State: AOAM5317FYKasvHBmptuPv91uG2fLlcYFna+9Xy3R4fcaDYQtimha1xg HJ+szZQcI+CrH4fjCJDiLRE= X-Google-Smtp-Source: ABdhPJyJs58APPSBbv50xADKh7Fo4yFO/0UGQOMAMDa8fOygjorZk1B7jLL9BjNkqqfkckCS7nc4rg== X-Received: by 2002:a1c:3285:: with SMTP id y127mr8501315wmy.104.1596024064564; Wed, 29 Jul 2020 05:01:04 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:03 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 01/10] arm64: dts: qcom: msm8992: Add support for SDHCI2 Date: Wed, 29 Jul 2020 14:00:47 +0200 Message-Id: <20200729120057.35079-2-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This will let us use SD cards on our devices. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 188fff2095f1..9b42ac42b171 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -269,6 +269,28 @@ sdhc_1: sdhci@f9824900 { status = "disabled"; }; + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; @@ -573,6 +595,42 @@ i2c13_sleep: i2c13-sleep { drive-strength = <2>; bias-disable; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; From patchwork Wed Jul 29 12:00:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8940A6C1 for ; Wed, 29 Jul 2020 12:01:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71D5C2083B for ; Wed, 29 Jul 2020 12:01:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dNW3EfQC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726650AbgG2MBJ (ORCPT ); Wed, 29 Jul 2020 08:01:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726772AbgG2MBI (ORCPT ); Wed, 29 Jul 2020 08:01:08 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 017A3C0619D2; Wed, 29 Jul 2020 05:01:08 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id 9so2463675wmj.5; Wed, 29 Jul 2020 05:01:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TF7XW+i8cbP3gIkhlhIAvvLS4ohbcx6+poBRM18scqo=; b=dNW3EfQCxfi7bVB1bqjW/PrHh2iBoDIiGQ9glC0S9lATe0WwlagXVgZpkFoPu4r5yu BCXvSQSxwlLkoFnF7b1z5hiCbZuk7KIPUQ+xNkr0UysidzdxM7fHO7Jbzmz/QwXVaS8G FGOKsriVvB7Iw/U/aMyC7nRwO4Bii1IB97+GLvwjyBv42tbRWFl6LcbUalTlsf664gVV 9k7hmTpiCUXhsWBzMIcJ8KUhzrPbn4zd01tYbW/N+yceIgLjd4UOqN688UiwXduuJu6h u+vJNiSRt0bgmnAuUEENAyZyfrAYKQKLVsC7ygfHv495dTUGD7SJDoc2QaLKfUWznWyr AoYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TF7XW+i8cbP3gIkhlhIAvvLS4ohbcx6+poBRM18scqo=; b=j39aYPgEe/vsgALPIv8giw+coG81UutUs4B4/nWbgqNjeubL+Lqav6itKpKWB2m09I CR9EdgrH3EZ+sWsLCbRzAXGEmd07hOYUsQBH8AaSPhL+p3ukeuO1KI5N1q1fTHxMB9Fr ishAOgrKumyoZivlm/ryAOklGS5Xbh1t5vBnCvoiTRsmKhzihDnXClXFbvbLpD/IF8dm EkT7OVkMZae3tryhpts62dXiVT6YFodvgp5vn9YVILgklhaRcxsvt9msrM4XiXJ+fyW1 7HUlwuszJw4zqd5eeVZbcIWivgijGhBdINhpxXeR8kYmtfC01Wd9AvQcIK2KJZepd93v 9XWQ== X-Gm-Message-State: AOAM530VFxaDOlxGRxLgbLVwiptZuaqBztsNw6HyG9lCiyyChPCFJng+ MhIfvNqs27gM0PnTyRznvzY= X-Google-Smtp-Source: ABdhPJx+OYutPH7e9/IDvz+HCiS6cVZnFa/O5uDXkYICd4PPP3FHVaoU+E5IqQGySLM0Nkq/Uk9/Qw== X-Received: by 2002:a05:600c:284:: with SMTP id 4mr8601167wmk.48.1596024066770; Wed, 29 Jul 2020 05:01:06 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:06 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 02/10] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support Date: Wed, 29 Jul 2020 14:00:48 +0200 Message-Id: <20200729120057.35079-3-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This will be required to support touchscreen on Lumia devices. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 9b42ac42b171..c7dc81311f6a 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -304,6 +304,27 @@ blsp1_uart2: serial@f991e000 { status = "disabled"; }; + /* + * This I2C seems to only be present on WP platforms + * and is likely disabled in firmware + * (hangs at least one device) on android platforms. + */ + blsp_i2c1: i2c@f9923000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9923000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@f9924000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; @@ -524,6 +545,20 @@ sdc1_rclk_off: rclk-off { bias-pull-down; }; + i2c1_default: i2c1-default { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep { + function = "gpio"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + i2c2_default: i2c2-default { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; From patchwork Wed Jul 29 12:00:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690841 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9285F13B1 for ; Wed, 29 Jul 2020 12:01:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A30A20829 for ; Wed, 29 Jul 2020 12:01:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CD0/QxB9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726853AbgG2MBN (ORCPT ); Wed, 29 Jul 2020 08:01:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbgG2MBK (ORCPT ); Wed, 29 Jul 2020 08:01:10 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D342C061794; Wed, 29 Jul 2020 05:01:10 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id r4so18412873wrx.9; Wed, 29 Jul 2020 05:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IyAadO7Kj4svE/f2q3Z4e23jYOH8YNibv5HEpOFyPnU=; b=CD0/QxB9mBf+NTzosNohe42lcZIfXDYQY2Rd8Px+Oer6gRe1nHnWYhJb9NEhK7YMes I+ts1dXG8hBbHfd9mnO/E7XwONZAKW8IVDiz4w04gKmxWhAIGQJBqdGDDUu4i3ztH9NY hjJyxdSrlIsgs28uOrkub8lkRfmh30CS1LVvWGIrCESwsyZym0p8ePMnvYUTft70fLh8 8iU1nQSTdzFGRZJfxJPQNftIbaVIAePMWZCZhUk4NsRwmfFABrJbNyc/xXHHEFLft5B5 /V6DiQj/fz7LyiAjbYxE2wo6hNYYWimJez8Lz45iWADPT9qviqJgxCZyCxPFlnZ3PlAE VIKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IyAadO7Kj4svE/f2q3Z4e23jYOH8YNibv5HEpOFyPnU=; b=tY0UVXcOOqSbHATeTcetOMUeRjY2UKrFEsa8h0mwmhkg5W5e3YhefAiGC35CZuFmGo rALC7n4xxvB8G+nZJsYQ352nIQHjoBEzjU+mhDg5zo0kGnakbyXD/o3SolMiJoxYJwB+ 6sB9AUYZnsu5tAvSSQMKQoKqzIGBiPAviA9OIs2sHZrr6BtFb1fNsmZjUY47IjszTPj/ BNyCr7TFmSixXaa4HOWzu0L2lue3/jVWIrilWAyC/QERt//t3iX9B3lVaHHiAi1vTZm7 +dBlFWbyWoK89EhVhQx/Upn+R2iX+2zsPY29F3yVdKOTmxpgEqOVsMz3E5vhJptTKR0b 8tag== X-Gm-Message-State: AOAM533iExWNhKO46f36I0dkq3ALbmZqWderUhWuamdpjlFaqncL6X8g 4utcVb6QMwyUh4FzXIlrUnw= X-Google-Smtp-Source: ABdhPJzVKTxrC7sh1y9rKVLz/vxh3ZwFojV3ITq1aNkQcsq7vM+n2G7ZMwHh29wRW0wbDw2mF6tDuQ== X-Received: by 2002:adf:9c8c:: with SMTP id d12mr28786755wre.369.1596024069040; Wed, 29 Jul 2020 05:01:09 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:08 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 03/10] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen Date: Wed, 29 Jul 2020 14:00:49 +0200 Message-Id: <20200729120057.35079-4-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This adds touchscreen capabilities to the Lumia 950. Signed-off-by: Konrad Dybcio --- .../dts/qcom/msm8992-msft-lumia-talkman.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts index 3cc01f02219d..c337a86a5c77 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts @@ -32,6 +32,34 @@ chosen { }; }; +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2560>; + }; + }; +}; + &sdhc_1 { status = "okay"; From patchwork Wed Jul 29 12:00:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690843 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE51114DD for ; Wed, 29 Jul 2020 12:01:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96A4820829 for ; Wed, 29 Jul 2020 12:01:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LfVOtMH3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726862AbgG2MBO (ORCPT ); Wed, 29 Jul 2020 08:01:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726772AbgG2MBN (ORCPT ); Wed, 29 Jul 2020 08:01:13 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB215C061794; Wed, 29 Jul 2020 05:01:12 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id k8so2677266wma.2; Wed, 29 Jul 2020 05:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HfR71JevxYRyz0TRhP/dP0bQAGuhE76yoGQG/3ujNjQ=; b=LfVOtMH3sBJN99EAmx1CqBPQSoeD0BP8Qkkf14hpg/Y+khqVhN4xrHy25gYYkEit2A YdlP3O1vvVHs9Qjawv1czwPDiZazu26Fsi0pVFmGwlLalUVFFqpBR9vUJjCZY/hYKLvw N0n2JEy4JleafGiQSScfsUcMbpWqGbaIpckIDDtbL3J4ccbB43VMFyN6XzoEQ3pWQoaD /Ce0i8Bugj3arqtV+3CtQ+MjC6Tmpl/AcE3yCwMGWWLg7Un0rjVAXjx3+aUdmDSSh7si +7GL/oONmebjVU7Czy57uzBUVgRul8ULG6IMNv5W4aZr8HRdDAxgATI6J4/wCf0Y/tWQ +xNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HfR71JevxYRyz0TRhP/dP0bQAGuhE76yoGQG/3ujNjQ=; b=uQIWaYkt0wLAW6NDsKeKBVwxZrhZN/25v0TCx/jrQIKuRakDNgJPsHvTjyDwc/zRe3 XsXG8Wb94KLbGfGk6zjFwc0ABkoWUNHP6qqfVZknhaV+hDIxK+tuSI+qa/yft1gsJ8Ms 6HL0M6gJdaD9GKar+WXg19C1W8BGge/UMew84BK7dsVjHQnjGacKezO3tuDxyaoQMIji GXi6ggjCHseub42UQEZrGtJjODeEyjIVcWUpW0F/tf0UFZmJ1FpFTg/RcSbT3bpsDnxB K9TahnVP/SoqBqauSMs2B93DuetlKYCFxln635o2znjijWMvW/zfXZqHSjVVwNx/LxoQ 0unw== X-Gm-Message-State: AOAM530I2h8FM2SPD7m7rfPTDOewpL+bsmxcoBbo+X0swcYe0f4lP7gJ Z9T76KVeG04/NEZEK0mJvD4= X-Google-Smtp-Source: ABdhPJxM4uQjcmKppyYpQ2M4qoEYN3Y60qmLKVVdIINwdBWCDwkmMSrUNb4MzX5voCBjJtfuQf0VYQ== X-Received: by 2002:a1c:67d4:: with SMTP id b203mr8352608wmc.8.1596024071547; Wed, 29 Jul 2020 05:01:11 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:11 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 04/10] arm64: dts: qcom: msm8994: Add USB support Date: Wed, 29 Jul 2020 14:00:50 +0200 Message-Id: <20200729120057.35079-5-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6707f898607f..69c99a4cd817 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -282,6 +282,37 @@ frame@f9028000 { }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; From patchwork Wed Jul 29 12:00:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690845 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 595F76C1 for ; Wed, 29 Jul 2020 12:01:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42B562083E for ; Wed, 29 Jul 2020 12:01:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b9TFoTsy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726901AbgG2MBQ (ORCPT ); Wed, 29 Jul 2020 08:01:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726888AbgG2MBP (ORCPT ); Wed, 29 Jul 2020 08:01:15 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51DBFC061794; Wed, 29 Jul 2020 05:01:15 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id g8so2484297wmk.3; Wed, 29 Jul 2020 05:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I2q93FVdT16iSOi/3vPrG4ZH4MZNlbJkhzRjHUU4qvI=; b=b9TFoTsy5WXyrr/4GhmwT96zN48h+XJG6F8OrMNjFWNeMe/HOvVWCFkHeSkj/kIQl2 Pr/dWwnILpoINmDTSdN02ewi3UNuDF1s0VZqe4zNVb3WjXw4Hw+sl2ewSn26HpYmVRmB M0tZJDdsud0237DTVTelevbP7UWcqpJ2vTi2GjJ+ggFQVdp3WZwuJXxPj9FS70VnLl4G 2ajr1a4tyIe85/K93HSyC1jhw95rL/8Y7WAbW23ZEN3+/fCBXGkUYV4SXa7GYJz35ze3 tafHHWNdQTHGwsR9iG8EkEbY8xXugd40+0AgcLeUIxj3FYwo5ixyRkfIn0GF4J9HSc8b itvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I2q93FVdT16iSOi/3vPrG4ZH4MZNlbJkhzRjHUU4qvI=; b=XzaSoENyLUm1hhUlTBkcN1/O/dLL+2+x3IWSM/e9ygDxwHo5XbxgW0vMKmvdSpy8Hs 5kAcKf040o5LP4iIpwNDEIgQpOUF1zE4fDg/b/H5RKAwCn00yjjLEhK21WIUhdv1/tI0 zAmKWK6QLO9fwj81Bcdiz4LWc+c5GYU4nvGTtsZVhFCWbX1wJuR4LChl4Z0TAXhPTo11 +Xkih+3lB1kENqORWfU46WR9bvhbGisqg+x2TsKEsxN7TexR0nZEw/cR1nkO7w7vI1aI Y+1IyvZFodflWzJGIDTY6IgM+8ExFgydixP1q33DBS7UbcqG+rq1nyGVzvglfba1nL/M uOSg== X-Gm-Message-State: AOAM530uieB5q9S2oTSNTpoQr7peZmKkI+1JmAbt821TIuW53Ew3cJsB F2iy1nh1SyCHIONXOQH17xM= X-Google-Smtp-Source: ABdhPJyfxcR9YmQV9N7S17bl7YsXVxAlaWJ/ZgsO97ePfr+8SUvMXE69Or24N6Y3lWOHMERiaRv8hg== X-Received: by 2002:a05:600c:202:: with SMTP id 2mr8311399wmi.139.1596024073983; Wed, 29 Jul 2020 05:01:13 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:13 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 05/10] arm64: dts: qcom: msm8992: Add USB support Date: Wed, 29 Jul 2020 14:00:51 +0200 Message-Id: <20200729120057.35079-6-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index c7dc81311f6a..c9502fcf5d70 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -242,6 +242,37 @@ frame@f9028000 { }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; From patchwork Wed Jul 29 12:00:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03B3314DD for ; Wed, 29 Jul 2020 12:01:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E015622B43 for ; Wed, 29 Jul 2020 12:01:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ngRZKqRT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726939AbgG2MBT (ORCPT ); Wed, 29 Jul 2020 08:01:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726916AbgG2MBR (ORCPT ); Wed, 29 Jul 2020 08:01:17 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F10C061794; Wed, 29 Jul 2020 05:01:17 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id a15so21367509wrh.10; Wed, 29 Jul 2020 05:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vT8ZV4Bq4gzHVcR91/D21EVr7w9iR11fQIpmJgM0Dvc=; b=ngRZKqRT4+gaUBIIzctLQiEdogB+ttmF8+jpU6BbRVUzMm6sMWLhE2MHuwOVLN23c8 TaxeEcSoUKW/dtxacIsCJ8IxOjqD01N7SJUzdq3Wyig8OGhAd/ZB7bb9YdxdCRYBF+ZN oou0Yd5RQBX5P6L4PEDLE4zyRFl7BnIydlJw4ukU9hLz2JN/ncqUqLcbTbulba8pTx30 rHvkrFO13znOz5cmntHfEaTOLlhSQHcJSNZcjgLEC8NZSYxI8sdEgKDjzLXvzeZ00gSp E5Uk+A+6HXB6srlhUjmSyeitoddIZ0EXP5XjiVRGprDJ/GJTfMMgN+1OwTfbrmOC8eRV mUSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vT8ZV4Bq4gzHVcR91/D21EVr7w9iR11fQIpmJgM0Dvc=; b=JqqKPSA6OOAIyaIDjuKMb71pY5DagyJ+efzqC6jeGlnxsDnPkc0LqdQPnoiwMSG1yd KYqU0GDa9kUKfMJUF2niePnKJY/9UMRjXJHopco1UckFfrcNBJRBp0o0Upd/FiyO+1/K 6zG5MZ05azzNfWHYn/pf81oW+q7m2ypJyX2PuxPrMESLRYySSktTV8IKRmns1/0yvqwp fQEnHn5e9jEIkmkjegPnC/fYpgVaHFvOkaE+Z56tJO684pTI0HVuUISfgzKr7EFKKUuj vcMWs6wDrYcNjLrXh251qzy6Y1DjnXGo+6MI565rgk1/ila4gjcaTmlfuRT8fmUzhGxc kyFQ== X-Gm-Message-State: AOAM532p1wixjKPgQwpwjDRjXqckjJk7yKpaH2SSvRA+ktO+OZthAQTG 5Ae/puI5+4d5WeXpe0ujRQg= X-Google-Smtp-Source: ABdhPJymKYYX8kIInl0J7sURQaH5CL4HhlAwE9Oq4KOSY5L5/epNGA3c+CKtBN2wM8PIIpkhIwfkcQ== X-Received: by 2002:a5d:6646:: with SMTP id f6mr29619790wrw.155.1596024076307; Wed, 29 Jul 2020 05:01:16 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:15 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 06/10] arm64: dts: qcom: kitakami: Add Synaptics touchscreen Date: Wed, 29 Jul 2020 14:00:52 +0200 Message-Id: <20200729120057.35079-7-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All Kitakami devices seem to use the Synaptics RMI4 touchscreen attached to the same i2c bus. Configure and enable it. Signed-off-by: Konrad Dybcio --- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 4032b7478f04..696cd39852f4 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -138,7 +138,34 @@ &blsp_i2c5 { &blsp_i2c6 { status = "okay"; - /* Synaptics touchscreen */ + rmi4-i2c-dev@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + vdd-supply = <&pm8994_l22>; + vio-supply = <&pm8994_s4>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <220>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; }; &blsp1_uart2 { @@ -233,3 +260,19 @@ &sdhc1 { * vqmmc-supply = <&pm8994_s4>; */ }; + +&tlmm { + ts_int_active: ts-int-active { + pins = "gpio42"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + ts_reset_active: ts-reset-active { + pins = "gpio109"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; From patchwork Wed Jul 29 12:00:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690847 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D47C6C1 for ; Wed, 29 Jul 2020 12:01:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 352CF22BEA for ; Wed, 29 Jul 2020 12:01:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ii8Ctz3D" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726958AbgG2MBV (ORCPT ); Wed, 29 Jul 2020 08:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726951AbgG2MBU (ORCPT ); Wed, 29 Jul 2020 08:01:20 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D177C061794; Wed, 29 Jul 2020 05:01:20 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id f1so20825878wro.2; Wed, 29 Jul 2020 05:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/lXxR/NY5u0DlFOjxBacWTF69g+Zu3unhXyQAhYQnSE=; b=Ii8Ctz3D1uiaERNJl48OkBtwTsKK2ZgNHo2JVCi0umqh5bVDAWfQnOGPkwcZ2P973I 0yKCKXDQMyUc74/kyskmDD/DDtzue58n914mjexDJIivrZyiJlimdxt/OJIHqrIv6mwA rHA3uhRVeX/X358AkqMxCVTm6ZfbVcGn4loRE53biVZ2iY6dazW1LKfbtCtrAIPrXT0v AHkOarc6wpIX0p2UlWoaweASjy6au/fKTH6rn58VO6KFfgtKfjmATOX86d0arEkw6u+h XAWL41doIVAg8QETx34xKQvYPrQCot28RRfIY2J7BKrnfyjsC1Sh8TbodjKcgdYZOZPq Ltqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/lXxR/NY5u0DlFOjxBacWTF69g+Zu3unhXyQAhYQnSE=; b=sN76ac2729+S4L9Bo7EoMLjcXnjU7JP+SbjGEdJq/Pk8DpBpxaNkxNePmcRgwT+hFU C+IaCFtGp2vIXaBFXvT1zO2STqsPw5PBNF3l0daEmBC4DcDAGFpklUYSRQMl/ljVyAE1 +nPl2+RiDpEwmxo9Iar66txrMJIK4XLxD85Pr98g6s8jK03Q+fOAnMao1C1A7UgyqpTe iSW/lLtbBa7aaPa9USDUmFGB9A5hYntAL9as4IN0QOC+4J8nE77zrq0wccMvC8SW16Eh RQMBpg94wLHqv6MlQldnzWcJwicjXgGPW/o7b6A+z5pqJzdLQ2dktgaTni88hmEr6u04 K2EA== X-Gm-Message-State: AOAM532kmMIA8u0iZ8OewLtpDMDi7TsSlnROyeQMqjPUc63pgLWqo4Ld IggbNzXNTEwQ5+yf3KzPwCM= X-Google-Smtp-Source: ABdhPJxaKldZOn68WQ/doouvGxrGEYEWjbgALmqtHMS66sqTK2JQ8XMWs+RYhCzLTZ0pkwMmX0ptvw== X-Received: by 2002:a5d:54ca:: with SMTP id x10mr21919524wrv.36.1596024079094; Wed, 29 Jul 2020 05:01:19 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:18 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 07/10] arm64: dts: qcom: msm8994: Add SDHCI2 node Date: Wed, 29 Jul 2020 14:00:53 +0200 Message-Id: <20200729120057.35079-8-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add SDHCI2 to enable use of uSD cards on msm8994. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 69c99a4cd817..58fc8b0321c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -336,6 +336,28 @@ sdhc1: sdhci@f9824900 { status = "disabled"; }; + sdhc2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + status = "disabled"; + }; + blsp1_dma: dma@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; @@ -714,6 +736,42 @@ sdc1_rclk_off: rclk-off { pins = "sdc1_rclk"; bias-pull-down; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <10>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; From patchwork Wed Jul 29 12:00:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690853 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CC6113B1 for ; Wed, 29 Jul 2020 12:01:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8497F2083E for ; Wed, 29 Jul 2020 12:01:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GAhF4rqW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726916AbgG2MBY (ORCPT ); Wed, 29 Jul 2020 08:01:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726976AbgG2MBY (ORCPT ); Wed, 29 Jul 2020 08:01:24 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A00B0C061794; Wed, 29 Jul 2020 05:01:22 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id l2so10827560wrc.7; Wed, 29 Jul 2020 05:01:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3xVG670XkylcieeabI4BfFgFxbC/3cUWewC6wtfaP/Y=; b=GAhF4rqWA/rCnxC0tmw0CqGWsHsMefRlXnwrFNwJkZRxk2S7Xlc2vthRRjMT2+bEJd Z2s/mNCF7YAPqEAEOcVmE7Ta0OKwBn4dVXY1VzTGe8lsCr5QPn2Xgc0tSLUplXn34chH cKO5cJD1kPAnz2n3AQz2mmpgzcydYv0gF2CRiIH75/BYhfbl07IS2W8LbzyVEJe0Hqqn l0I3vcQUQ7TkLtMjODUf9AeSGeB1dNveifBRpNKNirgxLxUCsSPRB6V6byfFgJP+jDZM ungqp3BHQupzl1ipOFqRz8krpQRXsLgLC1w4CvPGJ69QL6UGJmR7JilN7IZOuuGEoUK7 6M/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3xVG670XkylcieeabI4BfFgFxbC/3cUWewC6wtfaP/Y=; b=IpuJG/EK3KgILuWShP+FI3E1XLja8K9EV8kX/6lhcwa8WlBTmwMHvnlYaF3l7Ud8Bv fXUkIVnqnna+DKaLtXWqZs5v/2y2NjW8TryWSybHoEoILpYSRsvtfTa0kZB/Q9PjEfWK ViQr7osp13CLZDoQKHORRgso/DwhB5vOe2J63PNcAQnzE9+n/Xo7uXBAoIzpsjK14b3c U+Ab1eiCohFLRAm1t32yKi9PksmeptXfIJOx/M0OEM7hbRTkeRxDjyojpOBxz0YDMNsM TpiUNt3UdY9oaS+HWBSvNOigXQ+ru5QDc3pQ/gz4oClXHYkDEiEd5LmhyxKNE3FiS8LL QaGg== X-Gm-Message-State: AOAM530iFPyKf6MGC1CzwchDzJQAteXzyQd0COmrUxm/LrW8m8dp2Ra9 O4Yrp9mhX8dc7b/M1jqOQtY= X-Google-Smtp-Source: ABdhPJwaYKdSpCLeQeI5eyGMB+KUi6nGVIlTL4OC0YJQjCvxsI7L/NwUEDmuDNd1TKL0Dgyhw1Z0ag== X-Received: by 2002:a5d:4407:: with SMTP id z7mr28809614wrq.404.1596024081422; Wed, 29 Jul 2020 05:01:21 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:21 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 08/10] arm64: dts: qcom: kitakami: Enable SDHCI2 Date: Wed, 29 Jul 2020 14:00:54 +0200 Message-Id: <20200729120057.35079-9-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This enables the use of uSD cards. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 696cd39852f4..806e8ee00833 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -261,6 +261,10 @@ &sdhc1 { */ }; +&sdhc2 { + status = "okay"; +}; + &tlmm { ts_int_active: ts-int-active { pins = "gpio42"; From patchwork Wed Jul 29 12:00:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCEA013B1 for ; Wed, 29 Jul 2020 12:01:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AAF312173E for ; Wed, 29 Jul 2020 12:01:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UejDevBv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727022AbgG2MBh (ORCPT ); Wed, 29 Jul 2020 08:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726984AbgG2MB0 (ORCPT ); Wed, 29 Jul 2020 08:01:26 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 480DFC061794; Wed, 29 Jul 2020 05:01:26 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id k8so2678133wma.2; Wed, 29 Jul 2020 05:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sNDzOj06dVBJ6v8kCDFLm4glmz05bF3t/mKwoorOGHM=; b=UejDevBvPWb5c7jgYHnIMZNKjxn22NfUB7CWVNMRw3d+GMrV45IMXmoaRnjHXc6qqF HpfoenGftcGBwY67IeCMY5UOBbMDYTn4jr1fU47gd2zmJGQgxl9uuzA52Nu1GfVTjEFA RJ+G5AcC8XSG8mK1GTvDIEh9FLdciuCnJQ1bajd2WUxGYLlHUjiQHn7p0Biiqz0v6feZ Z1m1wEN3lVWobf9zzIAc83Bsw++HQTQ6CYVg6boTGWBT4tKd2Xq+rtZEsLAgtK/zGO1C g9hCicZkIWJ6muFBTKNTSJh2i1dOxNw+xJhs2cz8xR+kiQzu8VtCAJQG/IZWVwtZKO5r gcmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sNDzOj06dVBJ6v8kCDFLm4glmz05bF3t/mKwoorOGHM=; b=B9yulQuLIonWf/a8Rh2QOYyjsPKKLuijHfF3MsOZhjaoTAGkhZQ/q19CKim8NmbuOY zSDuH6UdpePOMygJRL/y+BzBSKRGFeAjQiJ56eAwUyWmgVT0CrqQJEPTw90wC/4rwFsT XJtxEMcDgPJl/2wqPWFn/wkNGutmORHC5MhAuLFvDu9JOzyzY9J+xj68pzC82bl3V7lT eJEaqzcAn4wvYdfx6uFg78n1L88/RjRNLU20ccdA9d6/L/xuxM1aryFUFymkEKPY5cZw bcQU9VCkfIAmHNE25bPwEvMaKIyGofrJtZHRlxIcfsQ5ZJHKI9trsWs6fRI8dStYW0U5 EQsQ== X-Gm-Message-State: AOAM532HkTROUmYpqDFhpNzClV1vRTBKIRDnRbQU9jUTbgyWVZ/LplwM 5QuatjMO9TEv1rz1Z2Lgw4U= X-Google-Smtp-Source: ABdhPJyACfuWn3+5w8AsqyBC4Oey2uf5P/+ateBpMgWbqHOg2NpY5P1qMrqvpGAQXtZXyNaWevbfTg== X-Received: by 2002:a1c:7511:: with SMTP id o17mr8928310wmc.49.1596024084708; Wed, 29 Jul 2020 05:01:24 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:24 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 09/10] clk: qcom: gcc-msm8994: Fix up the driver and modernize it Date: Wed, 29 Jul 2020 14:00:55 +0200 Message-Id: <20200729120057.35079-10-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Clocks have been switched from using parent_names to parent_data, predefined "xo" has been removed in favour of specifying it in the DT and the probe function has been updated to use qcom_cc_really_probe. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 800 ++++++++++++++----- include/dt-bindings/clock/qcom,gcc-msm8994.h | 37 + 2 files changed, 622 insertions(+), 215 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index b7fc8c7ba195..ee6b2d7ac2a2 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -20,6 +20,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -27,40 +28,6 @@ enum { P_GPLL4, }; -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, -}; - -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0", -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 }, -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0", - "gpll4", -}; - -static struct clk_fixed_factor xo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data) - { - .name = "xo", - .parent_names = (const char *[]) { "xo_board" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - static struct clk_alpha_pll gpll0_early = { .offset = 0x00000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], @@ -117,6 +84,28 @@ static struct clk_alpha_pll_postdiv gpll4 = { }, }; +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, +}; + static struct freq_tbl ftbl_ufs_axi_clk_src[] = { F(50000000, P_GPLL0, 12, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), @@ -136,7 +125,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "ufs_axi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -157,7 +146,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "usb30_master_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -177,7 +166,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -205,7 +194,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -219,7 +208,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -234,7 +223,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -248,7 +237,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -263,7 +252,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -277,7 +266,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -292,7 +281,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -306,7 +295,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -321,7 +310,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -335,7 +324,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -350,7 +339,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -384,7 +373,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -399,7 +388,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -414,7 +403,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -429,7 +418,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -444,7 +433,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -459,7 +448,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp1_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -473,7 +462,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -488,7 +477,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -502,7 +491,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -517,7 +506,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -531,7 +520,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -546,7 +535,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -560,7 +549,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -575,7 +564,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -589,7 +578,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -604,7 +593,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -618,7 +607,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -633,7 +622,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -648,7 +637,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -663,7 +652,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -678,7 +667,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -693,7 +682,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -708,7 +697,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -723,7 +712,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "blsp2_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -745,7 +734,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "gp1_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -767,7 +756,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "gp2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -789,7 +778,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "gp3_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -808,7 +797,9 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "pcie_0_aux_clk_src", - .parent_names = (const char *[]) { "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_rcg2_ops, }, @@ -826,7 +817,9 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "pcie_0_pipe_clk_src", - .parent_names = (const char *[]) { "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_rcg2_ops, }, @@ -845,7 +838,9 @@ static struct clk_rcg2 pcie_1_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "pcie_1_aux_clk_src", - .parent_names = (const char *[]) { "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_rcg2_ops, }, @@ -858,7 +853,9 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "pcie_1_pipe_clk_src", - .parent_names = (const char *[]) { "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_rcg2_ops, }, @@ -877,7 +874,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "pdm2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -904,7 +901,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "sdcc1_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4, + .parent_data = gcc_xo_gpll0_gpll4, .num_parents = 3, .ops = &clk_rcg2_floor_ops, }, @@ -930,7 +927,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "sdcc2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_floor_ops, }, @@ -945,7 +942,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "sdcc3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_floor_ops, }, @@ -960,7 +957,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "sdcc4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_floor_ops, }, @@ -979,7 +976,9 @@ static struct clk_rcg2 tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "tsif_ref_clk_src", - .parent_names = (const char *[]) { "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_rcg2_ops, }, @@ -999,7 +998,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -1017,7 +1016,9 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "usb3_phy_aux_clk_src", - .parent_names = (const char *[]) { "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_rcg2_ops, }, @@ -1036,7 +1037,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "usb_hs_system_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -1064,8 +1065,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup1_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1082,8 +1083,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup1_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1100,8 +1101,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup2_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1118,8 +1119,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup2_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1136,8 +1137,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup3_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1154,8 +1155,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup3_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1172,8 +1173,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup4_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1190,8 +1191,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup4_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1208,8 +1209,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup5_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup5_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup5_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1226,8 +1227,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup5_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup5_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup5_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1244,8 +1245,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup6_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup6_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup6_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1262,8 +1263,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_qup6_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp1_qup6_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_qup6_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1280,8 +1281,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]) { - "blsp1_uart1_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1298,8 +1299,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]) { - "blsp1_uart2_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1316,8 +1317,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_uart3_apps_clk", - .parent_names = (const char *[]) { - "blsp1_uart3_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1334,8 +1335,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_uart4_apps_clk", - .parent_names = (const char *[]) { - "blsp1_uart4_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_uart4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1352,8 +1353,8 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_uart5_apps_clk", - .parent_names = (const char *[]) { - "blsp1_uart5_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_uart5_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1370,8 +1371,8 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_uart6_apps_clk", - .parent_names = (const char *[]) { - "blsp1_uart6_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp1_uart6_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1402,8 +1403,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup1_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1420,8 +1421,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup1_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1438,8 +1439,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup2_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1456,8 +1457,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup2_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1474,8 +1475,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup3_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1492,8 +1493,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup3_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1510,8 +1511,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup4_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1528,8 +1529,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup4_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1546,8 +1547,8 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup5_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup5_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup5_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1564,8 +1565,8 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup5_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup5_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup5_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1582,8 +1583,8 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup6_i2c_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup6_i2c_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup6_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1600,8 +1601,8 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_qup6_spi_apps_clk", - .parent_names = (const char *[]) { - "blsp2_qup6_spi_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_qup6_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1618,8 +1619,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]) { - "blsp2_uart1_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1636,8 +1637,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]) { - "blsp2_uart2_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1654,8 +1655,8 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_uart3_apps_clk", - .parent_names = (const char *[]) { - "blsp2_uart3_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1672,8 +1673,8 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_uart4_apps_clk", - .parent_names = (const char *[]) { - "blsp2_uart4_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_uart4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1690,8 +1691,8 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_uart5_apps_clk", - .parent_names = (const char *[]) { - "blsp2_uart5_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_uart5_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1708,8 +1709,8 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp2_uart6_apps_clk", - .parent_names = (const char *[]) { - "blsp2_uart6_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &blsp2_uart6_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1726,8 +1727,8 @@ static struct clk_branch gcc_gp1_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_gp1_clk", - .parent_names = (const char *[]) { - "gp1_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1744,8 +1745,8 @@ static struct clk_branch gcc_gp2_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_gp2_clk", - .parent_names = (const char *[]) { - "gp2_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1762,8 +1763,8 @@ static struct clk_branch gcc_gp3_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_gp3_clk", - .parent_names = (const char *[]) { - "gp3_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1772,6 +1773,32 @@ static struct clk_branch gcc_gp3_clk = { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg = 0x0280, + .clkr = { + .enable_reg = 0x0280, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_lpass_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x0284, + .clkr = { + .enable_reg = 0x0284, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_mss_q6_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_0_aux_clk = { .halt_reg = 0x1ad4, .clkr = { @@ -1780,8 +1807,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_pcie_0_aux_clk", - .parent_names = (const char *[]) { - "pcie_0_aux_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1790,6 +1817,32 @@ static struct clk_branch gcc_pcie_0_aux_clk = { }, }; +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { + .halt_reg = 0x1ad0, + .clkr = { + .enable_reg = 0x1ad0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk = { + .halt_reg = 0x1acc, + .clkr = { + .enable_reg = 0x1acc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x1ad8, .halt_check = BRANCH_HALT_DELAY, @@ -1799,8 +1852,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk", - .parent_names = (const char *[]) { - "pcie_0_pipe_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie_0_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1809,6 +1862,20 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { }, }; +static struct clk_branch gcc_pcie_0_slv_axi_clk = { + .halt_reg = 0x1ac8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1ac8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_1_aux_clk = { .halt_reg = 0x1b54, .clkr = { @@ -1817,8 +1884,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_pcie_1_aux_clk", - .parent_names = (const char *[]) { - "pcie_1_aux_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie_1_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1827,6 +1894,32 @@ static struct clk_branch gcc_pcie_1_aux_clk = { }, }; +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .halt_reg = 0x1b54, + .clkr = { + .enable_reg = 0x1b54, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .halt_reg = 0x1b50, + .clkr = { + .enable_reg = 0x1b50, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x1b58, .halt_check = BRANCH_HALT_DELAY, @@ -1836,8 +1929,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_pcie_1_pipe_clk", - .parent_names = (const char *[]) { - "pcie_1_pipe_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie_1_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1846,6 +1939,19 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { }, }; +static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .halt_reg = 0x1b48, + .clkr = { + .enable_reg = 0x1b48, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x0ccc, .clkr = { @@ -1854,8 +1960,8 @@ static struct clk_branch gcc_pdm2_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_pdm2_clk", - .parent_names = (const char *[]) { - "pdm2_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1864,6 +1970,19 @@ static struct clk_branch gcc_pdm2_clk = { }, }; +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x0cc4, + .clkr = { + .enable_reg = 0x0cc4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc1_apps_clk = { .halt_reg = 0x04c4, .clkr = { @@ -1872,8 +1991,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]) { - "sdcc1_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1890,10 +2009,19 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sdcc1_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, - .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x0508, + .clkr = { + .enable_reg = 0x0508, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc2_ahb_clk", .ops = &clk_branch2_ops, }, }, @@ -1907,8 +2035,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]) { - "sdcc2_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1917,6 +2045,19 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; +static struct clk_branch gcc_sdcc3_ahb_clk = { + .halt_reg = 0x0548, + .clkr = { + .enable_reg = 0x0548, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc3_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc3_apps_clk = { .halt_reg = 0x0544, .clkr = { @@ -1925,8 +2066,8 @@ static struct clk_branch gcc_sdcc3_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sdcc3_apps_clk", - .parent_names = (const char *[]) { - "sdcc3_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &sdcc3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1935,6 +2076,19 @@ static struct clk_branch gcc_sdcc3_apps_clk = { }, }; +static struct clk_branch gcc_sdcc4_ahb_clk = { + .halt_reg = 0x0588, + .clkr = { + .enable_reg = 0x0588, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc4_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc4_apps_clk = { .halt_reg = 0x0584, .clkr = { @@ -1943,8 +2097,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sdcc4_apps_clk", - .parent_names = (const char *[]) { - "sdcc4_apps_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1961,8 +2115,8 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sys_noc_ufs_axi_clk", - .parent_names = (const char *[]) { - "ufs_axi_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1979,8 +2133,8 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_sys_noc_usb3_axi_clk", - .parent_names = (const char *[]) { - "usb30_master_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1989,6 +2143,19 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { }, }; +static struct clk_branch gcc_tsif_ahb_clk = { + .halt_reg = 0x0d84, + .clkr = { + .enable_reg = 0x0d84, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_tsif_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_tsif_ref_clk = { .halt_reg = 0x0d88, .clkr = { @@ -1997,8 +2164,8 @@ static struct clk_branch gcc_tsif_ref_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_tsif_ref_clk", - .parent_names = (const char *[]) { - "tsif_ref_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &tsif_ref_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2007,6 +2174,19 @@ static struct clk_branch gcc_tsif_ref_clk = { }, }; +static struct clk_branch gcc_ufs_ahb_clk = { + .halt_reg = 0x1d4c, + .clkr = { + .enable_reg = 0x1d4c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_axi_clk = { .halt_reg = 0x1d48, .clkr = { @@ -2015,8 +2195,8 @@ static struct clk_branch gcc_ufs_axi_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_ufs_axi_clk", - .parent_names = (const char *[]) { - "ufs_axi_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2033,8 +2213,8 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_ufs_rx_cfg_clk", - .parent_names = (const char *[]) { - "ufs_axi_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2043,6 +2223,34 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { }, }; +static struct clk_branch gcc_ufs_rx_symbol_0_clk = { + .halt_reg = 0x1d60, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d60, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_rx_symbol_1_clk = { + .halt_reg = 0x1d64, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d64, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_tx_cfg_clk = { .halt_reg = 0x1d50, .clkr = { @@ -2051,8 +2259,8 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_ufs_tx_cfg_clk", - .parent_names = (const char *[]) { - "ufs_axi_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2061,6 +2269,47 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { }, }; +static struct clk_branch gcc_ufs_tx_symbol_0_clk = { + .halt_reg = 0x1d58, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d58, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_tx_symbol_1_clk = { + .halt_reg = 0x1d5c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d5c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_tx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { + .halt_reg = 0x04ac, + .clkr = { + .enable_reg = 0x04ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb2_hs_phy_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb30_master_clk = { .halt_reg = 0x03c8, .clkr = { @@ -2069,8 +2318,8 @@ static struct clk_branch gcc_usb30_master_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]) { - "usb30_master_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2087,8 +2336,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]) { - "usb30_mock_utmi_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2097,6 +2346,19 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { }, }; +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0x03cc, + .clkr = { + .enable_reg = 0x03cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_phy_aux_clk = { .halt_reg = 0x1408, .clkr = { @@ -2105,8 +2367,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]) { - "usb3_phy_aux_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &usb3_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2115,6 +2377,19 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { }, }; +static struct clk_branch gcc_usb_hs_ahb_clk = { + .halt_reg = 0x0488, + .clkr = { + .enable_reg = 0x0488, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb_hs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb_hs_system_clk = { .halt_reg = 0x0484, .clkr = { @@ -2123,8 +2398,8 @@ static struct clk_branch gcc_usb_hs_system_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_usb_hs_system_clk", - .parent_names = (const char *[]) { - "usb_hs_system_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_hs_system_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2133,6 +2408,59 @@ static struct clk_branch gcc_usb_hs_system_clk = { }, }; +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x1a84, + .clkr = { + .enable_reg = 0x1a84, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc pcie_gdsc = { + .gdscr = 0x1e18, + .pd = { + .name = "pcie", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x1ac4, + .pd = { + .name = "pcie_0", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x1b44, + .pd = { + .name = "pcie_1", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_gdsc = { + .gdscr = 0x3c4, + .pd = { + .name = "usb30", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_gdsc = { + .gdscr = 0x1d44, + .pd = { + .name = "ufs", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_msm8994_clocks[] = { [GPLL0_EARLY] = &gpll0_early.clkr, [GPLL0] = &gpll0.clkr, @@ -2233,26 +2561,65 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, + [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, + [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, + [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, +}; + +static struct gdsc *gcc_msm8994_gdscs[] = { + [PCIE_GDSC] = &pcie_gdsc, + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_1_GDSC] = &pcie_1_gdsc, + [USB30_GDSC] = &usb30_gdsc, + [UFS_GDSC] = &ufs_gdsc, +}; + +static const struct qcom_reset_map gcc_msm8994_resets[] = { + [USB3_PHY_RESET] = { 0x1400 }, + [USB3PHY_PHY_RESET] = { 0x1404 }, + [MSS_RESTART] = { 0x1680 }, + [PCIE_PHY_0_RESET] = { 0x1b18 }, + [PCIE_PHY_1_RESET] = { 0x1b98 }, + [QUSB2_PHY_RESET] = { 0x04b8 }, }; static const struct regmap_config gcc_msm8994_regmap_config = { @@ -2267,6 +2634,10 @@ static const struct qcom_cc_desc gcc_msm8994_desc = { .config = &gcc_msm8994_regmap_config, .clks = gcc_msm8994_clocks, .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), + .resets = gcc_msm8994_resets, + .num_resets = ARRAY_SIZE(gcc_msm8994_resets), + .gdscs = gcc_msm8994_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), }; static const struct of_device_id gcc_msm8994_match_table[] = { @@ -2277,14 +2648,13 @@ MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); static int gcc_msm8994_probe(struct platform_device *pdev) { - struct device *dev = &pdev->dev; - struct clk *clk; + struct regmap *regmap; - clk = devm_clk_register(dev, &xo.hw); - if (IS_ERR(clk)) - return PTR_ERR(clk); + regmap = qcom_cc_map(pdev, &gcc_msm8994_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); - return qcom_cc_probe(pdev, &gcc_msm8994_desc); + return qcom_cc_really_probe(pdev, &gcc_msm8994_desc, regmap); } static struct platform_driver gcc_msm8994_driver = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 938969309e00..8175ebb0320f 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -126,5 +126,42 @@ #define GCC_USB3_PHY_AUX_CLK 116 #define GCC_USB_HS_SYSTEM_CLK 117 #define GCC_SDCC1_AHB_CLK 118 +#define GCC_LPASS_Q6_AXI_CLK 119 +#define GCC_MSS_Q6_BIMC_AXI_CLK 120 +#define GCC_PCIE_0_CFG_AHB_CLK 121 +#define GCC_PCIE_0_MSTR_AXI_CLK 122 +#define GCC_PCIE_0_SLV_AXI_CLK 123 +#define GCC_PCIE_1_CFG_AHB_CLK 124 +#define GCC_PCIE_1_MSTR_AXI_CLK 125 +#define GCC_PCIE_1_SLV_AXI_CLK 126 +#define GCC_PDM_AHB_CLK 127 +#define GCC_SDCC2_AHB_CLK 128 +#define GCC_SDCC3_AHB_CLK 129 +#define GCC_SDCC4_AHB_CLK 130 +#define GCC_TSIF_AHB_CLK 131 +#define GCC_UFS_AHB_CLK 132 +#define GCC_UFS_RX_SYMBOL_0_CLK 133 +#define GCC_UFS_RX_SYMBOL_1_CLK 134 +#define GCC_UFS_TX_SYMBOL_0_CLK 135 +#define GCC_UFS_TX_SYMBOL_1_CLK 136 +#define GCC_USB2_HS_PHY_SLEEP_CLK 137 +#define GCC_USB30_SLEEP_CLK 138 +#define GCC_USB_HS_AHB_CLK 139 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 + +/* GDSCs */ +#define PCIE_GDSC 0 +#define PCIE_0_GDSC 1 +#define PCIE_1_GDSC 2 +#define USB30_GDSC 3 +#define UFS_GDSC 4 + +/* Resets */ +#define USB3_PHY_RESET 0 +#define USB3PHY_PHY_RESET 1 +#define PCIE_PHY_0_RESET 2 +#define PCIE_PHY_1_RESET 3 +#define QUSB2_PHY_RESET 4 +#define MSS_RESTART 5 #endif From patchwork Wed Jul 29 12:00:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11690849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 831706C1 for ; Wed, 29 Jul 2020 12:01:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A6E922CB1 for ; Wed, 29 Jul 2020 12:01:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ADs2k5e2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726976AbgG2MB3 (ORCPT ); Wed, 29 Jul 2020 08:01:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727001AbgG2MB2 (ORCPT ); Wed, 29 Jul 2020 08:01:28 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3799AC0619D4; Wed, 29 Jul 2020 05:01:28 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id r4so18413911wrx.9; Wed, 29 Jul 2020 05:01:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4dsJZR6exGc1T0EmcyZPyr2Gz6t1X0UGcbSNE1N0tEw=; b=ADs2k5e2my6lFev6YnfqvFfjLdyhHpzb8DpB135rHP3kU6gOwZ+iluDWPd6l7tCfGi oxuyaRWQiopVN47KdcnrysD6oJmlpW04SZ6Fwy8FhvVrJ9EODJ3fV3RyY8uMHp1vhnx9 clcQsFTkbJ61vHPD3v/b70slyYdf+iwyGJh4f2z4RAAqbq1rixlu5pobAr5ygToIdieO NiyJPwW4FomSzEIu8zo+W+liGElj55sPlZ95CCBxdjxaDQvwuj/QnymydTaQkN5DPoOJ wPm+OaoWoZUTjjm09ClbeaHvm+D7IVmICJkSyiNYKqcgp/95pOr2CEgIlP5PrXKwdkBM Oq7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4dsJZR6exGc1T0EmcyZPyr2Gz6t1X0UGcbSNE1N0tEw=; b=BoHVExQO22+9LkmYwuUdviW+YESQzSnXc6PdZSxxz6pv2FSEJqkbGDCNEmxlK5w/Q/ gbk+vqWOlXs5OzBqpIV+upS0YwdUdCMLx7ELdm83Hb7XE8pPFmUpekRoMzVjuvm8uGSP tqxeFpdq8JlgmKAfc6CHFt8UB9ES0azBP0WKbPUA8c/vAB1V2WdrIba6WRsa/qfm1bJH 3LuqY5qjEy/ypKmOjqfMYQI6q9R35IgQ5/4mUBk54kGSvba+8rDRyL0ES67pk4YIlZWD IoKRxSw+OlY3fZf+i4AWWRN8eoBtwIqY2pLOk3JyXHozBzhi/aPe3ctBlHX6mTfoxeJE iLfA== X-Gm-Message-State: AOAM533vJz2aa6sByLzyVhdUnOTOr7fY13uSI0Z/8WU9ykuBZ/7ROaXx XMA6/W/bV0jkTbLZoxA61sI= X-Google-Smtp-Source: ABdhPJxtcOeNQtXzRyQOL5po8il8vZUESKCp/zwvGTPjQqWywMRZdXBlPmeeICZ4mjN8KIKEAdILSw== X-Received: by 2002:adf:cf10:: with SMTP id o16mr27064006wrj.380.1596024086992; Wed, 29 Jul 2020 05:01:26 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id l67sm5426000wml.13.2020.07.29.05.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 05:01:26 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 10/10] arm64: dts: qcom: msm8992/4: Add clocks property to gcc node Date: Wed, 29 Jul 2020 14:00:56 +0200 Message-Id: <20200729120057.35079-11-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200729120057.35079-1-konradybcio@gmail.com> References: <20200729120057.35079-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is required for the platforms to function after the recent driver cleanup and also is the current coding style. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index c9502fcf5d70..008206251f49 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -457,6 +457,8 @@ gcc: clock-controller@fc400000 { #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, <&sleep_clk>; }; rpm_msg_ram: memory@fc428000 { diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 58fc8b0321c3..f2f850ebd3c8 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -528,6 +528,8 @@ gcc: clock-controller@fc400000 { #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, <&sleep_clk>; }; rpm_msg_ram: memory@fc428000 {