From patchwork Thu Jul 30 03:37:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tomlinson X-Patchwork-Id: 11692251 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB1C5722 for ; Thu, 30 Jul 2020 03:38:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2D3C20829 for ; Thu, 30 Jul 2020 03:38:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="MOSOkalM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728503AbgG3DiG (ORCPT ); Wed, 29 Jul 2020 23:38:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728499AbgG3DiG (ORCPT ); Wed, 29 Jul 2020 23:38:06 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F5B9C0619D5 for ; Wed, 29 Jul 2020 20:38:05 -0700 (PDT) Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 7494A891AD; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1596080280; bh=YeyiC4Wu/Uu6RclpPH7B15lEUocwEtXXxu8/RyKOIpE=; h=From:To:Cc:Subject:Date; b=MOSOkalMNZDIEz/AzPSRcDz8YirOPqIyxHhtWoz/btlpahHWVzB2miKlAfp8sMIfN htGpmPvN3UBrpy4Ait8Z+/w84wMqTGNk9A0zTs+Ilqr9G31xNcG4XZxRmeNNbiAGJP qzqYfXZs02+iMHY/EOjgRWpNXAExjgHb52UCRZlOXgFk4UOWB8nL9Gp5MalY7fZdBM i7pXyeoyOpRYmulEn3a5qhEKkr8Dm1C8zAP8rNLtK4OhJnU01SmNZ9pmd+fJZZ41GI 75trd+PRdoVcwYfBRpPGB1f/XwEm3jyRNLE1JnbbkPc3Te8VU5gNpLQ/M8lmPSDvI/ aHuYo4r9nzisA== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Thu, 30 Jul 2020 15:38:01 +1200 Received: from markto-dl.ws.atlnz.lc (markto-dl.ws.atlnz.lc [10.33.23.25]) by smtp (Postfix) with ESMTP id F363813EEB7; Thu, 30 Jul 2020 15:37:59 +1200 (NZST) Received: by markto-dl.ws.atlnz.lc (Postfix, from userid 1155) id 3A1C8341092; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) From: Mark Tomlinson To: bhelgaas@google.com, rjui@broadcom.com, sbranden@broadcom.com, f.fainelli@gmail.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Tomlinson Subject: [PATCH 1/3] PCI: iproc: Add bus number parameter to read/write functions Date: Thu, 30 Jul 2020 15:37:45 +1200 Message-Id: <20200730033747.18931-1-mark.tomlinson@alliedtelesis.co.nz> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 x-atlnz-ls: pat Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This makes the read/write functions more generic, allowing them to be used from other places. Signed-off-by: Mark Tomlinson --- drivers/pci/controller/pcie-iproc.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 8c7f875acf7f..2c836eede42c 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -660,13 +660,13 @@ static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, where); } -static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, +static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, int busno, unsigned int devfn, int where, int size, u32 *val) { void __iomem *addr; - addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); + addr = iproc_pcie_map_cfg_bus(pcie, busno, devfn, where & ~0x3); if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -680,14 +680,14 @@ static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, return PCIBIOS_SUCCESSFUL; } -static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, +static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, int busno, unsigned int devfn, int where, int size, u32 val) { void __iomem *addr; u32 mask, tmp; - addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); + addr = iproc_pcie_map_cfg_bus(pcie, busno, devfn, where & ~0x3); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; @@ -793,7 +793,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) } /* make sure we are not in EP mode */ - iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); + iproc_pci_raw_config_read32(pcie, 0, 0, PCI_HEADER_TYPE, 1, &hdr_type); if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type); return -EFAULT; @@ -803,15 +803,16 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c #define PCI_CLASS_BRIDGE_MASK 0xffff00 #define PCI_CLASS_BRIDGE_SHIFT 8 - iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, + iproc_pci_raw_config_read32(pcie, 0, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 4, &class); class &= ~PCI_CLASS_BRIDGE_MASK; class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); - iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, + iproc_pci_raw_config_write32(pcie, 0, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 4, class); /* check link status to see if link is active */ - iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, + iproc_pci_raw_config_read32(pcie, 0, 0, + IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, 2, &link_status); if (link_status & PCI_EXP_LNKSTA_NLW) link_is_active = true; @@ -821,19 +822,19 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) #define PCI_TARGET_LINK_SPEED_MASK 0xf #define PCI_TARGET_LINK_SPEED_GEN2 0x2 #define PCI_TARGET_LINK_SPEED_GEN1 0x1 - iproc_pci_raw_config_read32(pcie, 0, + iproc_pci_raw_config_read32(pcie, 0, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, 4, &link_ctrl); if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) == PCI_TARGET_LINK_SPEED_GEN2) { link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK; link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1; - iproc_pci_raw_config_write32(pcie, 0, + iproc_pci_raw_config_write32(pcie, 0, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, 4, link_ctrl); msleep(100); - iproc_pci_raw_config_read32(pcie, 0, + iproc_pci_raw_config_read32(pcie, 0, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, 2, &link_status); if (link_status & PCI_EXP_LNKSTA_NLW) From patchwork Thu Jul 30 03:37:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tomlinson X-Patchwork-Id: 11692247 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BEEA314B7 for ; Thu, 30 Jul 2020 03:38:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A244322B4B for ; Thu, 30 Jul 2020 03:38:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="hF6zjJlK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728343AbgG3DiE (ORCPT ); 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Thu, 30 Jul 2020 15:38:01 +1200 Received: from markto-dl.ws.atlnz.lc (markto-dl.ws.atlnz.lc [10.33.23.25]) by smtp (Postfix) with ESMTP id 018C213EF0D; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) Received: by markto-dl.ws.atlnz.lc (Postfix, from userid 1155) id 3C3A733F7C9; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) From: Mark Tomlinson To: bhelgaas@google.com, rjui@broadcom.com, sbranden@broadcom.com, f.fainelli@gmail.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Tomlinson Subject: [PATCH 2/3] PCI: iproc: Stop using generic config read/write functions Date: Thu, 30 Jul 2020 15:37:46 +1200 Message-Id: <20200730033747.18931-2-mark.tomlinson@alliedtelesis.co.nz> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200730033747.18931-1-mark.tomlinson@alliedtelesis.co.nz> References: <20200730033747.18931-1-mark.tomlinson@alliedtelesis.co.nz> MIME-Version: 1.0 x-atlnz-ls: pat Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pci_generic_config_write32() function will give warning messages whenever writing less than 4 bytes at a time. As there is nothing we can do about this without changing the hardware, the message is just a nuisance. So instead of using the generic functions, use the functions that have already been written for reading/writing the config registers. Signed-off-by: Mark Tomlinson --- drivers/pci/controller/pcie-iproc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 2c836eede42c..68ecd3050529 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -709,12 +709,13 @@ static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, { int ret; struct iproc_pcie *pcie = iproc_data(bus); + int busno = bus->number; iproc_pcie_apb_err_disable(bus, true); if (pcie->iproc_cfg_read) ret = iproc_pcie_config_read(bus, devfn, where, size, val); else - ret = pci_generic_config_read32(bus, devfn, where, size, val); + ret = iproc_pci_raw_config_read32(pcie, busno, devfn, where, size, val); iproc_pcie_apb_err_disable(bus, false); return ret; @@ -724,9 +725,11 @@ static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { int ret; + struct iproc_pcie *pcie = iproc_data(bus); + int busno = bus->number; iproc_pcie_apb_err_disable(bus, true); - ret = pci_generic_config_write32(bus, devfn, where, size, val); + ret = iproc_pci_raw_config_write32(pcie, busno, devfn, where, size, val); iproc_pcie_apb_err_disable(bus, false); return ret; From patchwork Thu Jul 30 03:37:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tomlinson X-Patchwork-Id: 11692249 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 780CE722 for ; Thu, 30 Jul 2020 03:38:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5EC0920829 for ; Thu, 30 Jul 2020 03:38:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="NxsGlQYx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728508AbgG3DiG (ORCPT ); Wed, 29 Jul 2020 23:38:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726367AbgG3DiG (ORCPT ); Wed, 29 Jul 2020 23:38:06 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A7DC061794 for ; Wed, 29 Jul 2020 20:38:05 -0700 (PDT) Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6E3C58066C; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1596080280; bh=rFG+x9+HZow4TfntuPbVyKu06FhRpSlKls/VE8rrwy4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NxsGlQYxKUvwG4/yFORQSC1CkP7rmui3UCdjn/IKcuC8MacOpU20yqC998oGNuGxX gZg67tr4OdejJopPRUKGdN0d1LXDls6OC6Tak9/B3fCJ5GdKwRwwF46g+Jzlls9Bit Im0ALqoAcnli1W3to1odZ1maSOINii0iFsifHInsT7sl3n1M6q1qQ2qR3xksztPwKI MRYa3AJzzViqsJEFDt/8QzjJLUhmMHlm+5KWevVL2n/dk0vZOlnTDSqIACAA2+gMsU 3tZfj2JDhsNbhXvoT+J7KWj3A4uVkFMrSW7Jtqtf+AXQl74iGbsktUNFQzMUQyVGAj kuUfQlFNGhqdQ== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Thu, 30 Jul 2020 15:38:01 +1200 Received: from markto-dl.ws.atlnz.lc (markto-dl.ws.atlnz.lc [10.33.23.25]) by smtp (Postfix) with ESMTP id 047A813EF9B; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) Received: by markto-dl.ws.atlnz.lc (Postfix, from userid 1155) id 407DF3410D3; Thu, 30 Jul 2020 15:38:00 +1200 (NZST) From: Mark Tomlinson To: bhelgaas@google.com, rjui@broadcom.com, sbranden@broadcom.com, f.fainelli@gmail.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Tomlinson Subject: [PATCH 3/3] PCI: iproc: Set affinity mask on MSI interrupts Date: Thu, 30 Jul 2020 15:37:47 +1200 Message-Id: <20200730033747.18931-3-mark.tomlinson@alliedtelesis.co.nz> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200730033747.18931-1-mark.tomlinson@alliedtelesis.co.nz> References: <20200730033747.18931-1-mark.tomlinson@alliedtelesis.co.nz> MIME-Version: 1.0 x-atlnz-ls: pat Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The core interrupt code expects the irq_set_affinity call to update the effective affinity for the interrupt. This was not being done, so update iproc_msi_irq_set_affinity() to do so. Signed-off-by: Mark Tomlinson Reviewed-by: Ray Jui --- drivers/pci/controller/pcie-iproc-msi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c index 3176ad3ab0e5..908475d27e0e 100644 --- a/drivers/pci/controller/pcie-iproc-msi.c +++ b/drivers/pci/controller/pcie-iproc-msi.c @@ -209,15 +209,20 @@ static int iproc_msi_irq_set_affinity(struct irq_data *data, struct iproc_msi *msi = irq_data_get_irq_chip_data(data); int target_cpu = cpumask_first(mask); int curr_cpu; + int ret; curr_cpu = hwirq_to_cpu(msi, data->hwirq); if (curr_cpu == target_cpu) - return IRQ_SET_MASK_OK_DONE; + ret = IRQ_SET_MASK_OK_DONE; + else { + /* steer MSI to the target CPU */ + data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; + ret = IRQ_SET_MASK_OK; + } - /* steer MSI to the target CPU */ - data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; + irq_data_update_effective_affinity(data, cpumask_of(target_cpu)); - return IRQ_SET_MASK_OK; + return ret; } static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,