From patchwork Thu Jul 30 16:12:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11693411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64F2E912 for ; Thu, 30 Jul 2020 16:12:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4219D20829 for ; Thu, 30 Jul 2020 16:12:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="SFqwTAVX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726353AbgG3QMo (ORCPT ); Thu, 30 Jul 2020 12:12:44 -0400 Received: from crapouillou.net ([89.234.176.41]:46982 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726275AbgG3QMn (ORCPT ); Thu, 30 Jul 2020 12:12:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1596125561; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:references; bh=4UC5bN4C11HykhL6jcWAyq2cNXGmAe0l6v/GKa5hpCM=; b=SFqwTAVXyt5/QqdVrTJJqTsoraPX+mj2SLqfbWIh9748jBha+th241DbIgs37ngAPh6W6x Eov0wNaCpN6UGlztkNMSt6q8xky2mTwpo82jhTM+DMII5ttFKAQKpLyJcgo3rDWwCVzEJR QdvCWO1Vkls7RRlJp/4MS9tQmAlExXE= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Jiaxun Yang , od@zcrc.me, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 1/4] MIPS: head.S: Init fw_passed_dtb to builtin DTB Date: Thu, 30 Jul 2020 18:12:30 +0200 Message-Id: <20200730161233.61876-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Init the 'fw_passed_dtb' pointer to the buit-in Device Tree blob when it has been compiled in with CONFIG_BUILTIN_DTB. Signed-off-by: Paul Cercueil --- arch/mips/kernel/head.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 3b02ffe46304..7dd234e788e6 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -111,6 +111,12 @@ NESTED(kernel_entry, 16, sp) # kernel entry point move t2, a1 beq a0, t1, dtb_found +#ifdef CONFIG_BUILTIN_DTB + PTR_LA t2, __dtb_start + PTR_LA t1, __dtb_end + bne t1, t2, dtb_found +#endif /* CONFIG_BUILTIN_DTB */ + li t2, 0 dtb_found: #endif /* CONFIG_USE_OF */ From patchwork Thu Jul 30 16:12:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11693413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E81C76C1 for ; Thu, 30 Jul 2020 16:12:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D038B20842 for ; Thu, 30 Jul 2020 16:12:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="RjK2M9+t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726581AbgG3QMw (ORCPT ); Thu, 30 Jul 2020 12:12:52 -0400 Received: from crapouillou.net ([89.234.176.41]:47216 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726275AbgG3QMw (ORCPT ); Thu, 30 Jul 2020 12:12:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1596125562; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L7c3BbdvXEeBcbyvPR7oP4kQXz+lCc1qTz+IvvC8fbM=; b=RjK2M9+tePUSy8nHG44j1gGEg0xZdqIhPqcJdOes4G7rhO08VvqP7T8YCn5pgIXvojtLMz d1lGzlX6MFSJ8iLyVMv4p5EFPgjWlcRmeFEfFik1KKtEOP+cEYx/5aaQW+eZ3NJC7ovdNw lu7IesRFhyz1JjnqAftprWHiqDApeQA= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Jiaxun Yang , od@zcrc.me, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 2/4] MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB Date: Thu, 30 Jul 2020 18:12:31 +0200 Message-Id: <20200730161233.61876-2-paul@crapouillou.net> In-Reply-To: <20200730161233.61876-1-paul@crapouillou.net> References: <20200730161233.61876-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The fw_passed_dtb is now properly initialized even when CONFIG_BUILTIN_DTB is used, so there's no need to handle it in any particular way here. Note that the behaviour is slightly different, as the previous code used the built-in Device Tree unconditionally, while now the built-in Device Tree is only used when the bootloader did not provide one. Signed-off-by: Paul Cercueil --- arch/mips/jz4740/setup.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c index fc49601c2b96..d73c9b722bf3 100644 --- a/arch/mips/jz4740/setup.c +++ b/arch/mips/jz4740/setup.c @@ -67,13 +67,8 @@ static unsigned long __init get_board_mach_type(const void *fdt) void __init plat_mem_setup(void) { + void *dtb = (void *)fw_passed_dtb; int offset; - void *dtb; - - if (__dtb_start != __dtb_end) - dtb = __dtb_start; - else - dtb = (void *)fw_passed_dtb; __dt_setup_arch(dtb); From patchwork Thu Jul 30 16:12:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11693415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 652DB6C1 for ; Thu, 30 Jul 2020 16:13:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D5B820842 for ; Thu, 30 Jul 2020 16:13:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="pApeM7GQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729937AbgG3QM7 (ORCPT ); Thu, 30 Jul 2020 12:12:59 -0400 Received: from crapouillou.net ([89.234.176.41]:47256 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726275AbgG3QM7 (ORCPT ); Thu, 30 Jul 2020 12:12:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1596125562; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3DzFbhkz9Uh4b/FUC/mf+N2EFMvj/8dRbxdCyrTVYgI=; b=pApeM7GQ0nVTiB+MgOuAX5KuTg2ek+fjXpAclwwW6HTlMFhEE5cUugCgTLhzhclhQ1FFi8 lYSq2gvrPXQLelMT3oT6tggH+gBvI3uFqWE6LHmDwiEnjJfrpLZNpMyiheaNw9KXhsgFpc MeF2WRV3gZ3YLbfNMDQT5R+T3q5izhI= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Jiaxun Yang , od@zcrc.me, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 3/4] MIPS: DTS: ingenic/qi,lb60: Add model and memory node Date: Thu, 30 Jul 2020 18:12:32 +0200 Message-Id: <20200730161233.61876-3-paul@crapouillou.net> In-Reply-To: <20200730161233.61876-1-paul@crapouillou.net> References: <20200730161233.61876-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add a memory node, which was missing until now, and use the retail name "Ben Nanonote" as the model, as it is way more known under that name than under the name "LB60". Signed-off-by: Paul Cercueil --- arch/mips/boot/dts/ingenic/qi_lb60.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts index eda37fb516f0..bf298268f1a1 100644 --- a/arch/mips/boot/dts/ingenic/qi_lb60.dts +++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts @@ -16,6 +16,12 @@ / { compatible = "qi,lb60", "ingenic,jz4740"; + model = "Ben Nanonote"; + + memory { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; chosen { stdout-path = &uart0; From patchwork Thu Jul 30 16:12:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11693417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 340AA912 for ; Thu, 30 Jul 2020 16:13:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C9D520829 for ; Thu, 30 Jul 2020 16:13:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="abJghoYQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729387AbgG3QNI (ORCPT ); Thu, 30 Jul 2020 12:13:08 -0400 Received: from crapouillou.net ([89.234.176.41]:47478 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726275AbgG3QNH (ORCPT ); Thu, 30 Jul 2020 12:13:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1596125563; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xC/tAI47wFW/BIIHxeJ+n88dhg5MZw8jGzHIJhMQ+pI=; b=abJghoYQd4csxpb+NXHEht3ntWsP7Xd6FaZd6v73ek9SwoBnWpQyhldlotj1NlRNW5SAXN Sr+KcCuXpM3uCkVyENx1m0vQbZuDGTehVYrtnhyJw/HwTjGqfjjNV8PcQVY/exTcR0vTl3 iM0q2+Lix7cf3kIBESBXQQvOBgMSIs4= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Jiaxun Yang , od@zcrc.me, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 4/4] MIPS: ingenic: Hardcode mem size for qi,lb60 board Date: Thu, 30 Jul 2020 18:12:33 +0200 Message-Id: <20200730161233.61876-4-paul@crapouillou.net> In-Reply-To: <20200730161233.61876-1-paul@crapouillou.net> References: <20200730161233.61876-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Old Device Tree for the qi,lb60 (aka. Ben Nanonote) did not have a 'memory' node. The kernel would then read the memory controller registers to know how much RAM was available. Since every other supported board has had a 'memory' node from the beginning, we can just hardcode a RAM size of 32 MiB when running with an old Device Tree without the 'memory' node. Signed-off-by: Paul Cercueil --- arch/mips/jz4740/setup.c | 37 ++++++++----------------------------- 1 file changed, 8 insertions(+), 29 deletions(-) diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c index d73c9b722bf3..51d906325ce6 100644 --- a/arch/mips/jz4740/setup.c +++ b/arch/mips/jz4740/setup.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -22,31 +23,6 @@ #include #include -#define JZ4740_EMC_BASE_ADDR 0x13010000 - -#define JZ4740_EMC_SDRAM_CTRL 0x80 - -static void __init jz4740_detect_mem(void) -{ - void __iomem *jz_emc_base; - u32 ctrl, bus, bank, rows, cols; - phys_addr_t size; - - jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100); - ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); - bus = 2 - ((ctrl >> 31) & 1); - bank = 1 + ((ctrl >> 19) & 1); - cols = 8 + ((ctrl >> 26) & 7); - rows = 11 + ((ctrl >> 20) & 3); - printk(KERN_DEBUG - "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n", - bus, bank, rows, cols); - iounmap(jz_emc_base); - - size = 1 << (bus + bank + cols + rows); - add_memory_region(0, size, BOOT_MEM_RAM); -} - static unsigned long __init get_board_mach_type(const void *fdt) { if (!fdt_node_check_compatible(fdt, 0, "ingenic,x2000")) @@ -68,13 +44,16 @@ static unsigned long __init get_board_mach_type(const void *fdt) void __init plat_mem_setup(void) { void *dtb = (void *)fw_passed_dtb; - int offset; __dt_setup_arch(dtb); - offset = fdt_path_offset(dtb, "/memory"); - if (offset < 0) - jz4740_detect_mem(); + /* + * Old devicetree files for the qi,lb60 board did not have a /memory + * node. Hardcode the memory info here. + */ + if (!fdt_node_check_compatible(dtb, 0, "qi,lb60") && + fdt_path_offset(dtb, "/memory") < 0) + early_init_dt_add_memory_arch(0, SZ_32M); mips_machtype = get_board_mach_type(dtb); }