From patchwork Thu Oct 18 21:09:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 10648243 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 262CD3C13 for ; Thu, 18 Oct 2018 21:09:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1772E28D6D for ; Thu, 18 Oct 2018 21:09:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0B8D228D85; Thu, 18 Oct 2018 21:09:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90E2028D6D for ; Thu, 18 Oct 2018 21:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727405AbeJSFMl (ORCPT ); Fri, 19 Oct 2018 01:12:41 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:36271 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727404AbeJSFMl (ORCPT ); Fri, 19 Oct 2018 01:12:41 -0400 Received: by mail-pl1-f194.google.com with SMTP id y11-v6so14862761plt.3 for ; Thu, 18 Oct 2018 14:09:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jnOVjzaA3k+wL7/rkNrM4EYBgeAj3EhUbVMeYHm1XMU=; b=PRGf1TMOfyKUiP184cLZqkqH1PiUf8yjyb6hwi5I/QF/McUtzOFHLJB70N6vHYFz93 cUb2fDSWUntm/uTDL18iK+wXFHjSRc9blSqmfOppjXTbbWmQ3E0DFqeD63fQnWG5TGAw qy8wKIqeWxhzpvZrgj1NanMsjiPRtD2MhqOas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jnOVjzaA3k+wL7/rkNrM4EYBgeAj3EhUbVMeYHm1XMU=; b=hq6i2FyBktLizwQ2HrNXqVsBO8bp7HUUZ8H9Wgmgyu2dSMbZebxl6XT2ySfO/V+mdg iH/pcMXS8W/m9D5EyQ0K8HZHLyFLGPMtF+Dv2tSslctqD+jhp5h0siOwEqf4BsVFyk8C cv2iry7EfzTBupb2cHxmCbFjzyuV5/84WgZ2Efq3vZ70yVC57DtMpPq33TxCANGq78Zd MN20Ckg3ojjkAuXKgZ7VjP7DlvyHcnvbPb5do+c+CixvUklhNgxVJjTIoJ4Fkw5ff4xy omw8ILMck7ac1TY059fa/+1WYEJ5D39pklUNhmYiZ3pWnFLGN6e8LJLaS42vPuUN4uev 5s1Q== X-Gm-Message-State: ABuFfog9pcW5cY45HotEAsD8iqjf7ddTvmRXv4GnD+eSEUGhhHX5Sqjj Z3T4te+f3TLktTvNv2XF+Q4b1Q== X-Google-Smtp-Source: ACcGV60GZK5TQP4o14T/NwTlxpgv2EWI/xzShu1U22BJeJYnHCyKjiVFlT5g9wajfthr5Pd1v1Wkqw== X-Received: by 2002:a17:902:e111:: with SMTP id cc17-v6mr31350314plb.175.1539896989191; Thu, 18 Oct 2018 14:09:49 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id i29-v6sm35133678pfj.82.2018.10.18.14.09.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Oct 2018 14:09:48 -0700 (PDT) From: Evan Green To: Rob Herring , Mark Rutland , Andy Gross , David Brown , Kishon Vijay Abraham I , Douglas Anderson , Manu Gautam , Can Guo , Vivek Gautam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, swboyd@chromium.org Cc: Evan Green Subject: [PATCH v2 1/5] dt-bindings: phy-qcom-qmp: Fix register underspecification Date: Thu, 18 Oct 2018 14:09:29 -0700 Message-Id: <20181018210933.113592-2-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181018210933.113592-1-evgreen@chromium.org> References: <20181018210933.113592-1-evgreen@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change adds register regions for the second lane of dual-lane nodes. This additional specification is needed so that the driver can stop reaching beyond the tx and rx register allocations to get at the second lane registers in a dual-lane PHY. While in there, document #clock-cells as optional for PHYs that don't provide a pipe clock. Also, document the pcs_misc register region, which was being quietly supplied and used. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring --- This applies atop linux-next 20181018 with the addition of Doug's changes [1] and [2]. [1] https://lore.kernel.org/lkml/20181012213632.252346-1-dianders@chromium.org/ [2] https://lore.kernel.org/lkml/20181012213926.253765-1-dianders@chromium.org/ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 73 +++++++++++++++++++--- 1 file changed, 65 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index fbc198d5dd39..297a7c753fc8 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -25,7 +25,7 @@ Required properties: - For all others: - The reg-names property shouldn't be defined. - - #clock-cells: must be 1 + - #clock-cells: must be 1 (PCIe and USB3 PHYs only) - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe interface (for pipe based PHYs). These clock are then gate-controlled by gcc. @@ -82,23 +82,26 @@ Required nodes: - Each device node of QMP phy is required to have as many child nodes as the number of lanes the PHY has. -Required properties for child node: +Required properties for child nodes of PCIe PHYs (one child per lane): - reg: list of offset and length pairs of register sets for PHY blocks - - - index 0: tx - - index 1: rx - - index 2: pcs - - index 3: pcs_misc (optional) + tx, rx, pcs, and pcs_misc (optional). + - #phy-cells: must be 0 +Required properties for a single "lanes" child node of non-PCIe PHYs: + - reg: list of offset and length pairs of register sets for PHY blocks + For 1-lane devices: + tx, rx, pcs, and (optionally) pcs_misc + For 2-lane devices: + tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc - #phy-cells: must be 0 -Required properties child node of pcie and usb3 qmp phys: +Required properties for child node of PCIe and USB3 qmp phys: - clocks: a list of phandles and clock-specifier pairs, one for each entry in clock-names. - clock-names: Must contain following: "pipe" for pipe clock specific to each lane. - clock-output-names: Name of the PHY clock that will be the parent for the above pipe clock. - For "qcom,ipq8074-qmp-pcie-phy": - "pcie20_phy0_pipe_clk" Pipe Clock parent (or) @@ -150,3 +153,57 @@ Example: ... ... }; + + phy@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0x88eb000 0x18c>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + lane@88eb200 { + reg = <0x88eb200 0x128>, + <0x88eb400 0x1fc>, + <0x88eb800 0x218>, + <0x88e9600 0x70>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + + lanes@1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>, + <0x1d87800 0x108>, + <0x1d87a00 0x1e0>; + #phy-cells = <0>; + }; + }; From patchwork Thu Oct 18 21:09:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 10648251 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5152181D for ; Thu, 18 Oct 2018 21:10:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B661A28D6D for ; Thu, 18 Oct 2018 21:10:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9FE228D85; Thu, 18 Oct 2018 21:10:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 26F2A28D6D for ; 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bh=49D7Ak9Jei7nFdcm9ZwsYdkJxoXvirHyD82k9717FfE=; b=YE5C1DPkv4/4RIQIOyBu06E7VhYVoi8c8O6ABNjo3EnU/evBt4dDyE1PiWu1YMkh9J 5wy19tHc9d8m2nGar1gpfW8ieiEX65KeAQq3Jwte97CDILeJn4rnGGW29yq9GKLFz/4z Uvm/RojIqlshTY+V8GF2C1a1dYovWsz6H8HxtFEfJeZgWzlEng82sDAiwuwOsPFfJ2Ym 9Dpobl5AzaXklo4iMfxSzthC844zb4zP1GlhGD8qWmmbqyy8EEOT0f2qm4KLThgOvUNR OXTa2OBuV5csyUI/M76kVlAj5l941OqQpmz/oK8ekm9C3Zr9siK1+0a4uS9ctWZEg1UT mbEQ== X-Gm-Message-State: ABuFfogLM+GoBjHqD6JoIMpeiMhm88Yk7thEMluya3X0TZSUoNQJIa1F JZr8p4WkGs58KlpzktVixn1chg== X-Google-Smtp-Source: ACcGV60yCrXOZTxqWhcSEw5Zo6R+eMzBiKvl8ic7TiGpw4Y8bYnHywk+sJOUQnXYtpyy4STq7SU5EA== X-Received: by 2002:a17:902:6b82:: with SMTP id p2-v6mr31635729plk.50.1539896993892; Thu, 18 Oct 2018 14:09:53 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id i29-v6sm35133678pfj.82.2018.10.18.14.09.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Oct 2018 14:09:52 -0700 (PDT) From: Evan Green To: Rob Herring , Mark Rutland , Andy Gross , David Brown , Kishon Vijay Abraham I , Douglas Anderson , Manu Gautam , Can Guo , Vivek Gautam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, swboyd@chromium.org Cc: Evan Green Subject: [PATCH v2 2/5] phy: qcom-qmp: Utilize fully-specified DT registers Date: Thu, 18 Oct 2018 14:09:30 -0700 Message-Id: <20181018210933.113592-3-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181018210933.113592-1-evgreen@chromium.org> References: <20181018210933.113592-1-evgreen@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change utilizes the newly fixed up DT bindings to get the tx2 and rx2 register regions for the second lane of dual-lane PHYs. Before this change, the driver was simply using lane one's register region and adding 0x400, which reached well beyond the DT-specified register allocation. This would have been a crash were it not for the page size on ARM64. Fix the driver not to rely on the magic of virtual memory by using the newly specified DT register regions for tx2 and rx2. In order to support existing device trees, this change also contains a fallback mode for when those new register regions don't exist, which reverts to the original behavior of overreaching and prints a complaint. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson --- drivers/phy/qualcomm/phy-qcom-qmp.c | 51 +++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index a83332411026..957da2ef37c1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -72,6 +72,9 @@ #define MAX_PROP_NAME 32 +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -733,9 +736,6 @@ struct qmp_phy_cfg { bool has_phy_dp_com_ctrl; /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; - /* Register offset of secondary tx/rx lanes for USB DP combo PHY */ - unsigned int tx_b_lane_offset; - unsigned int rx_b_lane_offset; /* true, if PCS block has no separate SW_RESET register */ bool no_pcs_sw_reset; @@ -748,6 +748,8 @@ struct qmp_phy_cfg { * @tx: iomapped memory space for lane's tx * @rx: iomapped memory space for lane's rx * @pcs: iomapped memory space for lane's pcs + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @pipe_clk: pipe lock * @index: lane index @@ -759,6 +761,8 @@ struct qmp_phy { void __iomem *tx; void __iomem *rx; void __iomem *pcs; + void __iomem *tx2; + void __iomem *rx2; void __iomem *pcs_misc; struct clk *pipe_clk; unsigned int index; @@ -975,8 +979,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .has_phy_dp_com_ctrl = true, .is_dual_lane_phy = true, - .tx_b_lane_offset = 0x400, - .rx_b_lane_offset = 0x400, }; static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { @@ -1031,9 +1033,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .mask_pcs_ready = PCS_READY, .is_dual_lane_phy = true, - .tx_b_lane_offset = 0x400, - .rx_b_lane_offset = 0x400, - .no_pcs_sw_reset = true, }; @@ -1238,12 +1237,12 @@ static int qcom_qmp_phy_init(struct phy *phy) qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) - qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs, + qcom_qmp_phy_configure(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); if (cfg->is_dual_lane_phy) - qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs, + qcom_qmp_phy_configure(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); @@ -1614,8 +1613,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) /* * Get memory resources for each phy lane: - * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and - * pcs_misc (optional) -> 3. + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. */ qphy->tx = of_iomap(np, 0); if (!qphy->tx) @@ -1629,7 +1629,32 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) if (!qphy->pcs) return -ENOMEM; - qphy->pcs_misc = of_iomap(np, 3); + /* + * If this is a dual-lane PHY, then there should be registers for the + * second lane. Some old device trees did not specify this, so fall + * back to old legacy behavior of assuming they can be reached at an + * offset from the first lane. + */ + if (qmp->cfg->is_dual_lane_phy) { + qphy->tx2 = of_iomap(np, 3); + qphy->rx2 = of_iomap(np, 4); + if (!qphy->tx2 || !qphy->rx2) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + + /* In the old version, pcs_misc is at index 3. */ + qphy->pcs_misc = qphy->tx2; + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { + qphy->pcs_misc = of_iomap(np, 5); + } + + } else { + qphy->pcs_misc = of_iomap(np, 3); + } + if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); From patchwork Thu Oct 18 21:09:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 10648247 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0AC9D1057 for ; Thu, 18 Oct 2018 21:10:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F088A28D6D for ; Thu, 18 Oct 2018 21:10:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E40BC28D85; Thu, 18 Oct 2018 21:10:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D47628D6D for ; Thu, 18 Oct 2018 21:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727574AbeJSFM7 (ORCPT ); Fri, 19 Oct 2018 01:12:59 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:43275 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727528AbeJSFMu (ORCPT ); Fri, 19 Oct 2018 01:12:50 -0400 Received: by mail-pf1-f193.google.com with SMTP id p24-v6so15441551pff.10 for ; Thu, 18 Oct 2018 14:09:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C21QYdTfz09iS1Hzt4A9FPL9X6rUDQrdVSY18Xmu2nc=; b=j3AUMW06Zb+x5XcfA2ieAgwKBdqTQXet6fKLzyexCpDMAV80GUZtajHaezgL1+Cb5x LOFI/+ccXerSqgE0YAgKWNdejoqa+OUz/DMOEUuTKFekIWhZvVfvzwHeU92uXlptaHyl t+pMcumyEFKi/Zej79xdF5BiZWsVtcMN2N6MM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C21QYdTfz09iS1Hzt4A9FPL9X6rUDQrdVSY18Xmu2nc=; b=L5hX68s8Tv41Enw6WqVgrQSuGrIvmZkzQfUC0akJU9GvemXoDNTRs2AlOHE33zR6dX s4HnnRMrR4ZfkIt8y9Ok65wy/T/nxWspf/ymuZXPj4zmcWJ33xGichSelfGlpn0K2m2x fNYTfG2EYb9JAPKcfoBdwafty9KUEsju5emwDN7VVxR9WBDxaq40zv1KHFzPjC4xXCuj aj6rINV8HdSe7OUlO/LMzpOvGJB9T5DNrZYb1/Q2XXFQmZ4SgmRSuATeay4DagT9b9d6 QCO3EEz4S+7XQvel3D+43JWlXmnGP2wMbi7WzbpNJn6MYwZtKnM4mUaSWnuPiKs7fvWy KifQ== X-Gm-Message-State: ABuFfoi99mIeI98pDWQm55Wfh/gli58/gGEcBBLjjpmMLnHVE/uwIiEZ l2Pxj6LawIutuGf920J7ENzDLg== X-Google-Smtp-Source: ACcGV61shdQiXY0/t0sMdshDLoLybA+FspmUwKFllCf/vi2ReR0miNqNTwRCPEUOJ9NibNblXQHa4A== X-Received: by 2002:a63:2503:: with SMTP id l3-v6mr29811965pgl.69.1539896997573; Thu, 18 Oct 2018 14:09:57 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id i29-v6sm35133678pfj.82.2018.10.18.14.09.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Oct 2018 14:09:56 -0700 (PDT) From: Evan Green To: Rob Herring , Mark Rutland , Andy Gross , David Brown , Kishon Vijay Abraham I , Douglas Anderson , Manu Gautam , Can Guo , Vivek Gautam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, swboyd@chromium.org Cc: Evan Green Subject: [PATCH v2 3/5] arm64: dts: qcom: sdm845: add UFS controller Date: Thu, 18 Oct 2018 14:09:31 -0700 Message-Id: <20181018210933.113592-4-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181018210933.113592-1-evgreen@chromium.org> References: <20181018210933.113592-1-evgreen@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change adds the UFS controller and PHY to SDM845. Signed-off-by: Evan Green Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 67 ++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b72bdb0a31a5..9c72edb678ec 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -808,6 +808,73 @@ }; }; + ufshc1: ufshc@1d84000 { + compatible = "qcom,sdm845-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x1d84000 0x2500>; + interrupts = ; + phys = <&ufsphy1_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + power-domains = <&gcc UFS_PHY_GDSC>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + }; + + ufsphy1: phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + + ufsphy1_lanes: lanes@1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>, + <0x1d87800 0x108>, + <0x1d87a00 0x1e0>; + #phy-cells = <0>; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x40000>; From patchwork Thu Oct 18 21:09:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 10648245 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B0AB15E2 for ; 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Thu, 18 Oct 2018 14:10:00 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id i29-v6sm35133678pfj.82.2018.10.18.14.09.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Oct 2018 14:09:59 -0700 (PDT) From: Evan Green To: Rob Herring , Mark Rutland , Andy Gross , David Brown , Kishon Vijay Abraham I , Douglas Anderson , Manu Gautam , Can Guo , Vivek Gautam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, swboyd@chromium.org Cc: Evan Green Subject: [PATCH v2 4/5] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Date: Thu, 18 Oct 2018 14:09:32 -0700 Message-Id: <20181018210933.113592-5-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181018210933.113592-1-evgreen@chromium.org> References: <20181018210933.113592-1-evgreen@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Can Guo This change enables the UFS host controller and PHY on sdm845-mtp. Signed-off-by: Can Guo Signed-off-by: Evan Green Reviewed-by: Vivek Gautam Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index eedfaf8922e2..d5fddea71a85 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -356,6 +356,20 @@ status = "okay"; }; +&ufshc1 { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufsphy1 { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + &usb_1 { status = "okay"; }; From patchwork Thu Oct 18 21:09:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 10648249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 79F281057 for ; Thu, 18 Oct 2018 21:10:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 67C5728D6D for ; Thu, 18 Oct 2018 21:10:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B99028D85; Thu, 18 Oct 2018 21:10:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD1C328D6D for ; Thu, 18 Oct 2018 21:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727620AbeJSFM7 (ORCPT ); Fri, 19 Oct 2018 01:12:59 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:41844 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727602AbeJSFM7 (ORCPT ); Fri, 19 Oct 2018 01:12:59 -0400 Received: by mail-pl1-f195.google.com with SMTP id q17-v6so14869062plr.8 for ; Thu, 18 Oct 2018 14:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vPFTWN6zkNfJc9He9beXBm7dfztDsRrm25G1lDnMPhc=; b=TMYguQOpZs9/KWTcDkHX7kVNjJ8CpHj8E+tlLDHtGAMJFf8es4sZ8VYkUPX2DHHco6 0Yiygc13fROdD0artvEWgTECCSCh7/7p2AdQOLvVA6R+M81KCr8rH8EO/wYkvk7AjlO5 CeSRrE5mNaveiH4FW540lU9sGiX9oRga5K8z4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vPFTWN6zkNfJc9He9beXBm7dfztDsRrm25G1lDnMPhc=; b=J4hCAmOtqy2TPm4E7A2bjpPexopZcAlXB6DgtsrEA7NMfkawhjufYnGUKb6bflxxcU IxyQgLFp0vH8Gk5+FEvURssiVuiNs3s333JQHxEpz0KOK5UDOoMJNpQ2pugv8l+YWE0N Hk3YI3MHnkKRgyNd4gCl45tTlDRfZT+eYacHeQarwSccCknwPBPRFmC0F4GADs0cYx8T eDHGsCn6oJSjp20UlGUHZa1yV/BXyCTb5scdevh7s2lfECaY2xJlaIsrdF8mVFmTPf/E 8krZuboXjbEjWZ537XLM94NvOPb9gXT7vqpCNU51eg301bQKF6OHMJsyAMzpwRG8p86A /xAA== X-Gm-Message-State: ABuFfoi8dxHxWJ+5tUbgnJjOOrQUINPYOeHCoW1U8WrisieWf7A8atey d7mqavoWmm5JwkvKgq2G9okygA== X-Google-Smtp-Source: ACcGV63c8vxi2C4mIJx1dV4GuOQ8CHbqt8NR1/d4qjue/bQ8kDvFsUO1O8YD59MBEARNqdCeBzVqoA== X-Received: by 2002:a17:902:654e:: with SMTP id d14-v6mr31242785pln.292.1539897007352; Thu, 18 Oct 2018 14:10:07 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id i29-v6sm35133678pfj.82.2018.10.18.14.10.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Oct 2018 14:10:06 -0700 (PDT) From: Evan Green To: Rob Herring , Mark Rutland , Andy Gross , David Brown , Kishon Vijay Abraham I , Douglas Anderson , Manu Gautam , Can Guo , Vivek Gautam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, swboyd@chromium.org Cc: Evan Green Subject: [PATCH v2 5/5] arm64: dts: qcom: sdm845: Add USB PHY lane two Date: Thu, 18 Oct 2018 14:09:33 -0700 Message-Id: <20181018210933.113592-6-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181018210933.113592-1-evgreen@chromium.org> References: <20181018210933.113592-1-evgreen@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change adds the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Signed-off-by: Evan Green --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 9c72edb678ec..f28c50e93f5a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1188,10 +1188,12 @@ <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: lane@88e9200 { + usb_1_ssphy: lanes@88e9200 { reg = <0x88e9200 0x128>, <0x88e9400 0x200>, <0x88e9c00 0x218>, + <0x88e9600 0x128>, + <0x88e9800 0x200>, <0x88e9a00 0x100>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; @@ -1219,10 +1221,12 @@ <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; - usb_2_ssphy: lane@88eb200 { + usb_2_ssphy: lanes@88eb200 { reg = <0x88eb200 0x128>, <0x88eb400 0x1fc>, <0x88eb800 0x218>, + <0x88eb600 0x128>, + <0x88eb800 0x1fc>, <0x88e9600 0x70>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;