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Sun, 02 Aug 2020 22:24:40 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 2 Aug 2020 23:23:02 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 14:23:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 14:23:01 +0800 From: Mark-PK Tsai To: Subject: [PATCH 1/2] irqchip: irq-mt58xx: Add mt58xx interrupt controller support Date: Mon, 3 Aug 2020 14:22:13 +0800 Message-ID: <20200803062214.24076-2-mark-pk.tsai@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803062214.24076-1-mark-pk.tsai@mediatek.com> References: <20200803062214.24076-1-mark-pk.tsai@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200803_023516_022283_B77D5A1C X-CRM114-Status: GOOD ( 22.01 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alix.wu@mediatek.com, jason@lakedaemon.net, maz@kernel.org, yj.chiang@mediatek.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add mt58xx interrupt controller support using hierarchy irq domain. Signed-off-by: Mark-PK Tsai --- drivers/irqchip/Kconfig | 7 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mt58xx.c | 196 +++++++++++++++++++++++++++++++++++ 3 files changed, 204 insertions(+) create mode 100644 drivers/irqchip/irq-mt58xx.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 216b3b8392b5..00453af78be0 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -572,4 +572,11 @@ config LOONGSON_PCH_MSI help Support for the Loongson PCH MSI Controller. +config MT58XX_IRQ + bool "MT58XX IRQ" + select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY + help + Support Mediatek MT58XX Interrupt Controller. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 133f9c45744a..5062e9bfa92d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -111,3 +111,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o +obj-$(CONFIG_MT58XX_IRQ) += irq-mt58xx.o diff --git a/drivers/irqchip/irq-mt58xx.c b/drivers/irqchip/irq-mt58xx.c new file mode 100644 index 000000000000..e45ad023afa6 --- /dev/null +++ b/drivers/irqchip/irq-mt58xx.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020 MediaTek Inc. + * Author Mark-PK Tsai + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_MASK 0x0 +#define INTC_EOI 0x20 + +struct mtk_intc_chip_data { + char *name; + struct irq_chip chip; + unsigned int irq_start, nr_irqs; + void __iomem *base; +}; + +static void mtk_poke_irq(struct irq_data *d, u32 offset) +{ + struct mtk_intc_chip_data *cd = irq_data_get_irq_chip_data(d); + void __iomem *base = cd->base; + u8 index = (u8)irqd_to_hwirq(d); + u16 val, mask; + + mask = 1 << (index % 16); + val = readw_relaxed(base + offset + (index / 16) * 4) | mask; + writew_relaxed(val, base + offset + (index / 16) * 4); +} + +static void mtk_clear_irq(struct irq_data *d, u32 offset) +{ + struct mtk_intc_chip_data *cd = irq_data_get_irq_chip_data(d); + void __iomem *base = cd->base; + u8 index = (u8)irqd_to_hwirq(d); + u16 val, mask; + + mask = 1 << (index % 16); + val = readw_relaxed(base + offset + (index / 16) * 4) & ~mask; + writew_relaxed(val, base + offset + (index / 16) * 4); +} + +static void mtk_intc_mask_irq(struct irq_data *d) +{ + mtk_poke_irq(d, INTC_MASK); + irq_chip_mask_parent(d); +} + +static void mtk_intc_unmask_irq(struct irq_data *d) +{ + mtk_clear_irq(d, INTC_MASK); + irq_chip_unmask_parent(d); +} + +static void mtk_intc_eoi_irq(struct irq_data *d) +{ + mtk_poke_irq(d, INTC_EOI); + irq_chip_eoi_parent(d); +} + +static struct irq_chip mtk_intc_chip = { + .irq_mask = mtk_intc_mask_irq, + .irq_unmask = mtk_intc_unmask_irq, + .irq_eoi = mtk_intc_eoi_irq, + .irq_get_irqchip_state = irq_chip_get_parent_state, + .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, + .irq_set_type = irq_chip_set_type_parent, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int mt58xx_intc_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count != 3) + return -EINVAL; + + /* No PPI should point to this domain */ + if (fwspec->param[0] != 0) + return -EINVAL; + + *hwirq = fwspec->param[1]; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + return 0; + } + + return -EINVAL; +} + +static int mt58xx_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + int i; + irq_hw_number_t hwirq; + struct irq_fwspec parent_fwspec, *fwspec = data; + struct mtk_intc_chip_data *cd = (struct mtk_intc_chip_data *)domain->host_data; + + /* Not GIC compliant */ + if (fwspec->param_count != 3) + return -EINVAL; + + /* No PPI should point to this domain */ + if (fwspec->param[0]) + return -EINVAL; + + if (fwspec->param[1] >= cd->nr_irqs) + return -EINVAL; + + hwirq = fwspec->param[1]; + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &cd->chip, + domain->host_data); + + parent_fwspec = *fwspec; + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param[1] = cd->irq_start + hwirq; + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec); +} + +static const struct irq_domain_ops mt58xx_intc_domain_ops = { + .translate = mt58xx_intc_domain_translate, + .alloc = mt58xx_intc_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +int __init +mt58xx_intc_of_init(struct device_node *dn, struct device_node *parent) +{ + static int nr_intc; + struct irq_domain *domain, *domain_parent; + struct mtk_intc_chip_data *cd; + unsigned int irq_start, irq_end; + + domain_parent = irq_find_host(parent); + if (!domain_parent) { + pr_err("mt58xx-intc: interrupt-parent not found\n"); + return -EINVAL; + } + + cd = kzalloc(sizeof(*cd), GFP_KERNEL); + if (!cd) + return -ENOMEM; + + cd->chip = mtk_intc_chip; + if (of_property_read_u32_index(dn, "mediatek,irqs-map-range", 0, &irq_start) || + of_property_read_u32_index(dn, "mediatek,irqs-map-range", 1, &irq_end)) { + kfree(cd); + return -EINVAL; + } + + if (of_property_read_bool(dn, "mediatek,intc-no-eoi")) + cd->chip.irq_eoi = irq_chip_eoi_parent; + + cd->irq_start = irq_start; + cd->nr_irqs = irq_end - irq_start + 1; + cd->chip.name = kasprintf(GFP_KERNEL, "mt58xx-intc-%d", nr_intc++); + if (!cd->chip.name) { + kfree(cd); + return -ENOMEM; + } + + cd->base = of_iomap(dn, 0); + if (!cd->base) { + kfree(cd->chip.name); + kfree(cd); + return -ENOMEM; + } + + domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, + dn, &mt58xx_intc_domain_ops, cd); + if (!domain) { + kfree(cd->chip.name); + iounmap(cd->base); + kfree(cd); + return -ENOMEM; + } + + return 0; +} + +IRQCHIP_DECLARE(mt58xx_intc, "mediatek,mt58xx-intc", mt58xx_intc_of_init); From patchwork Mon Aug 3 06:22:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TWFyay1QSyBUc2FpICjolKHmspvliZsp?= X-Patchwork-Id: 11697411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7494F13B1 for ; Mon, 3 Aug 2020 06:34:43 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 19A97206D7 for ; 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Signed-off-by: Mark-PK Tsai --- .../mediatek,mt58xx-intc.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mt58xx-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt58xx-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt58xx-intc.yaml new file mode 100644 index 000000000000..23e04763ab86 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt58xx-intc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT58XX Interrupt Controller + +maintainers: + - Mark-PK Tsai + +description: |+ + Mediatek DTV SoCs contain multiple legacy interrupt controllers that + routes interrupts to the GIC. All the mt58xx SoCs have this + controller, hence the name of binding. + + The HW block exposes a number of interrupt controllers, each + can support up to 64 interrupts. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + - items: + - const: mediatek,mt58xx-intc + + interrupt-controller: true + + "#address-cells": + enum: [ 0, 1 ] + "#size-cells": + const: 1 + + "#interrupt-cells": + const: 3 + description: | + Use the same format as specified by GIC in arm,gic.yaml. + + reg: + description: | + Physical base address of the MT58xx interrupt controller + registers and length of memory mapped region. + + mediatek,irqs-map-range: + description: | + The range of parent interrupt controller's interrupt lines + that are hardwired to MT58xx interrupt controller. + + mediatek,intc-no-eoi: + description: | + Mark this controller has no End Of Interrupt(EOI) implementation. + This is a empty, boolean property. + +required: + - compatible + - reg + - mediatek,irqs-map-range + +examples: + - | + mt58xx_intc0: interrupt-controller@1f2032d0 { + compatible = "mediatek,mt58xx-intc"; + interrupt-controller; + #interrupt-cells = <0x3>; + interrupt-parent = <&gic>; + reg = <0x0 0x1f2032d0 0x0 0x30>; + mediatek,irqs-map-range = <0 63>; + }; +...