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This fix is applied as gstreamer alsasink gets stuck with the default buffer-time and latency-time parameters with 4 byte buffer alignment. Signed-off-by: Mohan Kumar --- sound/pci/hda/hda_tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index 5637f0129932..ecf98eb9df36 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -333,6 +333,8 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) gcap = azx_readw(chip, GCAP); dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); + chip->align_buffer_size = 1; + /* read number of streams from GCAP register instead of using * hardcoded value */ From patchwork Wed Aug 5 09:11:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar X-Patchwork-Id: 11701591 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CC9DE722 for ; Wed, 5 Aug 2020 09:13:37 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 666BF22CF8 for ; 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Wed, 05 Aug 2020 02:11:39 -0700 From: Mohan Kumar To: , Subject: [PATCH 2/3] ALSA: hda: Add behaviour flag for dma stop delay Date: Wed, 5 Aug 2020 14:41:15 +0530 Message-ID: <20200805091116.2314-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805091116.2314-1-mkumard@nvidia.com> References: <20200805091116.2314-1-mkumard@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596618651; bh=QLQa3HPgpMXlrNU8auTJWV6It11YYRpHfIV3i5lWL0w=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=l+zjdVaRctQu6Q/Ngsw+CZUQ20tPUzcDQr/TFoEegJYfm/uwSk2wktT7g/VC9zJ6n 6NGouZlhJm32TbOrt2MnVCJFbztMSjVXMbjK03oWLu6jzZUUvxwKM4+ZfuIF6uZP93 QzXuAS5R1m5BFAbf6xcs/aQiKMBLTTbkzgTNq3JoiYUMC0hcQc4IbqgW59E0791PKg X+8NiH4WtH46dta3HIZ7anH8Z3sISiIdWyyNdKSB6O/SbPA9tfSP7taqLv8FRrZhEL Ji645ECbTws+8gQCe6OI7hfGn8f1J/2k2Y+N6o6rBXNR7m4OGGSluy/sPHZK02m1Tw X7oBlTRHq2P2Q== Cc: alsa-devel@alsa-project.org, spujar@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Behaviour flag dma_stop_delay is added as a new member in hdac_bus structure to avoid memory decode error incase DMA RUN bit is not disabled in the given timeout from snd_hdac_stream_sync function and followed by stream reset which results in memory decode error between reset set and clear operation. Signed-off-by: Mohan Kumar --- include/sound/hdaudio.h | 2 ++ sound/hda/hdac_stream.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index c1f78d9a6e47..cf77c6b83016 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -347,6 +347,8 @@ struct hdac_bus { int bdl_pos_adj; /* BDL position adjustment */ + unsigned int dma_stop_delay; + /* locks */ spinlock_t reg_lock; struct mutex cmd_mutex; diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index a38a2af1654f..abe7a1b16fe1 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -150,9 +150,12 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) { unsigned char val; int timeout; + int dma_run_state; snd_hdac_stream_clear(azx_dev); + dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; + snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); udelay(3); timeout = 300; @@ -162,6 +165,10 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) if (val) break; } while (--timeout); + + if (azx_dev->bus->dma_stop_delay && dma_run_state) + udelay(azx_dev->bus->dma_stop_delay); + val &= ~SD_CTL_STREAM_RESET; snd_hdac_stream_writeb(azx_dev, SD_CTL, val); udelay(3); From patchwork Wed Aug 5 09:11:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar X-Patchwork-Id: 11701605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22D73722 for ; Wed, 5 Aug 2020 09:14:55 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B238C22CF8 for ; Wed, 5 Aug 2020 09:14:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="bC/WsbOI"; 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Wed, 05 Aug 2020 02:10:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 05 Aug 2020 02:11:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 05 Aug 2020 02:11:43 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 5 Aug 2020 09:11:42 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 5 Aug 2020 09:11:42 +0000 Received: from mkumard.nvidia.com (Not Verified[10.24.34.162]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 05 Aug 2020 02:11:41 -0700 From: Mohan Kumar To: , Subject: [PATCH 3/3] ALSA: hda/tegra: Add 100us dma stop delay Date: Wed, 5 Aug 2020 14:41:16 +0530 Message-ID: <20200805091116.2314-4-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805091116.2314-1-mkumard@nvidia.com> References: <20200805091116.2314-1-mkumard@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596618653; bh=uZF+fL32kiXr/FFhU7XFb0VNeNdMUglasynYmIpWkSs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=SCUCtsZj/zyCN0eJx6ccBmjzvkvz51vk6bicoRkWPk7y0gCB85QxgDU2s33Qtdir1 Q4wM/ECwEXRm4PlKMf4L786Lo3EJ7jdF44Fl3GySa2q+o/Xv5uRoJriXx5CBWjW9y2 pVq9zFmrWlAWa4bsV+TjnJ5gKgI3WkGq19mGBY0iIju9KBvjI/8BfyuyTQbPxcBXXQ m7cVVoUuLjnE9srwBfDtCoqH4VQomMe2a1wogiB6cvKyeA+KTmPUUVi03gxXEMjDA1 ViS12XznCyn9ew+g6/O5gUpueQDBdL4EBcidQqyIVCwrNUeCPysOZ0QvGuAO83Zkjt Mq/ET4Dd0OVWA== Cc: alsa-devel@alsa-project.org, spujar@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Tegra HDA has audio data buffer for upto tens of frames, this buffer can help to avoid underflow. HW will keep issuing new data fetch request when buffers are not full and current BDL is not done. When SW disable DMA RUN bit for a stream, HW can't cancel the already issued data fetch request and hence it can't stop DMA. HW has to wait for all issued data fetch request get data returned before it stops DMA. This HW behavior is not in sync with HDA spec which says DMA RUN bit should be cleared within 1 audio frame. For Tegra, DMA RUN bit was active for more than one audio frame, due to this the timeout in snd_hdac_stream_sync function is not helping. When Stream reset set and clear happens during DMA RUN bit active state it results in Memory Decode error. Unfortunately, there is no way to detect when these data accesses have completed, but testing has shown that a 100us delay between Stream reset set and clear operation for Tegra avoids the memory decode error. Therefore, adding a 100us dma stop delay. Signed-off-by: Mohan Kumar --- sound/pci/hda/hda_tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index ecf98eb9df36..c94553bcca88 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -308,6 +308,7 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) return err; } bus->irq = irq_id; + bus->dma_stop_delay = 100; card->sync_irq = bus->irq; /*