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a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596621154; bh=xr6uX8YmavJUmyTOqAj79akwf/8Wmbfu9U6LVTS7h30=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=csCHbZ8GcUPsUmU0/JI96BctaukWgpSlHHuJu3ZI60pZheaWCgHIVVCOL7Cv+Qu3s QjHzSoNl0IkYCmKuU4btbRX3YHxsxh8jt/Q9zdyFO9MH7xmNWk4OWZp5eVZpNyC3fY 6gA06yXiT720b1Fq/+JuVa+WUkQjO9EEdmkmxCcN8IzJQAH1sd4iwgUo7M6f0MTSeu GePLTFdNM3UEjVGhxpqKt8kWzaAHIT1dh17GPK3d9gRG18+zgcDbJXmdbbm2NVg0Fw AV0YpYbYewFqSYPkTzCNSGcUgOLWbF0uAgYycDjz9w8r37kcCCWpaoxD2GjLUqW/EL n5If7atWjmFQw== Cc: alsa-devel@alsa-project.org, spujar@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Set chip->align_buffer_size to 1 for Tegra platforms to make the buffer alignment to be multiple of 128 bytes. This fix is applied as gstreamer alsasink gets stuck with the default buffer-time and latency-time parameters with 4 byte buffer alignment. Signed-off-by: Mohan Kumar --- sound/pci/hda/hda_tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index 5637f0129932..ecf98eb9df36 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -333,6 +333,8 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) gcap = azx_readw(chip, GCAP); dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); + chip->align_buffer_size = 1; + /* read number of streams from GCAP register instead of using * hardcoded value */ From patchwork Wed Aug 5 09:52:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar X-Patchwork-Id: 11701661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48E86138A for ; Wed, 5 Aug 2020 09:55:36 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4AE42173E for ; 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Wed, 05 Aug 2020 02:52:49 -0700 From: Mohan Kumar To: , Subject: [PATCH v2 2/3] ALSA: hda: Add dma stop delay variable Date: Wed, 5 Aug 2020 15:22:20 +0530 Message-ID: <20200805095221.5476-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805095221.5476-1-mkumard@nvidia.com> References: <20200805095221.5476-1-mkumard@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596621071; bh=cAI69jqs7EoiWGpTZf5j8qW2hGEhCdiawWF5rWnA2DY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=Ozfzo0EzAYvJ55O+ZCLIdD/eoIbmaVchC/ISaRm8GMmXxsHQpYg04exA6Wq2SB4LC t+nAvOd0ZXmdLy2Crtn2CSlKGfW5VMeHlT95I8O+aoNIF9bMFZhkwoLpyKY6LAkTaI j6rIx2WF+Jksd8rpFS/QnBXPLbwSxiM+2IjupQZnGZ39JAQ9YXm16B7PUcXlggAPG6 mgFtybQDRw/PeNwh3axyN0E/kUBnOjkx1KTzHO0Lt7QPJO/X7f3e35NzoX0fZaY0/0 CiNP1Vkt+o/sBOJUQ2pNCsbpRAucTQROdUu1VcjmfwOvZ8BUBGbzTyroKUBNu520Vy ZyxAhkQNvPV3w== Cc: alsa-devel@alsa-project.org, spujar@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" A variable dma_stop_delay is added as a new member in hdac_bus structure to avoid memory decode error incase DMA RUN bit is not disabled in the given timeout from snd_hdac_stream_sync function and followed by stream reset which results in memory decode error between reset set and clear operation. Signed-off-by: Mohan Kumar --- include/sound/hdaudio.h | 3 +++ sound/hda/hdac_stream.c | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index c1f78d9a6e47..6eed61e6cf8a 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -347,6 +347,9 @@ struct hdac_bus { int bdl_pos_adj; /* BDL position adjustment */ + /* delay time in us for dma stop */ + unsigned int dma_stop_delay; + /* locks */ spinlock_t reg_lock; struct mutex cmd_mutex; diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index a38a2af1654f..abe7a1b16fe1 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -150,9 +150,12 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) { unsigned char val; int timeout; + int dma_run_state; snd_hdac_stream_clear(azx_dev); + dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; + snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); udelay(3); timeout = 300; @@ -162,6 +165,10 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) if (val) break; } while (--timeout); + + if (azx_dev->bus->dma_stop_delay && dma_run_state) + udelay(azx_dev->bus->dma_stop_delay); + val &= ~SD_CTL_STREAM_RESET; snd_hdac_stream_writeb(azx_dev, SD_CTL, val); udelay(3); From patchwork Wed Aug 5 09:52:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar X-Patchwork-Id: 11701663 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9EA7C138A for ; Wed, 5 Aug 2020 09:56:21 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 35A352076E for ; Wed, 5 Aug 2020 09:56:21 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wed, 05 Aug 2020 02:52:51 -0700 From: Mohan Kumar To: , Subject: [PATCH v2 3/3] ALSA: hda/tegra: Add 100us dma stop delay Date: Wed, 5 Aug 2020 15:22:21 +0530 Message-ID: <20200805095221.5476-4-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805095221.5476-1-mkumard@nvidia.com> References: <20200805095221.5476-1-mkumard@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596621159; bh=uZF+fL32kiXr/FFhU7XFb0VNeNdMUglasynYmIpWkSs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=Ue6pmgESI0KEd18bPXWXznCxRraZq044VlQbBMpliDuMu2N0F1h1v/pFid4D6688d Nb0JkeAN+Ekydp+UEcHyDK5J1a3QRptFSNm0CtRD43qNDdjL7RyycPdnx8/ZUQoYXq Iqz9RMTwdt6zxxPVl9nT8BdMEvZ+pFIJZGk51nrXkfo7g5jE7GzM3BFxik5pM7HM1x nJIO1r2w8Sg4SVspz9dAS/4CCPcZ4K9XrvUVyo396ErdgLbgjlnm1VtkTx170sBgp4 EwcAs/QtNAtVOq0ZytBV+HlDnqEzAdqcEhXpldtXniMFfC/2jNNv2V+kkHr2fdqV6T Pe0sz3F0iK+Cg== Cc: alsa-devel@alsa-project.org, spujar@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Tegra HDA has audio data buffer for upto tens of frames, this buffer can help to avoid underflow. HW will keep issuing new data fetch request when buffers are not full and current BDL is not done. When SW disable DMA RUN bit for a stream, HW can't cancel the already issued data fetch request and hence it can't stop DMA. HW has to wait for all issued data fetch request get data returned before it stops DMA. This HW behavior is not in sync with HDA spec which says DMA RUN bit should be cleared within 1 audio frame. For Tegra, DMA RUN bit was active for more than one audio frame, due to this the timeout in snd_hdac_stream_sync function is not helping. When Stream reset set and clear happens during DMA RUN bit active state it results in Memory Decode error. Unfortunately, there is no way to detect when these data accesses have completed, but testing has shown that a 100us delay between Stream reset set and clear operation for Tegra avoids the memory decode error. Therefore, adding a 100us dma stop delay. Signed-off-by: Mohan Kumar --- sound/pci/hda/hda_tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index ecf98eb9df36..c94553bcca88 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -308,6 +308,7 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) return err; } bus->irq = irq_id; + bus->dma_stop_delay = 100; card->sync_irq = bus->irq; /*