From patchwork Thu Aug 6 12:18:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11703487 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 138791392 for ; Thu, 6 Aug 2020 16:30:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5564F204FD for ; Thu, 6 Aug 2020 16:30:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SFkWefrh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728298AbgHFQaW (ORCPT ); Thu, 6 Aug 2020 12:30:22 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:46223 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727800AbgHFQ24 (ORCPT ); Thu, 6 Aug 2020 12:28:56 -0400 X-UUID: 63ebca70441545afb7dbb3ce575d5f3a-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JZ86xIMebilEvlp79Twszym4JnEpu5xLVQiKKFL0Rbg=; b=SFkWefrhHraW8b1UN/wdeW8EiGOXwnWSnplaDkfSw8Fp4l9sukuFxE8Q8x/lbah8GKDN4staOXWsT+gEiYC/7uocVZwGA5xle6ihYNm053YvDRpkisM7Q2nG11A3ycRZZZB4ZLRhicqx1ubCLohmvZv++O7nEQ7BicLnfQe1y/U=; X-UUID: 63ebca70441545afb7dbb3ce575d5f3a-20200806 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 180744894; Thu, 06 Aug 2020 20:18:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 20:18:42 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 20:18:43 +0800 From: Hector Yuan To: , , , , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Catalin Marinas , Will Deacon , Matthias Brugger , Bjorn Andersson , Shawn Guo , Li Yang , Vinod Koul , Arnd Bergmann , Anson Huang , Geert Uytterhoeven , Olof Johansson CC: , Subject: [PATCH v1 1/2] cpufreq: mediatek-hw: Add support for Mediatek cpufreq HW driver Date: Thu, 6 Aug 2020 20:18:39 +0800 Message-ID: <1596716320-19811-2-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1596716320-19811-1-git-send-email-hector.yuan@mediatek.com> References: <1596716320-19811-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 42A5787A7FDE4CFE2E60EF9A02322FB287087D54C7179A4681EB51728BEF576C2000:8 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add MT6779 cpufreq HW support. Signed-off-by: Hector.Yuan --- arch/arm64/configs/defconfig | 1 + drivers/cpufreq/Kconfig.arm | 11 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/mediatek-cpufreq-hw.c | 255 +++++++++++++++++++++++++++++++++ 4 files changed, 268 insertions(+) create mode 100644 drivers/cpufreq/mediatek-cpufreq-hw.c diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 883e8ba..866a1bf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -86,6 +86,7 @@ CONFIG_CPUFREQ_DT=y CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m CONFIG_ARM_ARMADA_37XX_CPUFREQ=y +CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_IMX_CPUFREQ_DT=m CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index c6cbfc8..81f1cc1 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -121,6 +121,17 @@ config ARM_MEDIATEK_CPUFREQ help This adds the CPUFreq driver support for MediaTek SoCs. +config ARM_MEDIATEK_CPUFREQ_HW + tristate "MediaTek CPUFreq HW driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Support for the CPUFreq HW driver. + Some MediaTek chipsets have a HW engine to offload the steps + necessary for changing the frequency of the CPUs. Firmware loaded + in this engine exposes a programming interface to the OS. + The driver implements the cpufreq interface for this HW engine. + Say Y if you want to support CPUFreq HW. + config ARM_OMAP2PLUS_CPUFREQ bool "TI OMAP2+" depends on ARCH_OMAP2PLUS diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index f6670c4..dc1f371 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o +obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ_HW) += mediatek-cpufreq-hw.o obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c new file mode 100644 index 0000000..920cc87 --- /dev/null +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LUT_MAX_ENTRIES 32U +#define LUT_FREQ GENMASK(11, 0) +#define LUT_VOLT GENMASK(28, 12) +#define LUT_ROW_SIZE 0x4 + +/* Register offsets */ +#define REG_ENABLE 0x84 +#define REG_PERF_STATE 0x88 + +static struct platform_device *global_pdev; +static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, + unsigned int index) +{ + void __iomem *perf_state_reg = policy->driver_data; + unsigned long freq = policy->freq_table[index].frequency; + + writel_relaxed(index, perf_state_reg); + arch_set_freq_scale(policy->related_cpus, freq, + policy->cpuinfo.max_freq); + return 0; +} + +static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) +{ + void __iomem *perf_state_reg; + struct cpufreq_policy *policy; + unsigned int index; + + policy = cpufreq_cpu_get_raw(cpu); + if (!policy) + return 0; + + perf_state_reg = policy->driver_data; + + index = readl_relaxed(perf_state_reg); + index = min(index, LUT_MAX_ENTRIES - 1); + + return policy->freq_table[index].frequency; +} + +static int mtk_cpufreq_hw_read_lut(struct device *cpu_dev, + struct cpufreq_policy *policy, + void __iomem *base) +{ + u32 data; + u32 freq, volt, prev_freq = 0; + int i = 0; + struct cpufreq_frequency_table *table; + + table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); + if (!table) + return -ENOMEM; + + for (i = 0; i < LUT_MAX_ENTRIES; i++) { + data = readl_relaxed(base + (i * LUT_ROW_SIZE)); + freq = FIELD_GET(LUT_FREQ, data) * 1000; + volt = FIELD_GET(LUT_VOLT, data); + if (freq != prev_freq) { + table[i].frequency = freq; + dev_pm_opp_add(cpu_dev, freq * 1000, volt); + dev_dbg(cpu_dev, "index=%d freq=%d, volt=%d\n", i, + freq, volt); + } else { + break; + } + prev_freq = freq; + } + table[i].frequency = CPUFREQ_TABLE_END; + policy->freq_table = table; + dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); + + return 0; +} + +static void mtk_get_related_cpus(int index, struct cpumask *m) +{ + struct device_node *cpu_np; + struct of_phandle_args args; + int cpu, ret; + + for_each_possible_cpu(cpu) { + cpu_np = of_cpu_device_node_get(cpu); + if (!cpu_np) + continue; + + ret = of_parse_phandle_with_args(cpu_np, "mtk,freq-domain", + "#freq-domain-cells", 0, + &args); + of_node_put(cpu_np); + if (ret < 0) + continue; + + if (index == args.args[0]) + cpumask_set_cpu(cpu, m); + } +} + +static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) +{ + struct device *dev = &global_pdev->dev; + struct of_phandle_args args; + struct device_node *cpu_np; + struct device *cpu_dev; + struct resource *res; + void __iomem *base; + int ret, index; + + cpu_dev = get_cpu_device(policy->cpu); + if (!cpu_dev) { + pr_err("%s: failed to get cpu%d device\n", __func__, + policy->cpu); + return -ENODEV; + } + + cpu_np = of_cpu_device_node_get(policy->cpu); + if (!cpu_np) + return -EINVAL; + + ret = of_parse_phandle_with_args(cpu_np, "mtk,freq-domain", + "#freq-domain-cells", 0, &args); + of_node_put(cpu_np); + if (ret) + return ret; + + index = args.args[0]; + res = platform_get_resource(global_pdev, IORESOURCE_MEM, index); + if (!res) + return -ENODEV; + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + mtk_get_related_cpus(index, policy->cpus); + if (!cpumask_weight(policy->cpus)) { + dev_err(dev, "Domain-%d failed to get related CPUs\n", index); + ret = -ENOENT; + goto error; + } + + policy->driver_data = base + REG_PERF_STATE; + ret = mtk_cpufreq_hw_read_lut(cpu_dev, policy, base); + if (ret) { + dev_err(dev, "Domain-%d failed to read LUT\n", index); + goto error; + } + + ret = dev_pm_opp_get_opp_count(cpu_dev); + if (ret <= 0) { + dev_err(cpu_dev, "Failed to add OPPs\n"); + ret = -ENODEV; + goto error; + } + + dev_pm_opp_of_register_em(policy->cpus); + + /* HW should be in enabled state to proceed now */ + writel_relaxed(0x1, (base + REG_ENABLE)); + return 0; +error: + devm_iounmap(dev, base); + return ret; +} + +static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) +{ + struct device *cpu_dev = get_cpu_device(policy->cpu); + void __iomem *base = policy->driver_data - REG_PERF_STATE; + + dev_pm_opp_remove_all_dynamic(cpu_dev); + kfree(policy->freq_table); + devm_iounmap(&global_pdev->dev, base); + + return 0; +} + +static struct freq_attr *mtk_cpufreq_hw_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL +}; + +static struct cpufreq_driver cpufreq_mtk_hw_driver = { + .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | + CPUFREQ_HAVE_GOVERNOR_PER_POLICY, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = mtk_cpufreq_hw_target_index, + .get = mtk_cpufreq_hw_get, + .init = mtk_cpufreq_hw_cpu_init, + .exit = mtk_cpufreq_hw_cpu_exit, + .name = "mtk-cpufreq-hw", + .attr = mtk_cpufreq_hw_attr, +}; + +static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev) +{ + int ret; + + global_pdev = pdev; + ret = cpufreq_register_driver(&cpufreq_mtk_hw_driver); + if (ret) + dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); + else + dev_dbg(&pdev->dev, "mtk CPUFreq HW driver initialized\n"); + + return ret; +} + +static int mtk_cpufreq_hw_driver_remove(struct platform_device *pdev) +{ + return cpufreq_unregister_driver(&cpufreq_mtk_hw_driver); +} + +static const struct of_device_id mtk_cpufreq_hw_match[] = { + { .compatible = "mediatek,cpufreq-hw" }, + {} +}; +MODULE_DEVICE_TABLE(of, mtk_cpufreq_hw_match); + +static struct platform_driver mtk_cpufreq_hw_driver = { + .probe = mtk_cpufreq_hw_driver_probe, + .remove = mtk_cpufreq_hw_driver_remove, + .driver = { + .name = "mtk-cpufreq-hw", + .of_match_table = mtk_cpufreq_hw_match, + }, +}; + +static int __init mtk_cpufreq_hw_init(void) +{ + return platform_driver_register(&mtk_cpufreq_hw_driver); +} +postcore_initcall(mtk_cpufreq_hw_init); + +static void __exit mtk_cpufreq_hw_exit(void) +{ + platform_driver_unregister(&mtk_cpufreq_hw_driver); +} +module_exit(mtk_cpufreq_hw_exit); + +MODULE_DESCRIPTION("mtk CPUFREQ HW Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Aug 6 12:18:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11703787 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D2F0722 for ; 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X-UUID: 8a705a9515e04b39a6104849cbefd20c-20200806 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 63181443; Thu, 06 Aug 2020 20:18:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 20:18:43 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 20:18:44 +0800 From: Hector Yuan To: , , , , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Catalin Marinas , Will Deacon , Matthias Brugger , Bjorn Andersson , Shawn Guo , Li Yang , Vinod Koul , Arnd Bergmann , Anson Huang , Geert Uytterhoeven , Olof Johansson CC: , Subject: [PATCH v1 2/2] dt-bindings: cpufreq: add MediaTek cpufreq bindings Date: Thu, 6 Aug 2020 20:18:40 +0800 Message-ID: <1596716320-19811-3-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1596716320-19811-1-git-send-email-hector.yuan@mediatek.com> References: <1596716320-19811-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add devicetree bindings for MediaTek HW driver. Signed-off-by: Hector.Yuan --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..2a35098 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: mediatek,cpufreq-hw + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + + reg-names: + items: + - const: "freq-domain0" + - const: "freq-domain1" + description: | + Frequency domain name. + + "#freq-domain-cells": + const: 1 + description: | + Number of cells in a freqency domain specifier. + +required: + - compatible + - reg + - reg-names + - "#freq-domain-cells" + +additionalProperties: false + +examples: + - | + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + reg-names = "freq-domain0", "freq-domain1"; + #freq-domain-cells = <1>; + }; +