From patchwork Fri Aug 7 09:35:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705357 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31EB61392 for ; Fri, 7 Aug 2020 10:01:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C73F20855 for ; Fri, 7 Aug 2020 10:01:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C73F20855 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A9246E9B9; Fri, 7 Aug 2020 10:01:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 80C396E9B5; Fri, 7 Aug 2020 10:01:46 +0000 (UTC) IronPort-SDR: a1R4Y+7H93n73BhobYq+eZ0yZdsXDLty+8/c3rKPpFBV0Wi4LA964fxeaSDvy67eRg1yjiGjx7 grSI1jB71OQg== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604141" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604141" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:01:46 -0700 IronPort-SDR: raQkrlO0NJZRC3Rn7DXmZDN/xgHgn6LcaCskJc3orb129VSc3LNpzh6xF227tq2Av/jMsebhhn RSwuRI17DmHg== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178357" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:01:42 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:45 +0530 Message-Id: <20200807093551.10673-2-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 1/7] drm/i915: Add enable/disable flip done and flip done handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add enable/disable flip done functions and the flip done handler function which handles the flip done interrupt. Enable the flip done interrupt in IER. Enable flip done function is called before writing the surface address register as the write to this register triggers the flip done interrupt Flip done handler is used to send the page flip event as soon as the surface address is written as per the requirement of async flips. The interrupt is disabled after the event is sent. v2: -Change function name from icl_* to skl_* (Paulo) -Move flip handler to this patch (Paulo) -Remove vblank_put() (Paulo) -Enable flip done interrupt for gen9+ only (Paulo) -Enable flip done interrupt in power_well_post_enable hook (Paulo) -Removed the event check in flip done handler to handle async flips without pageflip events. v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) -Make the pending vblank event NULL in the beginning of flip_done_handler to remove sporadic WARN_ON that is seen. v4: -Calculate timestamps using flip done time stamp and current timestamp for async flips (Ville) v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter' static.(Reported-by: kernel test robot ) -Fix the typo in commit message. v6: -Revert back to old time stamping code. -Remove the break while calling skl_enable_flip_done. (Paulo) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 8 +++ drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.h | 2 + 3 files changed, 62 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 522c772a2111..1ac2e6f27597 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15562,6 +15562,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_dbuf_pre_plane_update(state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) + skl_enable_flip_done(&crtc->base); + } + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display.commit_modeset_enables(state); @@ -15583,6 +15588,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) drm_atomic_helper_wait_for_flip_done(dev, &state->base); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) + skl_disable_flip_done(&crtc->base); + if (new_crtc_state->hw.active && !needs_modeset(new_crtc_state) && !new_crtc_state->preload_luts && diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f113fe44572b..6cc129b031d3 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, u32 crc4) {} #endif +static void flip_done_handler(struct drm_i915_private *dev_priv, + unsigned int pipe) +{ + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + struct drm_crtc_state *crtc_state = crtc->base.state; + struct drm_pending_vblank_event *e = crtc_state->event; + struct drm_device *dev = &dev_priv->drm; + unsigned long irqflags; + + spin_lock_irqsave(&dev->event_lock, irqflags); + + crtc_state->event = NULL; + + drm_crtc_send_vblank_event(&crtc->base, e); + + spin_unlock_irqrestore(&dev->event_lock, irqflags); +} static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) + flip_done_handler(dev_priv, pipe); + if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) return 0; } +void skl_enable_flip_done(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } +void skl_disable_flip_done(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + static void ibx_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; + if (INTEL_GEN(dev_priv) >= 9) + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; + spin_lock_irq(&dev_priv->irq_lock); if (!intel_irqs_enabled(dev_priv)) { @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; + if (INTEL_GEN(dev_priv) >= 9) + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; + de_port_enables = de_port_masked; if (IS_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 25f25cd95818..2f10c8135116 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); int i965_enable_vblank(struct drm_crtc *crtc); int ilk_enable_vblank(struct drm_crtc *crtc); int bdw_enable_vblank(struct drm_crtc *crtc); +void skl_enable_flip_done(struct drm_crtc *crtc); void i8xx_disable_vblank(struct drm_crtc *crtc); void i915gm_disable_vblank(struct drm_crtc *crtc); void i965_disable_vblank(struct drm_crtc *crtc); void ilk_disable_vblank(struct drm_crtc *crtc); void bdw_disable_vblank(struct drm_crtc *crtc); +void skl_disable_flip_done(struct drm_crtc *crtc); void gen2_irq_reset(struct intel_uncore *uncore); void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, From patchwork Fri Aug 7 09:35:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705359 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 000B614B7 for ; Fri, 7 Aug 2020 10:01:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE82B20748 for ; Fri, 7 Aug 2020 10:01:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE82B20748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C7F746E9BA; Fri, 7 Aug 2020 10:01:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 178166E9BA; Fri, 7 Aug 2020 10:01:50 +0000 (UTC) IronPort-SDR: UaWrgdQYZYdjUJW3ykyEnKqeBtAdPXjSgb7oo3pSwBzloXCjSKsBHDqny3ELW7GKSGm6MBqfZt RRbejIYKS+7g== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604146" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604146" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:01:49 -0700 IronPort-SDR: POPM4rkPD7a1Kjkg12UPbfnxP6o86mWZ6F/aM1FQQJie5TDq3WXCCoYbMkTj/1MF6oFTK/QgQ0 +kpYDKYPEiZg== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178367" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:01:46 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:46 +0530 Message-Id: <20200807093551.10673-3-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 2/7] drm/i915: Add support for async flips in I915 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set the Async Address Update Enable bit in plane ctl when async flip is requested. v2: -Move the Async flip enablement to individual patch (Paulo) v3: -Rebased. v4: -Add separate plane hook for async flip case (Ville) v5: -Rebased. v6: -Move the plane hook to separate patch. (Paulo) -Remove the early return in skl_plane_ctl. (Paulo) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1ac2e6f27597..ce2b0c14a073 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4768,6 +4768,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl = PLANE_CTL_ENABLE; + if (crtc_state->uapi.async_flip) + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { plane_ctl |= skl_plane_ctl_alpha(plane_state); plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e85c6fc1f3cb..3f88d9ac90a8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6924,6 +6924,7 @@ enum { #define PLANE_CTL_TILED_X (1 << 10) #define PLANE_CTL_TILED_Y (4 << 10) #define PLANE_CTL_TILED_YF (5 << 10) +#define PLANE_CTL_ASYNC_FLIP (1 << 9) #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ From patchwork Fri Aug 7 09:35:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705365 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B017A1392 for ; Fri, 7 Aug 2020 10:01:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A98920748 for ; Fri, 7 Aug 2020 10:01:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A98920748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F29726E9BE; Fri, 7 Aug 2020 10:01:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 292CF6E9BC; Fri, 7 Aug 2020 10:01:54 +0000 (UTC) IronPort-SDR: B7VI0o4tNjK5kmFiPfCVIYBEujjnojtJqo+EQL9yWM8swbgpSAL9NcjZpNwRKk/c4IXJMUEliD RNcP5a5r9qjA== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604158" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604158" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:01:53 -0700 IronPort-SDR: H0gtwNSgG43b9L4hZnNS+NPp5ZELkXr0I7005kkDW9JqyMcIlTi1dSB+GoqyAYxaJBf+sp9nbE NTeELsQyO/IQ== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178385" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:01:50 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:47 +0530 Message-Id: <20200807093551.10673-4-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 3/7] drm/i915: Add checks specific to async flips X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If flip is requested on any other plane, reject it. Make sure there is no change in fbc, offset and framebuffer modifiers when async flip is requested. If any of these are modified, reject async flip. v2: -Replace DRM_ERROR (Paulo) -Add check for changes in OFFSET, FBC, RC(Paulo) v3: -Removed TODO as benchmarking tests have been run now. v4: -Added more state checks for async flip (Ville) -Moved intel_atomic_check_async to the end of intel_atomic_check as the plane checks needs to pass before this. (Ville) -Removed crtc_state->enable_fbc check. (Ville) -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async flip case as scanline counter is not reliable here. v5: -Fix typo and other check patch errors seen in CI in 'intel_atomic_check_async' function. v6: -Don't call intel_atomic_check_async multiple times. (Ville) -Remove the check for n_planes in intel_atomic_check_async -Added documentation for async flips. (Paulo) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 113 +++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ce2b0c14a073..9629c751d2af 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14832,6 +14832,110 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, return false; } +/** + * DOC: asynchronous flip implementation + * + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. + * Correspondingly, support is currently added for primary plane only. + * + * Async flip can only change the plane surface address, so anything else + * changing is rejected from the intel_atomic_check_async() function. + * Once this check is cleared, flip done interrupt is enabled using + * the skl_enable_flip_done() function. + * + * As soon as the surface address register is written, flip done interrupt is + * generated and the requested events are sent to the usersapce in the interrupt + * handler itself. The timestamp and sequence sent during the flip done event + * correspond to the last vblank and have no relation to the actual time when + * the flip done event was sent. + */ + +static int intel_atomic_check_async(struct intel_atomic_state *state) +{ + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_plane_state *new_plane_state, *old_plane_state; + struct intel_crtc *crtc; + struct intel_plane *intel_plane; + int i; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (needs_modeset(new_crtc_state)) { + DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n"); + return -EINVAL; + } + + if (!new_crtc_state->uapi.active) { + DRM_DEBUG_KMS("CRTC inactive\n"); + return -EINVAL; + } + if (old_crtc_state->active_planes != new_crtc_state->active_planes) { + DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n"); + return -EINVAL; + } + } + + for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state, + new_plane_state, i) { + /*TODO: Async flip is only supported through the page flip IOCTL + * as of now. So support currently added for primary plane only. + * Support for other planes should be added when async flip is + * enabled in the atomic IOCTL path. + */ + if (intel_plane->id != PLANE_PRIMARY) + return -EINVAL; + + if (old_plane_state->color_plane[0].x != + new_plane_state->color_plane[0].x || + old_plane_state->color_plane[0].y != + new_plane_state->color_plane[0].y) { + DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.fb->modifier != + new_plane_state->uapi.fb->modifier) { + DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.fb->format != + new_plane_state->uapi.fb->format) { + DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n"); + return -EINVAL; + } + + if (intel_wm_need_update(old_plane_state, new_plane_state)) { + DRM_DEBUG_KMS("WM update not allowed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.alpha != new_plane_state->uapi.alpha) { + DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.pixel_blend_mode != + new_plane_state->uapi.pixel_blend_mode) { + DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.color_encoding != new_plane_state->uapi.color_encoding) { + DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.color_range != new_plane_state->uapi.color_range) { + DRM_DEBUG_KMS("Color range cannot be changed in async flip\n"); + return -EINVAL; + } + } + + return 0; +} + /** * intel_atomic_check - validate state object * @dev: drm device @@ -15011,6 +15115,15 @@ static int intel_atomic_check(struct drm_device *dev, "[modeset]" : "[fastset]"); } + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) { + ret = intel_atomic_check_async(state); + if (ret) + goto fail; + + break; + } + } return 0; fail: From patchwork Fri Aug 7 09:35:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705367 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AB1D14B7 for ; Fri, 7 Aug 2020 10:01:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42C5D20748 for ; Fri, 7 Aug 2020 10:01:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42C5D20748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CDE986E9C0; Fri, 7 Aug 2020 10:01:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id A61716E9BD; Fri, 7 Aug 2020 10:01:57 +0000 (UTC) IronPort-SDR: Qhofhgyf3G+ix+SXbXxV5vOLQPIbaJTgLKKFP1OxXVnCgDzonDTsFw7TnftMKBCirOal//4wxQ 5EwYqc02434g== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604163" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604163" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:01:57 -0700 IronPort-SDR: hHhMksox2ps/x8ndnNg/Vhp7oCs+zoufopKI5RiCG7qR6nkpXlGzeM0UsU1BEfR2dJmqpBhCp2 F4hYk064++ZQ== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178391" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:01:53 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:48 +0530 Message-Id: <20200807093551.10673-5-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since the flip done event will be sent in the flip_done_handler, no need to add the event to the list and delay it for later. v2: -Moved the async check above vblank_get as it was causing issues for PSR. v3: -No need to wait for vblank to pass, as this wait was causing a 16ms delay once every few flips. v4: -Rebased. v5: -Rebased. v6: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_sprite.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index c26ca029fc0a..2b2d96c59d7f 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) DEFINE_WAIT(wait); u32 psr_status; + if (new_crtc_state->uapi.async_flip) + goto irq_disable; + vblank_start = adjusted_mode->crtc_vblank_start; if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) vblank_start = DIV_ROUND_UP(vblank_start, 2); @@ -206,7 +209,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) * Would be slightly nice to just grab the vblank count and arm the * event outside of the critical section - the spinlock might spin for a * while ... */ - if (new_crtc_state->uapi.event) { + if (new_crtc_state->uapi.event && !new_crtc_state->uapi.async_flip) { drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base) != 0); @@ -220,6 +223,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) local_irq_enable(); + if (new_crtc_state->uapi.async_flip) + return; + if (intel_vgpu_active(dev_priv)) return; From patchwork Fri Aug 7 09:35:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705373 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12B9714B7 for ; Fri, 7 Aug 2020 10:02:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F17A420855 for ; Fri, 7 Aug 2020 10:02:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F17A420855 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E9DE6E9C2; Fri, 7 Aug 2020 10:02:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 537276E9BF; Fri, 7 Aug 2020 10:02:01 +0000 (UTC) IronPort-SDR: n7xPsudaq2dyqyuQGu0vrWJe3booIqaWiNlxLP1lPNlvfmXpSx6KYcWnkiJ24LgqYRx/iEFCYa X9TuMTTXlzDg== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604166" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604166" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:02:01 -0700 IronPort-SDR: epNt71jN513OSiN8E/62ZWs4O1cV0HxD7N/1YFDHHXEtBmpbXilH+vMvIhXZihXju5PXgLPhLM QyB2DkTsiCxA== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178403" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:01:57 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:49 +0530 Message-Id: <20200807093551.10673-6-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 5/7] drm/i915: Add dedicated plane hook for async flip case X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This hook is added to avoid writing other plane registers in case of async flips, so that we do not write the double buffered registers during async surface address update. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_sprite.c | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 2b2d96c59d7f..1c03546a4d2a 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -609,6 +609,24 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static void +skl_program_async_surface_address(struct drm_i915_private *dev_priv, + const struct intel_plane_state *plane_state, + enum pipe pipe, enum plane_id plane_id, + u32 surf_addr) +{ + unsigned long irqflags; + u32 plane_ctl = plane_state->ctl; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); +} + static void skl_program_plane(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -637,6 +655,13 @@ skl_program_plane(struct intel_plane *plane, u32 keymsk, keymax; u32 plane_ctl = plane_state->ctl; + /* During Async flip, no other updates are allowed */ + if (crtc_state->uapi.async_flip) { + skl_program_async_surface_address(dev_priv, plane_state, + pipe, plane_id, surf_addr); + return; + } + plane_ctl |= skl_plane_ctl_crtc(crtc_state); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) From patchwork Fri Aug 7 09:35:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705375 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9035B14B7 for ; Fri, 7 Aug 2020 10:02:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A7E120855 for ; Fri, 7 Aug 2020 10:02:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7A7E120855 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 051936E9C4; Fri, 7 Aug 2020 10:02:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id F28426E9C3; Fri, 7 Aug 2020 10:02:04 +0000 (UTC) IronPort-SDR: gNeaBZSEvuADU0FtUMyDtRvDAq3TGHoxZJceG9ZvNCYCKUIl2JMgv4RVNg4YPfMsaI7hlrSAHd dBifjDqPqukg== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604171" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604171" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:02:04 -0700 IronPort-SDR: AbDDZWhyyiPKr915D2MtdLvIlbYeiR211KjoHL6NDOrXuBSSse2nO4Q4l33dD2QTYeb/zCAoNn tK0tWOK0Os5Q== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178419" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:02:01 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:50 +0530 Message-Id: <20200807093551.10673-7-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 6/7] Documentation/gpu: Add asynchronous flip documentation for i915 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the details of the implementation of asynchronous flips for i915. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- Documentation/gpu/i915.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 33cc6ddf8f64..84ead508f7ad 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -118,6 +118,12 @@ Atomic Plane Helpers .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c :internal: +Asynchronous Page Flip +---------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c + :doc: asynchronous flip implementation + Output Probing -------------- From patchwork Fri Aug 7 09:35:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11705379 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D14171392 for ; Fri, 7 Aug 2020 10:02:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB99420748 for ; Fri, 7 Aug 2020 10:02:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB99420748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A5636E9BD; Fri, 7 Aug 2020 10:02:09 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B24D96E9BD; Fri, 7 Aug 2020 10:02:08 +0000 (UTC) IronPort-SDR: 99SipvRhL7f0UQrZuA7JAHGCsObYcjEEVpT8Njyhe2+VGTHMxLwdrnHpa8ORsWMFFZjE7fWgjN uKwNamB1vX9w== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="132604178" X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="132604178" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 03:02:08 -0700 IronPort-SDR: 1yCDtPNIVDUIuDLXqk00YYSixtA6ams/6UZD4f1n6lz0ykNJ6eR0QW+O+r4kgUtLJ8Z68lZ0+O 7zZnOrxp9aKQ== X-IronPort-AV: E=Sophos;i="5.75,445,1589266800"; d="scan'208";a="468178433" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 07 Aug 2020 03:02:04 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Aug 2020 15:05:51 +0530 Message-Id: <20200807093551.10673-8-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200807093551.10673-1-karthik.b.s@intel.com> References: <20200807093551.10673-1-karthik.b.s@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 7/7] drm/i915: Enable async flips in i915 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, daniel.vetter@intel.com, harry.wentland@amd.com, nicholas.kazlauskas@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable asynchronous flips in i915 for gen9+ platforms. v2: -Async flip enablement should be a stand alone patch (Paulo) v3: -Move the patch to the end of the serires (Paulo) v4: -Rebased. v5: -Rebased. v6: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9629c751d2af..3574b2700b99 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -17901,6 +17901,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915) mode_config->funcs = &intel_mode_funcs; + if (INTEL_GEN(i915) >= 9) + mode_config->async_page_flip = true; + /* * Maximum framebuffer dimensions, chosen to match * the maximum render engine surface size on gen4+.