From patchwork Fri Oct 19 15:19:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lis, Tomasz" X-Patchwork-Id: 10649629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB60013A4 for ; Fri, 19 Oct 2018 15:19:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A98BA26255 for ; Fri, 19 Oct 2018 15:19:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9D22626E75; Fri, 19 Oct 2018 15:19:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E75332624B for ; Fri, 19 Oct 2018 15:19:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 268606E464; Fri, 19 Oct 2018 15:19:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C77006E464 for ; Fri, 19 Oct 2018 15:19:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Oct 2018 08:19:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,400,1534834800"; d="scan'208";a="93369745" Received: from szara.igk.intel.com ([172.28.178.192]) by orsmga003.jf.intel.com with ESMTP; 19 Oct 2018 08:19:29 -0700 From: Tomasz Lis To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Oct 2018 17:19:28 +0200 Message-Id: <1539962368-5451-1-git-send-email-tomasz.lis@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH v1] drm/i915/icl: Define MOCS table for Icelake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mika Kuoppala MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The table has been unified across OSes to minimize virtualization overhead. The MOCS table is now versioned; the patch includes version 1 entries. BSpec: 34007 BSpec: 560 Signed-off-by: Tomasz Lis Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Mika Kuoppala Cc: Zhenyu Wang --- drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++- 1 file changed, 244 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 77e9871..b76d6db 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -44,6 +44,8 @@ struct drm_i915_mocs_table { #define LE_SCC(value) ((value) << 8) #define LE_PFM(value) ((value) << 11) #define LE_SCF(value) ((value) << 14) +#define LE_CoS(value) ((value) << 15) +#define LE_SSE(value) ((value) << 17) /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) ((value) << 0) @@ -96,6 +98,243 @@ struct drm_i915_mocs_table { * may only be updated incrementally by adding entries at the * end. */ +static const struct drm_i915_mocs_entry icelake_mocs_table[] = { + [0] = { + /* Base - Uncached (Deprecated) */ + .control_value = LE_CACHEABILITY(LE_UC) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [1] = { + /* Base - L3 + LeCC:PAT (Deprecated) */ + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [2] = { + /* Base - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [3] = { + /* Base - Uncached */ + .control_value = LE_CACHEABILITY(LE_UC) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [4] = { + /* Base - L3 */ + .control_value = LE_CACHEABILITY(LE_UC) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [5] = { + /* Base - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [6] = { + /* Age 0 - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [7] = { + /* Age 0 - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [8] = { + /* Age: Don't Chg. - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [9] = { + /* Age: Don't Chg. - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [10] = { + /* No AOM - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [11] = { + /* No AOM - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [12] = { + /* No AOM; Age 0 - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [13] = { + /* No AOM; Age 0 - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [14] = { + /* No AOM; Age:DC - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [15] = { + /* No AOM; Age:DC - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [16] = { + /* Reserved - For future use */ + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | + LE_TGT_CACHE(LE_TC_PAGETABLE) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT), + }, + [17] = { + /* Reserved - For future use */ + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | + LE_TGT_CACHE(LE_TC_PAGETABLE) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT), + }, + [18] = { + /* Self-Snoop - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [19] = { + /* Skip Caching - L3 + LLC(12.5%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [20] = { + /* Skip Caching - L3 + LLC(25%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [21] = { + /* Skip Caching - L3 + LLC(50%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [22] = { + /* Skip Caching - L3 + LLC(75%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [23] = { + /* Skip Caching - L3 + LLC(87.5%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [62] = { + /* HW Reserved - SW program but never use */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [63] = { + /* HW Reserved - SW program but never use */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, +}; + static const struct drm_i915_mocs_entry skylake_mocs_table[] = { [I915_MOCS_UNCACHED] = { /* 0x00000009 */ @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, { bool result = false; - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || - IS_ICELAKE(dev_priv)) { + if (IS_ICELAKE(dev_priv)) { + table->size = ARRAY_SIZE(icelake_mocs_table); + table->table = icelake_mocs_table; + result = true; + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true;