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spf=none smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan To: Will Deacon , Catalin Marinas , Marc Zyngier , Andre Przywara , Mark Rutland , Suzuki K Poulose , Stephen Boyd Subject: [PATCH] arm64: Add KRYO4XX gold CPU core to spectre-v2 safe list Date: Thu, 13 Aug 2020 13:48:34 +0530 Message-Id: <20200813081834.13576-1-saiprakash.ranjan@codeaurora.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200813_041848_726151_E7104620 X-CRM114-Status: GOOD ( 17.59 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [69.72.43.7 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [69.72.43.7 listed in wl.mailspike.net] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan , Douglas Anderson , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org KRYO4XX gold/big CPU cores are based on Cortex-A76 which has CSV2 bits set and are spectre-v2 safe. But on big.LITTLE systems where they are coupled with other CPU cores such as the KRYO4XX silver based on Cortex-A55 which are spectre-v2 safe but do not have CSV2 bits set, the system wide safe value will be set to the lowest value of CSV2 bits as per FTR_LOWER_SAFE defined for CSV2 bits of register ID_AA64PFR0_EL1. This is a problem when booting a guest kernel on gold CPU cores where it will incorrectly report ARM_SMCCC_ARCH_WORKAROUND_1 warning and consider them as vulnerable for Spectre variant 2 due to system wide safe value which is used in kvm emulation code when reading id registers. One wrong way of fixing this is to set the FTR_HIGHER_SAFE for CSV2 bits, so instead add the KRYO4XX gold CPU core to the safe list which will be consulted even when the sanitised read reports that CSV2 bits are not set for KRYO4XX gold cores. Reported-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- arch/arm64/kernel/cpu_errata.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 6bd1d3ad037a..6cbdd2d98a2a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -545,6 +545,7 @@ static const struct midr_range spectre_v2_safe_list[] = { MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD), { /* sentinel */ } };