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Fri, 14 Aug 2020 19:15:01 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: Yazen Ghannam , linux-kernel@vger.kernel.org, bp@suse.de, tony.luck@intel.com, x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com Subject: [PATCH 1/2] x86/MCE/AMD, EDAC/mce_amd: Use AMD NodeId for Family17h+ DRAM Decode Date: Fri, 14 Aug 2020 19:14:48 +0000 Message-Id: <20200814191449.183998-2-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200814191449.183998-1-Yazen.Ghannam@amd.com> References: <20200814191449.183998-1-Yazen.Ghannam@amd.com> X-ClientProxiedBy: SN1PR12CA0087.namprd12.prod.outlook.com (2603:10b6:802:21::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.78.2) by SN1PR12CA0087.namprd12.prod.outlook.com (2603:10b6:802:21::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3283.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: HJsOUluZy6nJQHlb05UiOgzpFrjGVLNRJ9l8kAfGWQuIjCtS9S2mFwP88EDuemxZGXH10qhiZ2WlDyTr6h+tS3ApmI81UgyTHZUZ+SZ28L+L5q3XhAiTfLR6liMxB/6noF4AsBL7CbGo5tzhOHzGzzDfcbI4Z7mcRrnfrEO51W9/DGW8WnU8h2z9shZBN0GGV1vgMpChH4ljkixKU/zuBU2XSRHEoTr13JPnCm4wZTNvNbiErqVEaXvBe3OmHUmc81oUexLSyRFapl0Ux503G78HLGlLk+g/6pthBTM0wrRLQVjcen0QqNpOsBl5f9aGv7K03gvKrZ8l5P1eEaW/49A+kVERmza4xpOcj/J8bItkmFJSUWPjqR/qmYI1dT4b27srp5ijbOoGlNQzCsctQ0itB36tju+wGy3Gbg/X2Ih0c6sLe5x+OC5UJihByfg7AkTIUi1+OFqqucfdOuX1SIV4qJ4Cm6+5N30iP7XphgfCWuTVz9/ZmyJkusyetwfbB8ehMYQeMvGvK6qWMSu918iJn/kf+arX7eoE/n+GX7R00CMa9PZOuQ6rl28vKLUwyv5w4tWRp0LcgtOeKMsUTpxEb/+wMrBPDB36c44GR/3LGIDcZE8PiVGC+iQpNtq7w+wxe9eLCsMjxCZ9PXKCeA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f8170d77-cb51-405d-ecf2-08d840865772 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2020 19:15:01.8215 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dye6mU9tkvqVKwB12HkGbvv8wovxYvxh3LARCSdTcejJ4fKFzHWwRiLBebzCz3MsNW6GD4rgXX3vO3fTtpDFdg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1700 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Yazen Ghannam The edac_mce_amd module calls decode_dram_ecc() on AMD Family17h and later systems. This function is used in amd64_edac_mod to do system-specific decoding for DRAM ECC errors. The function takes a "NodeId" as a parameter. In AMD documentation, NodeId is used to identify a physical die in a system. This can be used to identify a node in the AMD_NB code and also it is used with umc_normaddr_to_sysaddr(). However, the input used for decode_dram_ecc() is currently the NUMA node of a logical CPU. In the default configuration, the NUMA node and physical die will be equivalent, so this doesn't have an impact. But the NUMA node configuration can be adjusted with optional memory interleaving schemes. This will cause the NUMA node enumeration to not match the physical die enumeration. The mismatch will cause the address translation function to fail or report incorrect results. Save the "NodeId" as a percpu value during init in AMD MCE code. Export a function to return the value which can be used from modules like edac_mce_amd. Fixes: fbe63acf62f5 ("EDAC, mce_amd: Use cpu_to_node() to find the node ID") Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/amd.c | 11 +++++++++++ drivers/edac/mce_amd.c | 2 +- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index cf503824529c..92527cc9ed06 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -343,6 +343,8 @@ extern struct smca_bank smca_banks[MAX_NR_BANKS]; extern const char *smca_get_long_name(enum smca_bank_types t); extern bool amd_mce_is_memory_error(struct mce *m); +extern u8 amd_cpu_to_node(unsigned int cpu); + extern int mce_threshold_create_device(unsigned int cpu); extern int mce_threshold_remove_device(unsigned int cpu); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 99be063fcb1b..524edf81e287 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -202,6 +202,9 @@ static DEFINE_PER_CPU(unsigned int, bank_map); /* Map of banks that have more than MCA_MISC0 available. */ static DEFINE_PER_CPU(u32, smca_misc_banks_map); +/* CPUID_Fn8000001E_ECX[NodeId] used to identify a physical node/die. */ +static DEFINE_PER_CPU(u8, node_id); + static void amd_threshold_interrupt(void); static void amd_deferred_error_interrupt(void); @@ -233,6 +236,12 @@ static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) } +u8 amd_cpu_to_node(unsigned int cpu) +{ + return per_cpu(node_id, cpu); +} +EXPORT_SYMBOL_GPL(amd_cpu_to_node); + static void smca_configure(unsigned int bank, unsigned int cpu) { unsigned int i, hwid_mcatype; @@ -240,6 +249,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) u32 high, low; u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); + this_cpu_write(node_id, cpuid_ecx(0x8000001e) & 0xFF); + /* Set appropriate bits in MCA_CONFIG */ if (!rdmsr_safe(smca_config, &low, &high)) { /* diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 325aedf46ff2..9476097d0fdb 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -996,7 +996,7 @@ static void decode_smca_error(struct mce *m) } if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc) - decode_dram_ecc(cpu_to_node(m->extcpu), m); + decode_dram_ecc(amd_cpu_to_node(m->extcpu), m); } static inline void amd_decode_err_code(u16 ec) From patchwork Fri Aug 14 19:14:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 11715165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33B7914E3 for ; Fri, 14 Aug 2020 19:15:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B3A02078D for ; Fri, 14 Aug 2020 19:15:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="ml+HPTtv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728029AbgHNTPS (ORCPT ); Fri, 14 Aug 2020 15:15:18 -0400 Received: from mail-bn8nam11on2081.outbound.protection.outlook.com ([40.107.236.81]:57313 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726652AbgHNTPR (ORCPT ); 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Fri, 14 Aug 2020 19:15:04 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: Yazen Ghannam , linux-kernel@vger.kernel.org, bp@suse.de, tony.luck@intel.com, x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com Subject: [PATCH 2/2] x86/MCE/AMD Support new memory interleaving schemes during address translation Date: Fri, 14 Aug 2020 19:14:49 +0000 Message-Id: <20200814191449.183998-3-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200814191449.183998-1-Yazen.Ghannam@amd.com> References: <20200814191449.183998-1-Yazen.Ghannam@amd.com> X-ClientProxiedBy: SN1PR12CA0087.namprd12.prod.outlook.com (2603:10b6:802:21::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.78.2) by SN1PR12CA0087.namprd12.prod.outlook.com (2603:10b6:802:21::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3283.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: qvyYz7LmM6quSZwmgpiTJRKXXdb0nN046maHt35CFjnM/ek2+dBeL4aMr2Pc+YXeib+3B/kPJylJJIAkdQRd/4sRyY8CQYdRfwCAn7CcqsJAoUfA0VNL6dHVEX+jDgyBdqPwWfV0KMqQHRvKxzbFbnzgE7MIGMIety7fj93pShHk382s7xZL3tF8GjFRvvIdqYgOoeIGURvpt9hmzNtivOIBZI5hxutcdi6x6CEwK2+/oFdwyrUZMGTjjHos9Fq9B7feo7lzXKK//T1pb0qcLYasPQ1iMPFdRS0FDu9Ql5ITTgafFFtrLSIsyLjaM06M8fRfcI3/tYLpaf02UJTHqIJn4EE2wcGhGGHXd2lLab+tARuADfmVzKaJwi5cjc5MwLkh8w+DeCrEyhwdxD++/azScO83RFZkiVtSyZiaIUyKbe+f651wGuDUb4G1WiAMIPonQol7uTXisjVO+c3sDKUCus1Jjhj85173Gf+2P+MBeWiL0yhONX+m8PL+m70TqfGs/9vXqF8xaUJIdROy/DmNHBa/UwcHOi1GN1+LR9i1tlsBycShbraMZXGC488UYraAJQc58RAva+EYekJRoOBz93w0iwOvmxMhkzrDnmnLZk4yoQlYbSxMimkycV/MW7Wr0XA8BNzItQ1VeZpPcg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1a046cc1-1bce-4274-3160-08d8408658ee X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2020 19:15:04.4420 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jAs5WfpWIGMFK/NolHSPaGetRAPDockHXqwFFWIWEUg6V9rzTsmOG8/LL/oYmiGn+knSwnYyFEWJCAHxgIq3Ew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1700 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add support for new memory interleaving schemes used in current AMD systems. Check if the system is using a current Data Fabric version or a legacy version as some bit and register definitions have changed. Tested on AMD reference platforms with the following memory interleaving options. Naples - None - Channel - Die - Socket Rome (NPS = Nodes per Socket) - None - NPS0 - NPS1 - NPS2 - NPS4 The fixes tag refers to the commit that allows amd64_edac_mod to load on Rome systems. The module may report an incorrect system address on Rome systems depending on the interleaving option used. Fixes: 6e846239e548 ("EDAC/amd64: Add Family 17h Model 30h PCI IDs") Signed-off-by: Muralidhara M K Co-developed-by: Naveen Krishna Chtradhi Signed-off-by: Naveen Krishna Chtradhi Co-developed-by: Yazen Ghannam Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 237 +++++++++++++++++++++++++++------- 1 file changed, 188 insertions(+), 49 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 524edf81e287..a687aa898fef 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -689,18 +689,25 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; + /* We start from the normalized address */ u64 ret_addr = norm_addr; u32 tmp; - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + bool hash_enabled = false, split_normalized = false, legacy_df = false; + u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; + u8 intlv_addr_sel, intlv_addr_bit, num_intlv_bits; + u8 cs_mask, cs_id = 0, dst_fabric_id = 0; u8 lgcy_mmio_hole_en, base = 0; - u8 cs_mask, cs_id = 0; - bool hash_enabled = false; + + /* Read D18F1x208 (System Fabric ID Mask 0). */ + if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + goto out_err; + + /* Determine if system is a legacy Data Fabric type. */ + legacy_df = !(tmp & 0xFF); /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) @@ -708,7 +715,12 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) /* Remove HiAddrOffset from normalized address, if enabled: */ if (tmp & BIT(0)) { - u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; + u8 hi_addr_offset_lsb = legacy_df ? 20 : 12; + u64 hi_addr_offset = tmp & GENMASK_ULL(31, hi_addr_offset_lsb); + + /* Align to bit 28 regardless of the LSB used. */ + hi_addr_offset >>= hi_addr_offset_lsb; + hi_addr_offset <<= 28; if (norm_addr >= hi_addr_offset) { ret_addr -= hi_addr_offset; @@ -728,23 +740,31 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) } lgcy_mmio_hole_en = tmp & BIT(1); - intlv_num_chan = (tmp >> 4) & 0xF; - intlv_addr_sel = (tmp >> 8) & 0x7; - dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { - pr_err("%s: Invalid interleave address select %d.\n", - __func__, intlv_addr_sel); - goto out_err; + if (legacy_df) { + intlv_num_chan = (tmp >> 4) & 0xF; + intlv_addr_sel = (tmp >> 8) & 0x7; + } else { + intlv_num_chan = (tmp >> 2) & 0xF; + intlv_num_dies = (tmp >> 6) & 0x3; + intlv_num_sockets = (tmp >> 8) & 0x1; + intlv_addr_sel = (tmp >> 9) & 0x7; } + dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; + /* Read D18F0x114 (DramLimitAddress). */ if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) goto out_err; - intlv_num_sockets = (tmp >> 8) & 0x1; - intlv_num_dies = (tmp >> 10) & 0x3; + if (legacy_df) { + intlv_num_sockets = (tmp >> 8) & 0x1; + intlv_num_dies = (tmp >> 10) & 0x3; + dst_fabric_id = tmp & 0xFF; + } else { + dst_fabric_id = tmp & 0x3FF; + } + dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); intlv_addr_bit = intlv_addr_sel + 8; @@ -757,8 +777,27 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) case 5: intlv_num_chan = 3; break; case 7: intlv_num_chan = 4; break; - case 8: intlv_num_chan = 1; + case 8: + if (legacy_df) { + intlv_num_chan = 1; + hash_enabled = true; + } else { + intlv_num_chan = 5; + } + break; + case 12: + intlv_num_chan = 1; + hash_enabled = true; + break; + case 13: + intlv_num_chan = 2; + hash_enabled = true; + split_normalized = true; + break; + case 14: + intlv_num_chan = 3; hash_enabled = true; + split_normalized = true; break; default: pr_err("%s: Invalid number of interleaved channels %d.\n", @@ -766,18 +805,14 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) goto out_err; } - num_intlv_bits = intlv_num_chan; - - if (intlv_num_dies > 2) { - pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", - __func__, intlv_num_dies); + /* Assert interleave address bit is 8 or 9 for hashing cases. */ + if (hash_enabled && intlv_addr_bit != 8 && intlv_addr_bit != 9) { + pr_err("%s: Invalid interleave address bit for hashing %d.\n", + __func__, intlv_addr_bit); goto out_err; } - num_intlv_bits += intlv_num_dies; - - /* Add a bit if sockets are interleaved. */ - num_intlv_bits += intlv_num_sockets; + num_intlv_bits = intlv_num_chan + intlv_num_dies + intlv_num_sockets; /* Assert num_intlv_bits <= 4 */ if (num_intlv_bits > 4) { @@ -787,8 +822,10 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) } if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; + u8 cs_fabric_id_mask = legacy_df ? 0xFF : 0x3F; u8 die_id_bit, sock_id_bit, cs_fabric_id; + u64 addr_x, addr_y, addr_z; + u8 node_id_shift = 0; /* * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. @@ -799,7 +836,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) goto out_err; - cs_fabric_id = (tmp >> 8) & 0xFF; + cs_fabric_id = (tmp >> 8) & cs_fabric_id_mask; die_id_bit = 0; /* If interleaved over more than 1 channel: */ @@ -807,44 +844,94 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) die_id_bit = intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; cs_id = cs_fabric_id & cs_mask; + cs_id -= dst_fabric_id & cs_mask; } sock_id_bit = die_id_bit; - /* Read D18F1x208 (SystemFabricIdMask). */ - if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + if (intlv_num_dies || intlv_num_sockets) { + u16 offset = 0; + + if (legacy_df) { + /* Read D18F1x208 (SystemFabricIdMask). */ + offset = 0x208; + } else { + /* Read D18F1x20C (SystemFabricIdMask1). */ + offset = 0x20C; + } + + if (amd_df_indirect_read(nid, 1, offset, umc, &tmp)) goto out_err; + if (!legacy_df) + node_id_shift = tmp & 0xF; + } + /* If interleaved over more than 1 die. */ if (intlv_num_dies) { + u8 die_id_shift, die_id_mask; + sock_id_bit = die_id_bit + intlv_num_dies; - die_id_shift = (tmp >> 24) & 0xF; - die_id_mask = (tmp >> 8) & 0xFF; + + if (legacy_df) { + die_id_shift = (tmp >> 24) & 0xF; + die_id_mask = (tmp >> 8) & 0xFF; + } else { + die_id_shift = (tmp & 0xF) + node_id_shift; + + die_id_mask = (tmp >> 16) & 0x7; + die_id_mask <<= node_id_shift; + } cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ if (intlv_num_sockets) { - socket_id_shift = (tmp >> 28) & 0xF; - socket_id_mask = (tmp >> 16) & 0xFF; + u8 socket_id_shift, socket_id_mask; + + if (legacy_df) { + socket_id_shift = (tmp >> 28) & 0xF; + socket_id_mask = (tmp >> 16) & 0xFF; + } else { + socket_id_shift = (tmp >> 8) & 0x3; + socket_id_shift += node_id_shift; + + socket_id_mask = (tmp >> 24) & 0x7; + socket_id_mask <<= node_id_shift; + } cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; } /* * The pre-interleaved address consists of XXXXXXIIIYYYYY - * where III is the ID for this CS, and XXXXXXYYYYY are the - * address bits from the post-interleaved address. - * "num_intlv_bits" has been calculated to tell us how many "I" - * bits there are. "intlv_addr_bit" tells us how many "Y" bits - * there are (where "I" starts). + * or XXXXXXIIZZZIYYY where III is the ID for this CS, and + * XXXXXXZZZYYYYY are the address bits from the post-interleaved + * address. "num_intlv_bits" has been calculated to tell us how + * many "I" bits there are. "intlv_addr_bit" tells us how many + * "Y" bits there are (where "I" starts). + * + * The "split" III is only used in the COD modes, where there + * is one bit I at "intlv_addr_bit", and the remaining CS bits + * are higher up starting at bit 12. */ - temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); + + if (split_normalized) { + addr_x = ret_addr & GENMASK_ULL(63, 11); + addr_x <<= num_intlv_bits; + + addr_z = ret_addr & GENMASK_ULL(10, intlv_addr_bit); + addr_z <<= 1; + } else { + addr_x = ret_addr & GENMASK_ULL(63, intlv_addr_bit); + addr_x <<= num_intlv_bits; + + addr_z = 0; + } + + ret_addr = addr_x | addr_z | addr_y; } /* Add dram base address */ @@ -860,18 +947,70 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) ret_addr += (BIT_ULL(32) - dram_hole_base); } - if (hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ret_addr >> 12) ^ + /* + * There are three cases for hashing: + * 1) No Hashing + * 2) Legacy Hashing + * 3) Cluster-on-Die (COD) Hashing + */ + if (!hash_enabled) { + /* Fill in the interleave bit. */ + if (intlv_num_chan) + ret_addr |= (cs_id << intlv_addr_bit); + } else if (legacy_df) { + /* Legacy 2ch hash. */ + u8 hashed_bit = (ret_addr >> 12) ^ (ret_addr >> 18) ^ (ret_addr >> 21) ^ (ret_addr >> 30) ^ cs_id; hashed_bit &= BIT(0); + ret_addr ^= hashed_bit << intlv_addr_bit; + } else { + u8 hashed_bit, hash_ctl_64K, hash_ctl_2M, hash_ctl_1G; + + /* Read D18F0x3F8 (DfGlobalCtrl)). */ + if (amd_df_indirect_read(nid, 0, 0x3F8, umc, &tmp)) + goto out_err; + + hash_ctl_64K = !!(tmp & BIT(20)); + hash_ctl_2M = !!(tmp & BIT(21)); + hash_ctl_1G = !!(tmp & BIT(22)); + + /* COD with 2ch, 4ch, or 8ch hash. */ + hashed_bit = (ret_addr >> 14) ^ + ((ret_addr >> 18) & hash_ctl_64K) ^ + ((ret_addr >> 23) & hash_ctl_2M) ^ + ((ret_addr >> 32) & hash_ctl_1G) ^ + cs_id; + + hashed_bit &= BIT(0); + ret_addr ^= hashed_bit << intlv_addr_bit; + + /* COD with 4ch or 8ch hash. */ + if ((intlv_num_chan == 2) || (intlv_num_chan == 3)) { + hashed_bit = (ret_addr >> 12) ^ + ((ret_addr >> 16) & hash_ctl_64K) ^ + ((ret_addr >> 21) & hash_ctl_2M) ^ + ((ret_addr >> 30) & hash_ctl_1G) ^ + (cs_id >> 1); + + hashed_bit &= BIT(0); + ret_addr ^= hashed_bit << 12; + } + + /* COD with 8ch hash. */ + if (intlv_num_chan == 3) { + hashed_bit = (ret_addr >> 13) ^ + ((ret_addr >> 17) & hash_ctl_64K) ^ + ((ret_addr >> 22) & hash_ctl_2M) ^ + ((ret_addr >> 31) & hash_ctl_1G) ^ + (cs_id >> 2); - if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) - ret_addr ^= BIT(intlv_addr_bit); + hashed_bit &= BIT(0); + ret_addr ^= hashed_bit << 13; + } } /* Is calculated system address is above DRAM limit address? */