From patchwork Mon Aug 17 03:46:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D461739 for ; Mon, 17 Aug 2020 03:48:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60A9520826 for ; Mon, 17 Aug 2020 03:48:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="ZozkZjop" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727043AbgHQDr7 (ORCPT ); Sun, 16 Aug 2020 23:47:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgHQDr5 (ORCPT ); Sun, 16 Aug 2020 23:47:57 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC65CC061388 for ; Sun, 16 Aug 2020 20:47:57 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 25FAA1FEF5; Mon, 17 Aug 2020 03:47:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636076; bh=akb+og0HnO3wboY8Fq8f9zbqdX3Uoz+REcSJDdeCfZI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZozkZjopFHz84hwKNShWN4hgcNl9ecwl+KkYe0OnQNX1Kf0Q+K2KcFp7BOk+T8yvQ K9fg8Sxnc6uhT4IedQyJc+DKDODsvAQA5C2/K/gMKXz0aYfQ7I82+nWl7VED/EFfE1 EhDoldaLtmmcOd87ZTxyWWRvGvVT0B7rfFv9pDs8wFIKNRWN60d6+owsr3HkYdO0jC akEG5f/6xyvBCX3d+j+VO+qWTLqGIoUg0Ko2xMminrNt4rE4hPvgMz4ic7QDSQDSb8 tF9dd1Qy0C/LrAiIG2EiALP1/QlK7Dvr56E27V1bNfeMJK/gYIWAE5JmT4lfzZZ2aF rT9UJ7CU9rWOw== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Paul Burton , Serge Semin , WANG Xuerui , =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , Ingo Molnar , Peter Xu , "Peter Zijlstra (Intel)" , Sergey Korolev , Alexey Malahov , Marc Zyngier , Anup Patel , Palmer Dabbelt , Atish Patra , Michael Kelley , Steven Price , Daniel Jordan , Ming Lei , Ulf Hansson , Mike Leach , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 1/7] MIPS: sync-r4k: Rework to be many cores firendly Date: Mon, 17 Aug 2020 11:46:40 +0800 Message-Id: <20200817034701.3515721-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The original sync-r4k did a good job on reducing jitter by determine the "next time value", but it has a limitation that when we have lots of cores, the timewrap on CPU0 will become unaccpetable. That will also happen when CPU Hotplug is enabled and the counter needs to be synchronised at every plug event. Here we reworked the whole procdure. Now the synchronise event on CPU0 is triggered by smp call function, and we won't touch the count on CPU0 at all. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/r4k-timer.h | 5 -- arch/mips/kernel/smp.c | 2 - arch/mips/kernel/sync-r4k.c | 143 +++++++++++++----------------- 3 files changed, 61 insertions(+), 89 deletions(-) diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h index afe9e0e03fe9..2789d2fc5e23 100644 --- a/arch/mips/include/asm/r4k-timer.h +++ b/arch/mips/include/asm/r4k-timer.h @@ -12,15 +12,10 @@ #ifdef CONFIG_SYNC_R4K -extern void synchronise_count_master(int cpu); extern void synchronise_count_slave(int cpu); #else -static inline void synchronise_count_master(int cpu) -{ -} - static inline void synchronise_count_slave(int cpu) { } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 48d84d5fcc36..ead9ac883241 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -444,8 +444,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) return -EIO; } - synchronise_count_master(cpu); - /* Wait for CPU to finish startup & mark itself online before return */ wait_for_completion(&cpu_running); return 0; diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index abdd7aaa3311..c3e36d6d57fa 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/arch/mips/kernel/sync-r4k.c @@ -1,122 +1,101 @@ // SPDX-License-Identifier: GPL-2.0 /* * Count register synchronisation. - * - * All CPUs will have their count registers synchronised to the CPU0 next time - * value. This can cause a small timewarp for CPU0. All other CPU's should - * not have done anything significant (but they may have had interrupts - * enabled briefly - prom_smp_finish() should not be responsible for enabling - * interrupts...) */ #include #include #include +#include +#include #include #include #include #include -static unsigned int initcount = 0; -static atomic_t count_count_start = ATOMIC_INIT(0); -static atomic_t count_count_stop = ATOMIC_INIT(0); +#define STAGE_START 0 +#define STAGE_MASTER_READY 1 +#define STAGE_SLAVE_SYNCED 2 -#define COUNTON 100 -#define NR_LOOPS 3 +static unsigned int cur_count; +static unsigned int fini_count; +static atomic_t sync_stage = ATOMIC_INIT(0); +static DEFINE_RAW_SPINLOCK(sync_r4k_lock); -void synchronise_count_master(int cpu) +#define MAX_LOOPS 1000 + +void synchronise_count_master(void *unused) { - int i; unsigned long flags; + long delta; + int i; - pr_info("Synchronize counters for CPU %u: ", cpu); + if (atomic_read(&sync_stage) != STAGE_START) + BUG(); local_irq_save(flags); - /* - * We loop a few times to get a primed instruction cache, - * then the last pass is more or less synchronised and - * the master and slaves each set their cycle counters to a known - * value all at once. This reduces the chance of having random offsets - * between the processors, and guarantees that the maximum - * delay between the cycle counters is never bigger than - * the latency of information-passing (cachelines) between - * two CPUs. - */ - - for (i = 0; i < NR_LOOPS; i++) { - /* slaves loop on '!= 2' */ - while (atomic_read(&count_count_start) != 1) - mb(); - atomic_set(&count_count_stop, 0); - smp_wmb(); + cur_count = read_c0_count(); + smp_wmb(); + atomic_inc(&sync_stage); /* inc to STAGE_MASTER_READY */ - /* Let the slave writes its count register */ - atomic_inc(&count_count_start); - - /* Count will be initialised to current timer */ - if (i == 1) - initcount = read_c0_count(); - - /* - * Everyone initialises count in the last loop: - */ - if (i == NR_LOOPS-1) - write_c0_count(initcount); - - /* - * Wait for slave to leave the synchronization point: - */ - while (atomic_read(&count_count_stop) != 1) - mb(); - atomic_set(&count_count_start, 0); + for (i = 0; i < MAX_LOOPS; i++) { + cur_count = read_c0_count(); smp_wmb(); - atomic_inc(&count_count_stop); + if (atomic_read(&sync_stage) == STAGE_SLAVE_SYNCED) + break; } - /* Arrange for an interrupt in a short while */ - write_c0_compare(read_c0_count() + COUNTON); + + delta = read_c0_count() - fini_count; local_irq_restore(flags); - /* - * i386 code reported the skew here, but the - * count registers were almost certainly out of sync - * so no point in alarming people - */ - pr_cont("done.\n"); + if (i == MAX_LOOPS) + pr_err("sync-r4k: Master: synchronise timeout\n"); + else + pr_info("sync-r4k: Master: synchronise succeed, maximum delta: %ld\n", delta); + + return; } void synchronise_count_slave(int cpu) { int i; unsigned long flags; + call_single_data_t csd; - local_irq_save(flags); + raw_spin_lock(&sync_r4k_lock); - /* - * Not every cpu is online at the time this gets called, - * so we first wait for the master to say everyone is ready - */ - - for (i = 0; i < NR_LOOPS; i++) { - atomic_inc(&count_count_start); - while (atomic_read(&count_count_start) != 2) - mb(); - - /* - * Everyone initialises count in the last loop: - */ - if (i == NR_LOOPS-1) - write_c0_count(initcount); - - atomic_inc(&count_count_stop); - while (atomic_read(&count_count_stop) != 2) - mb(); + /* Let variables get attention from cache */ + for (i = 0; i < MAX_LOOPS; i++) { + cur_count++; + fini_count += cur_count; + cur_count += fini_count; } - /* Arrange for an interrupt in a short while */ - write_c0_compare(read_c0_count() + COUNTON); + + atomic_set(&sync_stage, STAGE_START); + csd.func = synchronise_count_master; + + /* Master count is always CPU0 */ + if (smp_call_function_single_async(0, &csd)) { + pr_err("sync-r4k: Salve: Failed to call master\n"); + raw_spin_unlock(&sync_r4k_lock); + return; + } + + local_irq_save(flags); + + /* Wait until master ready */ + while (atomic_read(&sync_stage) != STAGE_MASTER_READY) + cpu_relax(); + + write_c0_count(cur_count); + fini_count = read_c0_count(); + smp_wmb(); + atomic_inc(&sync_stage); /* inc to STAGE_SLAVE_SYNCED */ local_irq_restore(flags); + + raw_spin_unlock(&sync_r4k_lock); } -#undef NR_LOOPS From patchwork Mon Aug 17 03:46:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716407 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF5B5739 for ; Mon, 17 Aug 2020 03:48:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A27312072E for ; Mon, 17 Aug 2020 03:48:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="GbCs5Tlb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727079AbgHQDsV (ORCPT ); Sun, 16 Aug 2020 23:48:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726985AbgHQDsR (ORCPT ); Sun, 16 Aug 2020 23:48:17 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86386C061388; Sun, 16 Aug 2020 20:48:17 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id CB6E61FEF9; Mon, 17 Aug 2020 03:48:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636097; bh=yi1R8x6RvUJ7bAaN1Z7AIjYeqPaOFINIjV7gUgOK68Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GbCs5Tlb08GvjOFM543qU04ygjuZ0+K1IyKewuWhseB8YmJE6zqpl91ti35v4H4ag imh19YYj4zOK1W1VLcFQuvr4shSHzw43CrlsCjNQ/wqP8NDSeavtu8GvRHXM299cfK JrzWm3J09JaOP6ZxKFjEragV7fNkGQCcB412HNYyPlqT+dOUMf82HVhTEnOtAxIxGm +I5zhrRvfvwkpIlN+zBvg34Ru3cTauT3igDB0rS+Rq7NReqShBg3pLDae6jX1HS2Ms Bt33FJcKNwo6GtRRJcYkqTtHvoINzIgGKBxQVeSE0TpXQ97Ok1tMZ+krV/5LTx7Ndy 1ggGCemaKTdsQ== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Serge Semin , Paul Burton , WANG Xuerui , =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , Peter Xu , Ingo Molnar , "Peter Zijlstra (Intel)" , Sergey Korolev , Alexey Malahov , Anup Patel , Marc Zyngier , Michael Kelley , Greg Kroah-Hartman , Daniel Wagner , Mike Leach , Atish Patra , Ming Lei , Steven Price , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 2/7] MIPS: time: Use CPUHUP to handle r4k timer Date: Mon, 17 Aug 2020 11:46:41 +0800 Message-Id: <20200817034701.3515721-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org There is no need to hijack initialization procudre to take care of r4k timer we have CPUHP framework to deal with the CPU plug sequence. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/time.h | 28 +++++++++++++++------------- arch/mips/kernel/cevt-r4k.c | 30 ++++++++++++++++++++++-------- arch/mips/kernel/smp.c | 3 --- arch/mips/kernel/time.c | 22 ++++++++++++++++++++-- include/linux/cpuhotplug.h | 1 + 5 files changed, 58 insertions(+), 26 deletions(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index e855a3611d92..d00a5b05a420 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -39,30 +39,32 @@ extern int __weak get_c0_perfcount_int(void); * Initialize the calling CPU's compare interrupt as clockevent device */ extern unsigned int get_c0_compare_int(void); -extern int r4k_clockevent_init(void); -static inline int mips_clockevent_init(void) -{ #ifdef CONFIG_CEVT_R4K - return r4k_clockevent_init(); +extern int r4k_clockevent_init(void); +extern int r4k_clockevent_percpu_init(int cpu); #else - return -ENXIO; -#endif +static inline int r4k_clockevent_init(void) +{ + return -ENODEV; +} +static inline int r4k_clockevent_percpu_init(int cpu) +{ + return -ENODEV; } +#endif /* * Initialize the count register as a clocksource */ -extern int init_r4k_clocksource(void); - -static inline int init_mips_clocksource(void) -{ #ifdef CONFIG_CSRC_R4K - return init_r4k_clocksource(); +extern int init_r4k_clocksource(void); #else - return 0; -#endif +static inline int init_r4k_clocksource(void) +{ + return -ENODEV; } +#endif static inline void clockevent_set_clock(struct clock_event_device *cd, unsigned int clock) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 995ad9e69ded..f0c52d751d0a 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -294,10 +294,8 @@ core_initcall(r4k_register_cpufreq_notifier); #endif /* !CONFIG_CPU_FREQ */ -int r4k_clockevent_init(void) +int r4k_clockevent_percpu_init(int cpu) { - unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; - unsigned int cpu = smp_processor_id(); struct clock_event_device *cd; unsigned int irq, min_delta; @@ -307,11 +305,6 @@ int r4k_clockevent_init(void) if (!c0_compare_int_usable()) return -ENXIO; - /* - * With vectored interrupts things are getting platform specific. - * get_c0_compare_int is a hook to allow a platform to return the - * interrupt number of its liking. - */ irq = get_c0_compare_int(); cd = &per_cpu(mips_clockevent_device, cpu); @@ -331,9 +324,30 @@ int r4k_clockevent_init(void) clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff); + return 0; +} + +int r4k_clockevent_init(void) +{ + int ret; + unsigned int irq; + unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; + + ret = r4k_clockevent_percpu_init(0); + if (ret) + return ret; + + if (cp0_timer_irq_installed) return 0; + /* + * With vectored interrupts things are getting platform specific. + * get_c0_compare_int is a hook to allow a platform to return the + * interrupt number of its liking. + */ + irq = get_c0_compare_int(); + cp0_timer_irq_installed = 1; if (request_irq(irq, c0_compare_interrupt, flags, "timer", diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index ead9ac883241..0ca4f7cf6402 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -337,7 +337,6 @@ asmlinkage void start_secondary(void) cpu_probe(); per_cpu_trap_init(false); - mips_clockevent_init(); mp_ops->init_secondary(); cpu_report(); maar_init(); @@ -358,8 +357,6 @@ asmlinkage void start_secondary(void) /* Notify boot CPU that we're starting & ready to sync counters */ complete(&cpu_starting); - synchronise_count_slave(cpu); - /* The CPU is running and counters synchronised, now mark it online */ set_cpu_online(cpu, true); diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index caa01457dce6..9b16e60aaa30 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -8,6 +8,7 @@ */ #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #ifdef CONFIG_CPU_FREQ @@ -155,6 +157,16 @@ static __init int cpu_has_mfc0_count_bug(void) return 0; } +#if defined(CONFIG_CEVT_R4K) || defined(CONFIG_CSRC_R4K) +static int mips_r4k_timer_starting_cpu(unsigned int cpu) +{ + synchronise_count_slave(cpu); + r4k_clockevent_percpu_init(cpu); + + return 0; +} +#endif + void __init time_init(void) { plat_time_init(); @@ -167,6 +179,12 @@ void __init time_init(void) * timer interrupt isn't reliable; the interference doesn't * matter then, because we don't use the interrupt. */ - if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug()) - init_mips_clocksource(); + if (r4k_clockevent_init() != 0 || !cpu_has_mfc0_count_bug()) + init_r4k_clocksource(); + +#if defined(CONFIG_CEVT_R4K) || defined(CONFIG_CSRC_R4K) + cpuhp_setup_state_nocalls(CPUHP_AP_MIPS_R4K_TIMER_STARTING, + "clockevents/mips/r4k/timer:starting", + mips_r4k_timer_starting_cpu, NULL); +#endif } diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 191772d4a4d7..163288803cd4 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -129,6 +129,7 @@ enum cpuhp_state { CPUHP_AP_TEGRA_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, + CPUHP_AP_MIPS_R4K_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, CPUHP_AP_ARC_TIMER_STARTING, CPUHP_AP_RISCV_TIMER_STARTING, From patchwork Mon Aug 17 03:46:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7D1F739 for ; Mon, 17 Aug 2020 03:48:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0235214F1 for ; Mon, 17 Aug 2020 03:48:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="xj7xpPzD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727118AbgHQDsj (ORCPT ); Sun, 16 Aug 2020 23:48:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726385AbgHQDsi (ORCPT ); Sun, 16 Aug 2020 23:48:38 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1B4AC061388; Sun, 16 Aug 2020 20:48:37 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 1B33B1FEFE; Mon, 17 Aug 2020 03:48:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636117; bh=PFWiObevUs0vhYw4Mg5ewb9+RYTJ10CHEuPDj8cUb9c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xj7xpPzDm8qy25IFVABsByjJvvvFmneQRtrtAKsHX35ONBcOxwSQ0TxcLH0fgmpWS DrvfeB0G1ZhMBYEUIMqSh+/1ecjudXLyzx6J4a+KAUqoITD0xOYHKWtNyHEY3u0yk7 M89THOB3ubkXkkEAB7zVL6brMFTSl+2oy3cHqEVIB3d3LeGt9RQqLln0H8GsIauHFl YHMFTz+NUxLiMorUDY1LyHdRJt7NBPZNZ4747sRhpEeG6titAtmLvuukTH+kPKYtTE Akn1qCAHOI4H8TvVYh8xj3RBERDsMFzj8Ta4cOmdv54DpUUs/Lk+Az2CZoow4cj134 j8+jj/kJkqRZg== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Serge Semin , Paul Burton , WANG Xuerui , =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , Peter Xu , Ingo Molnar , Sergey Korolev , Alexey Malahov , Anup Patel , Marc Zyngier , Daniel Jordan , Michael Kelley , Palmer Dabbelt , Ulf Hansson , Steven Price , Atish Patra , Ming Lei , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 3/7] MIPS: Kconfig: Always select SYNC_R4K if both SMP and r4k timer is enabled Date: Mon, 17 Aug 2020 11:46:42 +0800 Message-Id: <20200817034701.3515721-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Now all platforms are sharing sync-r4k procdure, there is no need to let platform to select it. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 880680c0df31..7674f4379d39 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -234,7 +234,6 @@ config BMIPS_GENERIC select USE_OF select CEVT_R4K select CSRC_R4K - select SYNC_R4K select COMMON_CLK select BCM6345_L1_IRQ select BCM7038_L1_IRQ @@ -291,7 +290,6 @@ config BCM63XX select BOOT_RAW select CEVT_R4K select CSRC_R4K - select SYNC_R4K select DMA_NONCOHERENT select IRQ_MIPS_CPU select SYS_SUPPORTS_32BIT_KERNEL @@ -726,7 +724,6 @@ config SGI_IP30 select BOOT_ELF64 select CEVT_R4K select CSRC_R4K - select SYNC_R4K if SMP select ZONE_DMA32 select HAVE_PCI select IRQ_MIPS_CPU @@ -979,7 +976,6 @@ config NLM_XLR_BOARD select CSRC_R4K select IRQ_MIPS_CPU select ZONE_DMA32 if 64BIT - select SYNC_R4K select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_ZBOOT select SYS_SUPPORTS_ZBOOT_UART16550 @@ -1006,7 +1002,6 @@ config NLM_XLP_BOARD select CSRC_R4K select IRQ_MIPS_CPU select ZONE_DMA32 if 64BIT - select SYNC_R4K select SYS_HAS_EARLY_PRINTK select USE_OF select SYS_SUPPORTS_ZBOOT @@ -1076,6 +1071,7 @@ config CEVT_GT641XX bool config CEVT_R4K + select SYNC_R4K if SMP bool config CEVT_SB1250 @@ -1091,6 +1087,7 @@ config CSRC_IOASIC bool config CSRC_R4K + select SYNC_R4K if SMP select CLOCKSOURCE_WATCHDOG if CPU_FREQ bool @@ -2361,7 +2358,6 @@ config MIPS_MT_SMP depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI - select SYNC_R4K select MIPS_MT select SMP select SMP_UP @@ -2465,7 +2461,6 @@ config MIPS_CMP bool "MIPS CMP framework support (DEPRECATED)" depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6 select SMP - select SYNC_R4K select SYS_SUPPORTS_SMP select WEAK_ORDERING default n @@ -2483,7 +2478,6 @@ config MIPS_CPS select MIPS_CM select MIPS_CPS_PM if HOTPLUG_CPU select SMP - select SYNC_R4K if (CEVT_R4K || CSRC_R4K) select SYS_SUPPORTS_HOTPLUG_CPU select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6 select SYS_SUPPORTS_SMP From patchwork Mon Aug 17 03:46:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F7E013A4 for ; Mon, 17 Aug 2020 03:49:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77DBF2072E for ; Mon, 17 Aug 2020 03:49:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="k7y+m7oo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727792AbgHQDs7 (ORCPT ); Sun, 16 Aug 2020 23:48:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726729AbgHQDs6 (ORCPT ); Sun, 16 Aug 2020 23:48:58 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02382C061388; Sun, 16 Aug 2020 20:48:58 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 736DC1FF02; Mon, 17 Aug 2020 03:48:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636137; bh=DG4HaU9QQ7zmJ9disDopHNWXYPU0r4P16T3M3Oeh0v8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k7y+m7oobNcnyEw8zisBtP5mbOJfk/nHNionO299OhfazRxuu1Ik2h3aNwJc0Bjtr YC2DWMLXLRBqTZbz7U8lYyavuysFGo5mny+x/JaD9jIgpg7g12zWVVJEEiPa2RkGnL VZjeiI8j6CNaMDpspo/a2gLkFHXrj3vkRi702ZdnuOWfg9VC0VeLIkcs47lw8qERPD IdnxQZ3MLRoWhKzEh3MDNzEIC3bw6MMlsQuYQSKhm2EklZRF8lqNZQEA7tp/dBlKMO v3kPsV0ARo+o12jsFEKkG6SjKdbHoxW1YcLLc5kZJe2iaowOfvacCUFIc/Hu8sOmJE iEtXFe9m5XvvA== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Paul Burton , Serge Semin , WANG Xuerui , =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , Peter Xu , "Peter Zijlstra (Intel)" , Sergey Korolev , Alexey Malahov , Anup Patel , Marc Zyngier , "Rafael J. Wysocki" , Michael Kelley , Steven Price , Atish Patra , Ming Lei , Daniel Jordan , Mike Leach , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 4/7] MIPS: Loongson64: Remove custom count sync procudure Date: Mon, 17 Aug 2020 11:46:43 +0800 Message-Id: <20200817034701.3515721-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Now we have hotplug aware reliable sync-r4k, we can simply use that instead of our IPI based implementation. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/smp.h | 1 - arch/mips/loongson64/smp.c | 32 ++------------------------------ 2 files changed, 2 insertions(+), 31 deletions(-) diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 5d9ff61004ca..2300cc0bba34 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -52,7 +52,6 @@ extern int __cpu_logical_map[NR_CPUS]; #define SMP_CALL_FUNCTION 0x2 /* Octeon - Tell another core to flush its icache */ #define SMP_ICACHE_FLUSH 0x4 -#define SMP_ASK_C0COUNT 0x8 /* Mask of CPUs which are currently definitely operating coherently */ extern cpumask_t cpu_coherent_mask; diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index e744e1bee49e..d6a3a7c3d1b2 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -32,7 +32,6 @@ static void *ipi_clear0_regs[16]; static void *ipi_status0_regs[16]; static void *ipi_en0_regs[16]; static void *ipi_mailbox_buf[16]; -static uint32_t core0_c0count[NR_CPUS]; /* read a 32bit value from ipi register */ #define loongson3_ipi_read32(addr) readl(addr) @@ -307,8 +306,8 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) { - int i, cpu = smp_processor_id(); - unsigned int action, c0count; + int cpu = smp_processor_id(); + unsigned int action; action = ipi_read_clear(cpu); @@ -321,15 +320,6 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) irq_exit(); } - if (action & SMP_ASK_C0COUNT) { - BUG_ON(cpu != 0); - c0count = read_c0_count(); - c0count = c0count ? c0count : 1; - for (i = 1; i < nr_cpu_ids; i++) - core0_c0count[i] = c0count; - __wbflush(); /* Let others see the result ASAP */ - } - return IRQ_HANDLED; } @@ -340,7 +330,6 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) static void loongson3_init_secondary(void) { int i; - uint32_t initcount; unsigned int cpu = smp_processor_id(); unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP3 | STATUSF_IP2; @@ -356,23 +345,6 @@ static void loongson3_init_secondary(void) cpu_logical_map(cpu) % loongson_sysconf.cores_per_package); cpu_data[cpu].package = cpu_logical_map(cpu) / loongson_sysconf.cores_per_package; - - i = 0; - core0_c0count[cpu] = 0; - loongson3_send_ipi_single(0, SMP_ASK_C0COUNT); - while (!core0_c0count[cpu]) { - i++; - cpu_relax(); - } - - if (i > MAX_LOOPS) - i = MAX_LOOPS; - if (cpu_data[cpu].package) - initcount = core0_c0count[cpu] + i; - else /* Local access is faster for loops */ - initcount = core0_c0count[cpu] + i/2; - - write_c0_count(initcount); } static void loongson3_smp_finish(void) From patchwork Mon Aug 17 03:46:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716421 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36AF7739 for ; Mon, 17 Aug 2020 03:49:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1DF822072E for ; Mon, 17 Aug 2020 03:49:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="MfoazQ/P" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727827AbgHQDt1 (ORCPT ); Sun, 16 Aug 2020 23:49:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727818AbgHQDtX (ORCPT ); Sun, 16 Aug 2020 23:49:23 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7456BC061388 for ; Sun, 16 Aug 2020 20:49:23 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id C704E1FF2E; Mon, 17 Aug 2020 03:49:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636158; bh=tkpc/JTygn6o+xCIvRDfTn+uT6G2NyWz4hNvpeTgZbU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MfoazQ/PgCh5GA96W/lf7BkTN1v5bd84tXxLgIDPZgMuONl2mddmPNlnANRxUOzrT OBJLeZgqcHNpCbVSVcu5rojv87oL9nSB14ZwwdYDaCSK1qRX5sj7zXHWJ4agS/uCP8 CgaKmzZQm5Yaa6yjR4K4ypZG5CtTJ/FyrI5hyaao1swL1Il4LeDMysgprbnJMRcnUJ J9LEQm4qPNSyl4qroyAUa7yhJKKSPBRp2hH+eWYyjpCWai8oU0CEyFoGS25Zuv6mVb JP21CW1cN4lMqB61AXAcWOe08rxIccIOu08WPeXyeLLKHyYJMC1WYEs1OGFIjxo23u M0qE42HcTiI2A== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Serge Semin , Paul Burton , WANG Xuerui , Alexey Malahov , =?utf-8?b?5ZGo55Cw?= =?utf-8?b?5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , "Peter Zijlstra (Intel)" , Peter Xu , Sergey Korolev , Marc Zyngier , Anup Patel , Herbert Xu , Steven Price , Atish Patra , Ming Lei , Daniel Jordan , Mike Leach , Ulf Hansson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 5/7] MIPS: cevt-r4k: Don't handle IRQ if clockevent is not enabled Date: Mon, 17 Aug 2020 11:46:44 +0800 Message-Id: <20200817034701.3515721-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some platforms may have shared Cause.TI, bailing out in IRQ handler when clock event is not enabled can give another clock device a chance. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/cevt-r4k.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index f0c52d751d0a..d396b1011fee 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -142,6 +142,15 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id) if (handle_perf_irq(r2)) return IRQ_HANDLED; + cd = &per_cpu(mips_clockevent_device, cpu); + /* + * If the clockevent have not enabled, then no need to check the rest. + * Some platforms may have shared Cause.TI, bailing out here can + * give another clock device a chance. + */ + if (clockevent_state_detached(cd) || clockevent_state_shutdown(cd)) + return IRQ_NONE; + /* * The same applies to performance counter interrupts. But with the * above we now know that the reason we got here must be a timer @@ -150,7 +159,6 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id) if (!r2 || (read_c0_cause() & CAUSEF_TI)) { /* Clear Count/Compare Interrupt */ write_c0_compare(read_c0_compare()); - cd = &per_cpu(mips_clockevent_device, cpu); cd->event_handler(cd); return IRQ_HANDLED; From patchwork Mon Aug 17 03:46:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716425 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77EDF13A4 for ; Mon, 17 Aug 2020 03:49:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D0F82072E for ; Mon, 17 Aug 2020 03:49:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="r/L8sn/5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727856AbgHQDtm (ORCPT ); Sun, 16 Aug 2020 23:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727818AbgHQDtj (ORCPT ); Sun, 16 Aug 2020 23:49:39 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BA11C061388 for ; Sun, 16 Aug 2020 20:49:39 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id F146C200D0; Mon, 17 Aug 2020 03:49:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636178; bh=Q5RJ1NIgEccdftXxouCtJty5D3e1oMIrOLeVC8dh9Iw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r/L8sn/53RTqpNEUSf7STc7jzV9+RjbiDLarYZCxsaIzipCI5kb6ug9Yffe8t48su nWaqprhN/TZdSjlToFtqAQ2orJENiKh8Vf5hldy5m9194cREQA+VK3gQTZNqbglJaC akesoJgk5caoqXZl53MxMwlSmSGeWcowMuK/HSDlVuMQoMHs9r/JTXcVSZ5KamUuLh 6W3i1BHH14RgZiKHF977jl6449Y09mh3/eYwyyvoFGsRwt2UGJhpDT/S5QzlIur3A3 awYmntV1GV50L3KPcHQcbAG/v+YZcehD5lK7dWFxq4I6oVbu8vH9jMeJdU+wlZ1F5L R9utB2FS1PW9w== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Serge Semin , Paul Burton , WANG Xuerui , =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , Peter Xu , "Peter Zijlstra (Intel)" , Ingo Molnar , Sergey Korolev , Alexey Malahov , Marc Zyngier , Anup Patel , Daniel Jordan , Ulf Hansson , Atish Patra , Steven Price , Mike Leach , Ming Lei , Michael Kelley , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 6/7] MIPS: cevt-r4k: Enable intimer for Loongson CPUs with extimer Date: Mon, 17 Aug 2020 11:46:45 +0800 Message-Id: <20200817034701.3515721-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Loongson64C and Loongson64G have extimer feature, which is sharing Cause.TI with intimer (which is cevt-r4k). To ensure the cevt-r4k's usability, we need to add a callback for clock device to ensure intimer is enabled when cevt-r4k is enabled. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/kernel/cevt-r4k.c | 25 +++++++++++++++++++++++++ arch/mips/kernel/cpu-probe.c | 6 +++++- 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 78cf7e300f12..aec458eee2a5 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -576,6 +576,10 @@ # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) #endif +#ifndef cpu_has_extimer +# define cpu_has_extimer __opt(MIPS_CPU_EXTIMER) +#endif + #ifdef CONFIG_SMP /* * Some systems share FTLB RAMs between threads within a core (siblings in diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 388a82f28a87..854e1b44254b 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -429,6 +429,7 @@ enum cpu_type_enum { #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */ #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */ #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */ +#define MIPS_CPU_EXTIMER BIT_ULL(63) /* CPU has External Timer (Loongson) */ /* * CPU ASE encodings diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index d396b1011fee..a6e56e9d4e70 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -15,6 +15,8 @@ #include #include +#include +#include static int mips_next_event(unsigned long delta, struct clock_event_device *evt) @@ -302,6 +304,24 @@ core_initcall(r4k_register_cpufreq_notifier); #endif /* !CONFIG_CPU_FREQ */ +#ifdef CONFIG_CPU_LOONGSON64 +static int c0_compare_int_enable(struct clock_event_device *cd) +{ + if (cpu_has_extimer) + set_c0_config6(LOONGSON_CONF6_INTIMER); + + return 0; +} + +static int c0_compare_int_disable(struct clock_event_device *cd) +{ + if (cpu_has_extimer) + clear_c0_config6(LOONGSON_CONF6_INTIMER); + + return 0; +} +#endif + int r4k_clockevent_percpu_init(int cpu) { struct clock_event_device *cd; @@ -330,6 +350,11 @@ int r4k_clockevent_percpu_init(int cpu) cd->set_next_event = mips_next_event; cd->event_handler = mips_event_handler; +#ifdef CONFIG_CPU_LOONGSON64 + cd->set_state_oneshot = c0_compare_int_enable; + cd->set_state_shutdown = c0_compare_int_disable; +#endif + clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff); return 0; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e2955f1f6316..f41e8d4f6d84 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2030,6 +2030,9 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c) if (cfg2 & LOONGSON_CFG2_LEXT2) c->ases |= MIPS_ASE_LOONGSON_EXT2; + if (cfg2 & LOONGSON_CFG2_LLFTP) + c->options |= MIPS_CPU_EXTIMER; + if (cfg2 & LOONGSON_CFG2_LSPW) { c->options |= MIPS_CPU_LDPTE; c->guest.options |= MIPS_CPU_LDPTE; @@ -2088,7 +2091,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) * Also some early Loongson-3A2000 had wrong TLB type in Config * register, we correct it here. */ - c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE | + MIPS_CPU_EXTIMER; c->writecombine = _CACHE_UNCACHED_ACCELERATED; c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); From patchwork Mon Aug 17 03:46:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11716429 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4F106739 for ; Mon, 17 Aug 2020 03:50:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 386CA20738 for ; Mon, 17 Aug 2020 03:50:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="l3yc9oba" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727869AbgHQDuE (ORCPT ); Sun, 16 Aug 2020 23:50:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727813AbgHQDt7 (ORCPT ); Sun, 16 Aug 2020 23:49:59 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31213C061345; Sun, 16 Aug 2020 20:49:59 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 3D253200D1; Mon, 17 Aug 2020 03:49:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1597636198; bh=kL2YUnCYl8qwBpA6tmpQUNRMhCovsao/yjQt7sCo0Bo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l3yc9obazAd+ebc31MIheSBo1LGXzc2+BKtmErfwYN0nOQcBzgiqjToLCjPtMBla5 XLW5DctmBESfPdkcLgW9zf61XDVzByrtDNg1OLOwyTXOtkyfsBpVp4ADs6G2PkPA5R 4sTtWQsiHGEiZUY575dw0j5IXTHocCOTdN55ROmXU3dyfMmo5kr26TvOf3lfhPLIka bWAH/Yhte3hphyj3IgKBXYXDcVsNm6Bs0ce8lR46GGqw43a9jTtp9Kme2mU2Ds6snq k6tau/J34MKdQT+8Ou59wP0+2LOdKrV7lHRN+dzZABA/ooP+sQDozNm1kWFrT4UYFy eQ/5qA7R6GUvA== From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Thomas Bogendoerfer , Huacai Chen , Aleksandar Markovic , Paul Burton , Serge Semin , WANG Xuerui , =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Liangliang Huang , afzal mohammed , Ingo Molnar , Peter Xu , "Peter Zijlstra (Intel)" , Sergey Korolev , Alexey Malahov , Anup Patel , Marc Zyngier , "Rafael J. Wysocki" , Jens Axboe , Steven Price , Michael Kelley , Mike Leach , Ulf Hansson , Atish Patra , Ming Lei , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 7/7] MIPS: KVM: Don't use htimer when INTIMER is disabled Date: Mon, 17 Aug 2020 11:46:46 +0800 Message-Id: <20200817034701.3515721-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.28.0.rc1 In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> References: <20200817034701.3515721-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When INTIMER is disabled by host, the GT compare interrupt will be ignored. Signed-off-by: Jiaxun Yang --- arch/mips/kvm/vz.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 9d03bd0a604a..1d2140f7461a 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -341,6 +341,12 @@ static bool kvm_vz_should_use_htimer(struct kvm_vcpu *vcpu) if (kvm_mips_count_disabled(vcpu)) return false; + if (cpu_has_extimer) { + /* Guest htimer compare interrupt will be ignored if INTIMER is disabled */ + if (!(read_c0_config6() & LOONGSON_CONF6_INTIMER)) + return false; + } + /* Chosen frequency must match real frequency */ if (mips_hpt_frequency != vcpu->arch.count_hz) return false;