From patchwork Tue Aug 18 03:34:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 11719817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C765B15E4 for ; Tue, 18 Aug 2020 03:40:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BABE1207DE for ; Tue, 18 Aug 2020 03:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726398AbgHRDkK (ORCPT ); Mon, 17 Aug 2020 23:40:10 -0400 Received: from inva021.nxp.com ([92.121.34.21]:44512 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726302AbgHRDkJ (ORCPT ); Mon, 17 Aug 2020 23:40:09 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 41C9F2016DD; Tue, 18 Aug 2020 05:40:07 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 61AD32016D9; Tue, 18 Aug 2020 05:40:01 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id E4B6B402AD; Tue, 18 Aug 2020 05:39:53 +0200 (CEST) From: Anson Huang To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, gregkh@linuxfoundation.org, fugang.duan@nxp.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 1/5] dt-bindings: clock: Update i.MX28 example Date: Tue, 18 Aug 2020 11:34:41 +0800 Message-Id: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Update the i.MX28 clock example to align with MXS AUART binding doc to avoid below build error: Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml: serial@8006a000: clocks: [[4294967295, 45]] is too short Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml: serial@8006a000: compatible: Additional items are not allowed ('fsl,imx23-auart' was unexpected) Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml: serial@8006a000: compatible: ['fsl,imx28-auart', 'fsl,imx23-auart'] is too long Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml: serial@8006a000: 'dmas' is a required property Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml: serial@8006a000: 'dma-names' is a required property Signed-off-by: Anson Huang --- no change. --- Documentation/devicetree/bindings/clock/imx28-clock.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.yaml b/Documentation/devicetree/bindings/clock/imx28-clock.yaml index 72328d5..671b279 100644 --- a/Documentation/devicetree/bindings/clock/imx28-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx28-clock.yaml @@ -108,8 +108,10 @@ examples: }; serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + compatible = "fsl,imx28-auart"; reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; clocks = <&clks 45>; }; From patchwork Tue Aug 18 03:34:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 11719807 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9099A1575 for ; Tue, 18 Aug 2020 03:40:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83C64207D3 for ; Tue, 18 Aug 2020 03:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726620AbgHRDkP (ORCPT ); Mon, 17 Aug 2020 23:40:15 -0400 Received: from inva021.nxp.com ([92.121.34.21]:44622 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbgHRDkK (ORCPT ); Mon, 17 Aug 2020 23:40:10 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A43972016D9; Tue, 18 Aug 2020 05:40:08 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id C61842016D7; Tue, 18 Aug 2020 05:40:02 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 4B125402BE; Tue, 18 Aug 2020 05:39:55 +0200 (CEST) From: Anson Huang To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, gregkh@linuxfoundation.org, fugang.duan@nxp.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 2/5] dt-bindings: clock: Update i.MX23 example Date: Tue, 18 Aug 2020 11:34:42 +0800 Message-Id: <1597721685-9280-2-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> References: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Update the i.MX23 clock example to align with MXS AUART binding doc to avoid below build error: Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml: serial@8006c000: clocks: [[4294967295, 32]] is too short Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml: serial@8006c000: 'dmas' is a required property Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml: serial@8006c000: 'dma-names' is a required property Signed-off-by: Anson Huang --- no change. --- Documentation/devicetree/bindings/clock/imx23-clock.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.yaml b/Documentation/devicetree/bindings/clock/imx23-clock.yaml index 66cb238..4028c1f 100644 --- a/Documentation/devicetree/bindings/clock/imx23-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx23-clock.yaml @@ -87,6 +87,8 @@ examples: serial@8006c000 { compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; - interrupts = <24 25 23>; + interrupts = <24>; clocks = <&clks 32>; + dmas = <&dma_apbx 6>, <&dma_apbx 7>; + dma-names = "rx", "tx"; }; From patchwork Tue Aug 18 03:34:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 11719815 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5A8E214E3 for ; Tue, 18 Aug 2020 03:40:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C4AF2078E for ; Tue, 18 Aug 2020 03:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726752AbgHRDk2 (ORCPT ); Mon, 17 Aug 2020 23:40:28 -0400 Received: from inva021.nxp.com ([92.121.34.21]:44740 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726302AbgHRDkM (ORCPT ); Mon, 17 Aug 2020 23:40:12 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3EDC7200DE3; Tue, 18 Aug 2020 05:40:10 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3943C2000ED; Tue, 18 Aug 2020 05:40:04 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id AF45B402C3; Tue, 18 Aug 2020 05:39:56 +0200 (CEST) From: Anson Huang To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, gregkh@linuxfoundation.org, fugang.duan@nxp.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 3/5] dt-bindings: serial: Convert i.MX uart to json-schema Date: Tue, 18 Aug 2020 11:34:43 +0800 Message-Id: <1597721685-9280-3-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> References: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert the i.MX uart binding to DT schema format using json-schema. Signed-off-by: Anson Huang --- no change. --- .../devicetree/bindings/serial/fsl-imx-uart.txt | 40 ---------- .../devicetree/bindings/serial/fsl-imx-uart.yaml | 92 ++++++++++++++++++++++ 2 files changed, 92 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/fsl-imx-uart.txt create mode 100644 Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt deleted file mode 100644 index 9582fc2..0000000 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART) - -Required properties: -- compatible : Should be "fsl,-uart" -- reg : Address and length of the register set for the device -- interrupts : Should contain uart interrupt - -Optional properties: -- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works - in DCE mode by default. -- fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached - to the peripheral inverts the signal transmitted or received, - respectively, and that the peripheral should invert its output/input - using the INVT/INVR registers. -- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx, - linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485 - you must enable either the "uart-has-rtscts" or the "rts-gpios" - properties. In case you use "uart-has-rtscts" the signal that controls - the transceiver is actually CTS_B, not RTS_B. CTS_B is always output, - and RTS_B is input, regardless of dte-mode. - -Please check Documentation/devicetree/bindings/serial/serial.yaml -for the complete list of generic properties. - -Note: Each uart controller should have an alias correctly numbered -in "aliases" node. - -Example: - -aliases { - serial0 = &uart1; -}; - -uart1: serial@73fbc000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fbc000 0x4000>; - interrupts = <31>; - uart-has-rtscts; - fsl,dte-mode; -}; diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml new file mode 100644 index 0000000..cba3f83 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Fabio Estevam + +allOf: + - $ref: "serial.yaml" + - $ref: "rs485.yaml" + +properties: + compatible: + oneOf: + - const: fsl,imx1-uart + - const: fsl,imx21-uart + - const: fsl,imx53-uart + - const: fsl,imx6q-uart + - items: + - enum: + - fsl,imx25-uart + - fsl,imx27-uart + - fsl,imx31-uart + - fsl,imx35-uart + - fsl,imx50-uart + - fsl,imx51-uart + - const: fsl,imx21-uart + - items: + - enum: + - fsl,imx6sl-uart + - fsl,imx6sll-uart + - fsl,imx6sx-uart + - fsl,imx6ul-uart + - fsl,imx7d-uart + - const: fsl,imx6q-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,dte-mode: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicate the uart works in DTE mode. The uart works in DCE mode by default. + + fsl,inverted-tx: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicate that the hardware attached to the peripheral inverts the signal + transmitted, and that the peripheral should invert its output using the + INVT registers. + + fsl,inverted-rx: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicate that the hardware attached to the peripheral inverts the signal + received, and that the peripheral should invert its input using the + INVR registers. + + uart-has-rtscts: true + + rs485-rts-delay: true + rs485-rts-active-low: true + rs485-rx-during-tx: true + linux,rs485-enabled-at-boot-time: true + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + aliases { + serial0 = &uart1; + }; + + uart1: serial@73fbc000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fbc000 0x4000>; + interrupts = <31>; + uart-has-rtscts; + fsl,dte-mode; + }; From patchwork Tue Aug 18 03:34:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 11719803 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 523D414E3 for ; Tue, 18 Aug 2020 03:40:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4351F20706 for ; Tue, 18 Aug 2020 03:40:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726691AbgHRDkR (ORCPT ); Mon, 17 Aug 2020 23:40:17 -0400 Received: from inva020.nxp.com ([92.121.34.13]:39476 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726599AbgHRDkR (ORCPT ); Mon, 17 Aug 2020 23:40:17 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A377E1A0114; Tue, 18 Aug 2020 05:40:11 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9CD581A0FE9; Tue, 18 Aug 2020 05:40:05 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 1504B402DD; Tue, 18 Aug 2020 05:39:58 +0200 (CEST) From: Anson Huang To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, gregkh@linuxfoundation.org, fugang.duan@nxp.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 4/5] dt-bindings: serial: Convert MXS auart to json-schema Date: Tue, 18 Aug 2020 11:34:44 +0800 Message-Id: <1597721685-9280-4-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> References: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert the MXS auart binding to DT schema format using json-schema. Signed-off-by: Anson Huang --- changes since V2: - update maintainer. --- .../devicetree/bindings/serial/fsl-mxs-auart.txt | 53 ------------- .../devicetree/bindings/serial/fsl-mxs-auart.yaml | 91 ++++++++++++++++++++++ 2 files changed, 91 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt create mode 100644 Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt deleted file mode 100644 index 5c96d41..0000000 --- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale MXS Application UART (AUART) - -Required properties for all SoCs: -- compatible : Should be one of fallowing variants: - "fsl,imx23-auart" - Freescale i.MX23 - "fsl,imx28-auart" - Freescale i.MX28 - "alphascale,asm9260-auart" - Alphascale ASM9260 -- reg : Address and length of the register set for the device -- interrupts : Should contain the auart interrupt numbers -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and AUART DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: "rx" for RX channel, "tx" for TX channel. - -Required properties for "alphascale,asm9260-auart": -- clocks : the clocks feeding the watchdog timer. See clock-bindings.txt -- clock-names : should be set to - "mod" - source for tick counter. - "ahb" - ahb gate. - -Optional properties: -- uart-has-rtscts : Indicate the UART has RTS and CTS lines - for hardware flow control, - it also means you enable the DMA support for this UART. -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD - line respectively. It will use specified PIO instead of the peripheral - function pin for the USART feature. - If unsure, don't specify this property. - -Example: -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - cts-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; -}; - -Note: Each auart port should have an alias correctly numbered in "aliases" -node. - -Example: - -aliases { - serial0 = &auart0; - serial1 = &auart1; - serial2 = &auart2; - serial3 = &auart3; - serial4 = &auart4; -}; diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml new file mode 100644 index 0000000..ce1d894 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl-mxs-auart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS Application UART (AUART) + +maintainers: + - Fabio Estevam + +allOf: + - $ref: "serial.yaml" + +properties: + compatible: + enum: + - fsl,imx23-auart + - fsl,imx28-auart + - alphascale,asm9260-auart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + clocks: + items: + - description: mod clock + - description: ahb clock + minItems: 1 + + clock-names: + items: + - const: mod + - const: ahb + minItems: 1 + + uart-has-rtscts: true + rts-gpios: true + cts-gpios: true + dtr-gpios: true + dsr-gpios: true + rng-gpios: true + dcd-gpios: true + +if: + properties: + compatible: + contains: + enum: + - alphascale,asm9260-auart +then: + required: + - clocks + - clock-names + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + aliases { + serial0 = &auart0; + }; + + auart0: serial@8006a000 { + compatible = "fsl,imx28-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + }; From patchwork Tue Aug 18 03:34:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 11719805 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22DE91575 for ; Tue, 18 Aug 2020 03:40:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 144242078D for ; Tue, 18 Aug 2020 03:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726721AbgHRDkV (ORCPT ); Mon, 17 Aug 2020 23:40:21 -0400 Received: from inva021.nxp.com ([92.121.34.21]:44892 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726612AbgHRDkR (ORCPT ); Mon, 17 Aug 2020 23:40:17 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4AC772016E6; Tue, 18 Aug 2020 05:40:14 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 437C82016E5; Tue, 18 Aug 2020 05:40:08 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 6E8E4402E1; Tue, 18 Aug 2020 05:39:59 +0200 (CEST) From: Anson Huang To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, gregkh@linuxfoundation.org, fugang.duan@nxp.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 5/5] dt-bindings: serial: Convert NXP lpuart to json-schema Date: Tue, 18 Aug 2020 11:34:45 +0800 Message-Id: <1597721685-9280-5-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> References: <1597721685-9280-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert the NXP lpuart binding to DT schema format using json-schema. Signed-off-by: Anson Huang --- changes since V2: - update maintainer, the original owner's email address is no longer valid, use one of the patch contributors as well as NXP's UART owner as maintainer. --- .../devicetree/bindings/serial/fsl-lpuart.txt | 43 ------------ .../devicetree/bindings/serial/fsl-lpuart.yaml | 79 ++++++++++++++++++++++ 2 files changed, 79 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/fsl-lpuart.txt create mode 100644 Documentation/devicetree/bindings/serial/fsl-lpuart.yaml diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt deleted file mode 100644 index e7448b9..0000000 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Freescale low power universal asynchronous receiver/transmitter (lpuart) - -Required properties: -- compatible : - - "fsl,vf610-lpuart" for lpuart compatible with the one integrated - on Vybrid vf610 SoC with 8-bit register organization - - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated - on LS1021A SoC with 32-bit big-endian register organization - - "fsl,ls1028a-lpuart" for lpuart compatible with the one integrated - on LS1028A SoC with 32-bit little-endian register organization - - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated - on i.MX7ULP SoC with 32-bit little-endian register organization - - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated - on i.MX8QXP SoC with 32-bit little-endian register organization - - "fsl,imx8qm-lpuart" for lpuart compatible with the one integrated - on i.MX8QM SoC with 32-bit little-endian register organization -- reg : Address and length of the register set for the device -- interrupts : Should contain uart interrupt -- clocks : phandle + clock specifier pairs, one for each entry in clock-names -- clock-names : For vf610/ls1021a/ls1028a/imx7ulp, "ipg" clock is for uart - bus/baud clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used - to access lpuart controller registers, it also requires "baud" clock for - module to receive/transmit data. - -Optional properties: -- dmas: A list of two dma specifiers, one for each entry in dma-names. -- dma-names: should contain "tx" and "rx". -- rs485-rts-active-low, linux,rs485-enabled-at-boot-time: see rs485.txt - -Note: Optional properties for DMA support. Write them both or both not. - -Example: - -uart0: serial@40027000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40027000 0x1000>; - interrupts = <0 61 0x00>; - clocks = <&clks VF610_CLK_UART0>; - clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; - dma-names = "rx","tx"; - }; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml new file mode 100644 index 0000000..e82c2cf --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale low power universal asynchronous receiver/transmitter (lpuart) + +maintainers: + - Fugang Duan + +allOf: + - $ref: "rs485.yaml" + +properties: + compatible: + enum: + - fsl,vf610-lpuart + - fsl,ls1021a-lpuart + - fsl,ls1028a-lpuart + - fsl,imx7ulp-lpuart + - fsl,imx8qxp-lpuart + - fsl,imx8qm-lpuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ipg clock + - description: baud clock + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: baud + minItems: 1 + maxItems: 2 + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + rs485-rts-active-low: true + linux,rs485-enabled-at-boot-time: true + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@40027000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40027000 0x1000>; + interrupts = <0 61 0x00>; + clocks = <&clks VF610_CLK_UART0>; + clock-names = "ipg"; + dmas = <&edma0 0 2>, <&edma0 0 3>; + dma-names = "rx","tx"; + };