From patchwork Wed Aug 19 11:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 11723577 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7138618 for ; Wed, 19 Aug 2020 11:46:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C136221744 for ; Wed, 19 Aug 2020 11:46:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ts+DpD+e"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="RdLMUM5X" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C136221744 Authentication-Results: mail.kernel.org; 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Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 44/49] dts: hisilicon: hi3670.dtsi: add I2C settings Date: Wed, 19 Aug 2020 13:46:12 +0200 Message-Id: <577acc4d4de8f812d4f58de167a731bfc6d1d32e.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_074625_214098_6D92A073 X-CRM114-Status: GOOD ( 13.41 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Manivannan Sadhasivam , Mauro Carvalho Chehab , linuxarm@huawei.com, dri-devel , linux-kernel@vger.kernel.org, Rob Herring , John Stultz , Wei Xu , Daniel Vetter , mauro.chehab@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The I2C buses are not declared at the device tree. As this will be needed by further patches, add them, keeping all in disabled state. Per-board settings can override it. Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index b1acb4fb1d1c..416f69c782d7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -723,5 +723,76 @@ dwmmc2: dwmmc2@fc183000 { card-detect-delay = <200>; status = "disabled"; }; + + /* I2C */ + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c2: i2c@ffd73000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd73000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&iomcu HI3670_CLK_GATE_I2C2>; + resets = <&iomcu_rst 0x20 5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c4: i2c@fdf0d000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0d000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>; + resets = <&crg_rst 0x78 27>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>; + status = "disabled"; + }; }; }; From patchwork Wed Aug 19 11:46:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 11723659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8A478618 for ; Wed, 19 Aug 2020 11:48:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55C00207BB for ; Wed, 19 Aug 2020 11:48:30 +0000 (UTC) Authentication-Results: mail.kernel.org; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597837584; bh=5GS0RTIKrmx37wIM0DKdGb8tbjBjS+1xmPyQ42ARTpk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oUmVK4NgKxFDLZLTXbMVUbYYyYMhmmd9fKYXotoAni1IqcKrso/lnz0pBxXbU+Blz AWJXPfHQ8vmdXpyERgkVutmJoVABOKG05MseM89HcULnMVuBf+G7kmNQZ7lQkS23Nc n8juiXA5jxEZSHcqcpd9I63xm/IkTZCjjNwXMnyg= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00Euc8-K1; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 45/49] dts: hikey970-pinctrl.dtsi: add missing pinctrl settings Date: Wed, 19 Aug 2020 13:46:13 +0200 Message-Id: <7e0450b87df8862852669d179eb9579b64fcf815.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_074625_240884_E9259DEF X-CRM114-Status: GOOD ( 14.19 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Manivannan Sadhasivam , Mauro Carvalho Chehab , linuxarm@huawei.com, dri-devel , linux-kernel@vger.kernel.org, Rob Herring , John Stultz , Wei Xu , Daniel Vetter , mauro.chehab@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There are several pinctrl settings that are missing at this DT file. Also, the entries are out of order. Add the missing bits, as they'll be required by the DRM driver - and probably by other drivers not upstreamed yet. Reorder the entres, adding the missing bits. Signed-off-by: Mauro Carvalho Chehab --- .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 548 +++++++++++++++++- 1 file changed, 537 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index d456b0aa6f58..75723a1ad5ab 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -61,6 +61,153 @@ uart6_pmx_func: uart6_pmx_func { 0x060 MUX_M1 /* UART6_TXD */ >; }; + + i2c3_pmx_func: i2c3_pmx_func { + pinctrl-single,pins = < + 0x010 MUX_M1 /* I2C3_SCL */ + 0x014 MUX_M1 /* I2C3_SDA */ + >; + }; + + i2c4_pmx_func: i2c4_pmx_func { + pinctrl-single,pins = < + 0x03c MUX_M1 /* I2C4_SCL */ + 0x040 MUX_M1 /* I2C4_SDA */ + >; + }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x714 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x048 MUX_M0 /* CAM1_RST */ + >; + }; + + cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x098 MUX_M0 /* CAM0_PWD_N */ + >; + }; + + cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CAM1_PWD_N */ + >; + }; + + isp0_pmx_func: isp0_pmx_func { + pinctrl-single,pins = < + 0x018 MUX_M1 /* ISP_CLK0 */ + 0x024 MUX_M1 /* ISP_SCL0 */ + 0x028 MUX_M1 /* ISP_SDA0 */ + >; + }; + + isp1_pmx_func: isp1_pmx_func { + pinctrl-single,pins = < + 0x01c MUX_M1 /* ISP_CLK1 */ + 0x02c MUX_M1 /* ISP_SCL1 */ + 0x030 MUX_M1 /* ISP_SDA1 */ + >; + }; + }; + + pmx1: pinmux@fff11000 { + compatible = "pinctrl-single"; + reg = <0x0 0xfff11000 0x0 0x73c>; + #gpio-range-cells = <0x3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 46 0>; + + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x064 MUX_M0 /* GPIO_203 */ + >; + }; + + pd_pmx_func: pd_pmx_func{ + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_221 */ + >; + }; + + i2s2_pmx_func: i2s2_pmx_func { + pinctrl-single,pins = < + 0x050 MUX_M1 /* I2S2_DI */ + 0x054 MUX_M1 /* I2S2_DO */ + 0x058 MUX_M1 /* I2S2_XCLK */ + 0x05c MUX_M1 /* I2S2_XFS */ + >; + }; + + spi0_pmx_func: spi0_pmx_func { + pinctrl-single,pins = < + 0x094 MUX_M1 /* SPI0_CLK */ + 0x098 MUX_M1 /* SPI0_DI */ + 0x09c MUX_M1 /* SPI0_DO */ + 0x0a0 MUX_M1 /* SPI0_CS0_N */ + >; + }; + + spi2_pmx_func: spi2_pmx_func { + pinctrl-single,pins = < + 0x710 MUX_M1 /* SPI2_CLK */ + 0x714 MUX_M1 /* SPI2_DI */ + 0x718 MUX_M1 /* SPI2_DO */ + 0x71c MUX_M1 /* SPI2_CS0_N */ + >; + }; + + spi3_pmx_func: spi3_pmx_func { + pinctrl-single,pins = < + 0x72c MUX_M1 /* SPI3_CLK */ + 0x730 MUX_M1 /* SPI3_DI */ + 0x734 MUX_M1 /* SPI3_DO */ + 0x738 MUX_M1 /* SPI3_CS0_N */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0x020 MUX_M1 /* I2C0_SCL */ + 0x024 MUX_M1 /* I2C0_SDA */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0x028 MUX_M1 /* I2C1_SCL */ + 0x02c MUX_M1 /* I2C1_SDA */ + >; + }; + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0x030 MUX_M1 /* I2C2_SCL */ + 0x034 MUX_M1 /* I2C2_SDA */ + >; + }; + + pcie_clkreq_pmx_func: pcie_clkreq_pmx_func { + pinctrl-single,pins = < + 0x084 MUX_M1 /* PCIE0_CLKREQ_N */ + >; + }; + + gpio185_pmx_func: gpio185_pmx_func { + pinctrl-single,pins = <0x01C 0x1>; + }; + + gpio185_pmx_idle: gpio185_pmx_idle { + pinctrl-single,pins = <0x01C 0x0>; + }; }; pmx2: pinmux@e896c800 { @@ -184,6 +331,108 @@ PULL_UP DRIVE7_02MA DRIVE6_MASK >; }; + + i2c3_cfg_func: i2c3_cfg_func { + pinctrl-single,pins = < + 0x014 0x0 /* I2C3_SCL */ + 0x018 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c4_cfg_func: i2c4_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2C4_SCL */ + 0x044 0x0 /* I2C4_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x714 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x04C 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x09C 0x0 /* CAM0_PWD_N */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x048 0x0 /* CAM1_PWD_N */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x01C 0x0 /* ISP_CLK0 */ + 0x028 0x0 /* ISP_SCL0 */ + 0x02C 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + isp1_cfg_func: isp1_cfg_func { + pinctrl-single,pins = < + 0x020 0x0 /* ISP_CLK1 */ + 0x030 0x0 /* ISP_SCL1 */ + 0x034 0x0 /* ISP_SDA1 */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; }; pmx5: pinmux@fc182000 { @@ -338,22 +587,299 @@ DRIVE6_MASK }; }; - pmx1: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0x73c>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 46 0>; - }; - pmx16: pinmux@fff11800 { compatible = "pinconf-single"; reg = <0x0 0xfff11800 0x0 0x73c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + pwr_key_cfg_func: pwr_key_cfg_func { + pinctrl-single,pins = < + 0x090 0x0 /* GPIO_203 */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0AC 0x0 /* GPIO_221 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi0_cfg_func: spi0_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* SPI0_DI */ + 0x0cc 0x0 /* SPI0_DO */ + 0x0d0 0x0 /* SPI0_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x714 0x0 /* SPI2_DI */ + 0x718 0x0 /* SPI2_DO */ + 0x71c 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x730 0x0 /* SPI3_DI */ + 0x734 0x0 /* SPI3_DO */ + 0x738 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + spi0_clk_cfg_func: spi0_clk_cfg_func { + pinctrl-single,pins = < + 0x0c4 0x0 /* SPI0_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + spi2_clk_cfg_func: spi2_clk_cfg_func { + pinctrl-single,pins = < + 0x710 0x0 /* SPI2_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + spi3_clk_cfg_func: spi3_clk_cfg_func { + pinctrl-single,pins = < + 0x72c 0x0 /* SPI3_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_10MA DRIVE6_MASK + >; + }; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x04c 0x0 /* I2C0_SCL */ + 0x050 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x054 0x0 /* I2C1_SCL */ + 0x058 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0x05c 0x0 /* I2C2_SCL */ + 0x060 0x0 /* I2C2_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + pcie_clkreq_cfg_func: pcie_clkreq_cfg_func { + pinctrl-single,pins = < + 0x0b0 0x0 + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x07c 0x0 /* I2S2_DI */ + 0x080 0x0 /* I2S2_DO */ + 0x084 0x0 /* I2S2_XCLK */ + 0x088 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + gpio185_cfg_func: gpio185_cfg_func { + pinctrl-single,pins = <0x048 0>; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x00 0x70>; + pinctrl-single,slew-rate = <0x0 0x80>; + }; + + gpio185_cfg_idle: gpio185_cfg_idle { + pinctrl-single,pins = <0x048 0>; + pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x00 0x70>; + pinctrl-single,slew-rate = <0x0 0x80>; + }; }; }; }; From patchwork Wed Aug 19 11:46:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 11724001 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 85D94913 for ; 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Wed, 19 Aug 2020 11:46:31 +0000 Received: from mail.kernel.org (ip5f5ad5a3.dynamic.kabel-deutschland.de [95.90.213.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A72762312D; Wed, 19 Aug 2020 11:46:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597837583; bh=+UhVBmbMj6lt2RenvveVdDhvKup+dtdi1C8Rlc5YXQc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gn3Rncg45FO46KGjrWfViln7lPI6scjaw6Qi6P1iGD4a5UGpsXydDEzVtlW1Xnnea sAjfuFU3NP3g/vxFtalAyXJqGAO4dWPjJVL/MCkcpbCJJ3PwcXBVpZvcpMsBs7JeGg GQuKo+Tp58wJSDZOU3q+Fl1D7NltMAf5XLGeEnUI= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00EucA-LD; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 46/49] dt: hisilicon: add support for the PMIC found on Hikey 970 Date: Wed, 19 Aug 2020 13:46:14 +0200 Message-Id: <9df854e76bedc8726c634dee213f4520b6449b1e.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_074625_108305_21CF9C0B X-CRM114-Status: GOOD ( 20.06 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Manivannan Sadhasivam , Mauro Carvalho Chehab , linuxarm@huawei.com, dri-devel , linux-kernel@vger.kernel.org, Rob Herring , John Stultz , Wei Xu , Daniel Vetter , mauro.chehab@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add a device tree for the HiSilicon 6421v600 SPMI PMIC, used on HiKey970 board. As we now have support for it, change the fixed regulators used by the SD I/O to use the proper LDO supplies. Signed-off-by: Mauro Carvalho Chehab --- .../boot/dts/hisilicon/hi3670-hikey970.dts | 22 +- .../boot/dts/hisilicon/hikey970-pmic.dtsi | 197 ++++++++++++++++++ 2 files changed, 200 insertions(+), 19 deletions(-) create mode 100644 arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 01234a175dcd..a9ad90e769ad 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -12,6 +12,7 @@ #include "hi3670.dtsi" #include "hikey970-pinctrl.dtsi" +#include "hikey970-pmic.dtsi" / { model = "HiKey970"; @@ -39,23 +40,6 @@ memory@0 { reg = <0x0 0x0 0x0 0x0>; }; - sd_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sd_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - wlan_en: wlan-en-1-8v { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; @@ -402,8 +386,8 @@ &dwmmc1 { pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; - vmmc-supply = <&sd_3v3>; - vqmmc-supply = <&sd_1v8>; + vmmc-supply = <&ldo16>; + vqmmc-supply = <&ldo9>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi new file mode 100644 index 000000000000..843e841c7371 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hi6421v600 SPMI PMIC used at the HiKey970 Development Board + * + * Copyright (C) 2020, Huawei Tech. Co., Ltd. + */ + +#include + +/ { + spmi: spmi@fff24000 { + compatible = "hisilicon,kirin970-spmi-controller"; + #address-cells = <2>; + #size-cells = <0>; + status = "ok"; + reg = <0x0 0xfff24000 0x0 0x1000>; + spmi-channel = <2>; + + pmic: pmic@0 { + compatible = "hisilicon,hi6421-spmi"; + reg = <0 SPMI_USID>; + + #interrupt-cells = <2>; + interrupt-controller; + gpios = <&gpio28 0 0>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + ldo3: ldo3@16 { + reg = <0x16>; + vsel-reg = <0x51>; + + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + + enable-mask = <0x01>; + + voltage-table = <1500000>, <1550000>, + <1600000>, <1650000>, + <1700000>, <1725000>, + <1750000>, <1775000>, + <1800000>, <1825000>, + <1850000>, <1875000>, + <1900000>, <1925000>, + <1950000>, <2000000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo4: ldo4@17 { /* 40 PIN */ + reg = <0x17>; + vsel-reg = <0x52>; + + regulator-name = "ldo4"; + regulator-min-microvolt = <1725000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + hi6421-vsel = <0x52 0x07>; + voltage-table = <1725000>, <1750000>, + <1775000>, <1800000>, + <1825000>, <1850000>, + <1875000>, <1900000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo9: ldo9@1C { /* SDCARD I/O */ + reg = <0x1C>; + vsel-reg = <0x57>; + + regulator-name = "ldo9"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <1750000>, <1800000>, + <1825000>, <2800000>, + <2850000>, <2950000>, + <3000000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <360>; + }; + + ldo15: ldo15@21 { /* UFS */ + reg = <0x21>; + vsel-reg = <0x5c>; + + regulator-name = "ldo15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <1800000>, <1850000>, + <2400000>, <2600000>, + <2700000>, <2850000>, + <2950000>, <3000000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo16: ldo16@22 { /* SD */ + reg = <0x22>; + vsel-reg = <0x5d>; + + regulator-name = "ldo16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <1800000>, <1850000>, + <2400000>, <2600000>, + <2700000>, <2850000>, + <2950000>, <3000000>; + off-on-delay-us = <20000>; + startup-delay-us = <360>; + }; + + ldo17: ldo17@23 { + reg = <0x23>; + vsel-reg = <0x5e>; + + regulator-name = "ldo17"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + + enable-mask = <0x01>; + idle-mode-mask = <0x10>; + eco-microamp = <10000>; + + voltage-table = <2500000>, <2600000>, + <2700000>, <2800000>, + <3000000>, <3100000>, + <3200000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo33: ldo33@32 { /* PEX8606 */ + reg = <0x32>; + vsel-reg = <0x6d>; + regulator-name = "ldo33"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + enable-mask = <0x01>; + + voltage-table = <2500000>, <2600000>, + <2700000>, <2800000>, + <3000000>, <3100000>, + <3200000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + + ldo34: ldo34@33 { /* GPS AUX IN VDD */ + reg = <0x33>; + vsel-reg = <0x6e>; + + regulator-name = "ldo34"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + + enable-mask = <0x01>; + + voltage-table = <2600000>, <2700000>, + <2800000>, <2900000>, + <3000000>, <3100000>, + <3200000>, <3300000>; + off-on-delay-us = <20000>; + startup-delay-us = <120>; + }; + }; + }; + }; +}; From patchwork Wed Aug 19 11:46:15 2020 Content-Type: text/plain; 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Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 47/49] dts: add support for Hikey 970 DRM Date: Wed, 19 Aug 2020 13:46:15 +0200 Message-Id: <0f87d492431d4163873498c954d87595bf8776a0.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_074625_325330_F79C5EDB X-CRM114-Status: GOOD ( 18.44 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jesper Dangaard Brouer , Daniel Borkmann , Manivannan Sadhasivam , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, John Fastabend , linuxarm@huawei.com, dri-devel , Alexei Starovoitov , Rob Herring , John Stultz , Wei Xu , Daniel Vetter , netdev@vger.kernel.org, mauro.chehab@huawei.com, Jakub Kicinski , bpf@vger.kernel.org, "David S. Miller" , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the needed bits for the DRM driver to work with the Hikey 970 board. Signed-off-by: Mauro Carvalho Chehab --- .../boot/dts/hisilicon/hi3670-hikey970.dts | 52 +++++++ arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 6 + .../boot/dts/hisilicon/hikey970-drm.dtsi | 130 ++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index a9ad90e769ad..b3e16378182e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -13,6 +13,7 @@ #include "hi3670.dtsi" #include "hikey970-pinctrl.dtsi" #include "hikey970-pmic.dtsi" +#include "hikey970-drm.dtsi" / { model = "HiKey970"; @@ -40,6 +41,27 @@ memory@0 { reg = <0x0 0x0 0x0 0x0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_dma_reserved: drm_dma_mem_region { + compatible = "shared-dma-pool"; + reg = <0 0x32200000 0 0x8000000>; + alignment = <0x400000>; + no-map; + }; + }; + + fixed_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + wlan_en: wlan-en-1-8v { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; @@ -435,3 +457,33 @@ &uart6 { label = "LS-UART1"; status = "okay"; }; + +&i2c4 { + status = "okay"; + + adv7533: adv7533@39 { + compatible = "adi,adv7533"; + reg = <0x39>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + v1p2-supply = <&ldo3>; + avdd-supply = <&ldo3>; + dvdd-supply = <&ldo3>; + pvdd-supply = <&ldo3>; + a2vdd-supply = <&ldo3>; + v3p3-supply = <&fixed_3v3>; + + interrupt-parent = <&gpio1>; + interrupts = <1 2>; + pd-gpio = <&gpio27 1 0>; + sel-gpio = <&gpio25 7 0>; + adi,dsi-lanes = <4>; + adi,disable-timing-generator; + #sound-dai-cells = <0>; + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 416f69c782d7..e2b2e21295a7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -194,6 +194,12 @@ media2_crg: media2_crgctrl@e8900000 { #clock-cells = <1>; }; + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + uart0: serial@fdf02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf02000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi new file mode 100644 index 000000000000..3bd744b061ed --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + dpe: dpe@E8600000 { + compatible = "hisilicon,kirin970-dpe"; + memory-region = <&drm_dma_reserved>; + // DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, PMCTRL, MEDIA_CRG + reg = <0 0xE8600000 0 0xC0000>, + <0 0xFFF35000 0 0x1000>, + <0 0xFFF0A000 0 0x1000>, + <0 0xE8A09000 0 0x1000>, + <0 0xE86C0000 0 0x10000>, + <0 0xFFF31000 0 0x1000>, + <0 0xE87FF000 0 0x1000>; + // dss-pdp + interrupts = <0 245 4>; + + clocks = <&media1_crg HI3670_ACLK_GATE_DSS>, + <&media1_crg HI3670_PCLK_GATE_DSS>, + <&media1_crg HI3670_CLK_GATE_EDC0>, + <&media1_crg HI3670_CLK_GATE_LDI0>, + <&media1_crg HI3670_CLK_GATE_DSS_AXI_MM>, + <&media1_crg HI3670_PCLK_GATE_MMBUF>, + <&crg_ctrl HI3670_PCLK_GATE_PCTRL>; + + clock-names = "aclk_dss", + "pclk_dss", + "clk_edc0", + "clk_ldi0", + "clk_dss_axi_mm", + "pclk_mmbuf", + "pclk_pctrl"; + + dma-coherent; + + port { + dpe_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + + iommu_info { + start-addr = <0x8000>; + size = <0xbfff8000>; + }; + }; + + dsi: dsi@E8601000 { + compatible = "hisilicon,kirin970-dsi"; + reg = <0 0xE8601000 0 0x7F000>, + <0 0xFFF35000 0 0x1000>, + <0 0xE8A09000 0 0x1000>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_CFG>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_CFG>, + <&crg_ctrl HI3670_PCLK_GATE_DSI0>, + <&crg_ctrl HI3670_PCLK_GATE_DSI1>; + clock-names = "clk_txdphy0_ref", + "clk_txdphy1_ref", + "clk_txdphy0_cfg", + "clk_txdphy1_cfg", + "pclk_dsi0", + "pclk_dsi1"; + + #address-cells = <1>; + #size-cells = <0>; + mux-gpio = <&gpio25 7 0>;//HDMI_SEL(GPIO_207) + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dpe_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + + dsi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel0_in>; + }; + }; + }; + + panel@1 { + compatible = "hisilicon,mipi-hikey"; + #address-cells = <2>; + #size-cells = <2>; + reg = <1>; + panel-width-mm = <94>; + panel-height-mm = <151>; + vdd-supply = <&ldo3>; + pwr-en-gpio = <&gpio21 3 0>;//GPIO_171 + bl-en-gpio = <&gpio6 4 0>;//GPIO_052 + pwm-gpio = <&gpio23 1 0>;//GPIO_185 + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi_out1>; + }; + }; + }; + }; + + panel_pwm { + #address-cells = <2>; + #size-cells = <2>; + compatible = "hisilicon,hisipwm"; + reg = <0 0xE8A04000 0 0x1000>, + <0 0xFFF35000 0 0x1000>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PWM>; + clock-names = "clk_pwm"; + pinctrl-names = "default","idle"; + pinctrl-0 = <&gpio185_pmx_func &gpio185_cfg_func>; + pinctrl-1 = <&gpio185_pmx_idle &gpio185_cfg_idle>; + }; +}; From patchwork Wed Aug 19 11:46:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 11724005 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B36A8913 for ; Wed, 19 Aug 2020 12:52:02 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 688AC206B5 for ; Wed, 19 Aug 2020 12:52:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Y4AUhFgL"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="zZBYyU78" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 688AC206B5 Authentication-Results: mail.kernel.org; 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Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 48/49] staging: hikey9xx/gpu: drop kirin9xx_pwm Date: Wed, 19 Aug 2020 13:46:16 +0200 Message-Id: <119ae70a01d925f918705817fe185301e89edbda.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_074625_567570_0BDDC4FB X-CRM114-Status: GOOD ( 28.42 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, Liwei Cai , linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Mauro Carvalho Chehab , Chen Feng , linuxarm@huawei.com, dri-devel , Xiubin Zhang , Rob Herring , John Stultz , Wei Xu , Daniel Vetter , mauro.chehab@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This is part of support for a panel display. Those don't come with the Hikey 960 or 970 boards. As I don't have any of those for tests, and we didn't port another required driver for this to work, for now, let's drop it. This patch can be reversed later, if one would be adding support for it. Signed-off-by: Mauro Carvalho Chehab --- .../boot/dts/hisilicon/hikey970-drm.dtsi | 37 -- drivers/staging/hikey9xx/gpu/Makefile | 2 +- drivers/staging/hikey9xx/gpu/kirin9xx_pwm.c | 404 ------------------ 3 files changed, 1 insertion(+), 442 deletions(-) delete mode 100644 drivers/staging/hikey9xx/gpu/kirin9xx_pwm.c diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi index 3bd744b061ed..503c7c9425c8 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi @@ -87,44 +87,7 @@ dsi_out0: endpoint@0 { reg = <0>; remote-endpoint = <&adv7533_in>; }; - - dsi_out1: endpoint@1 { - reg = <1>; - remote-endpoint = <&panel0_in>; - }; }; }; - - panel@1 { - compatible = "hisilicon,mipi-hikey"; - #address-cells = <2>; - #size-cells = <2>; - reg = <1>; - panel-width-mm = <94>; - panel-height-mm = <151>; - vdd-supply = <&ldo3>; - pwr-en-gpio = <&gpio21 3 0>;//GPIO_171 - bl-en-gpio = <&gpio6 4 0>;//GPIO_052 - pwm-gpio = <&gpio23 1 0>;//GPIO_185 - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi_out1>; - }; - }; - }; - }; - - panel_pwm { - #address-cells = <2>; - #size-cells = <2>; - compatible = "hisilicon,hisipwm"; - reg = <0 0xE8A04000 0 0x1000>, - <0 0xFFF35000 0 0x1000>; - clocks = <&crg_ctrl HI3670_CLK_GATE_PWM>; - clock-names = "clk_pwm"; - pinctrl-names = "default","idle"; - pinctrl-0 = <&gpio185_pmx_func &gpio185_cfg_func>; - pinctrl-1 = <&gpio185_pmx_idle &gpio185_cfg_idle>; }; }; diff --git a/drivers/staging/hikey9xx/gpu/Makefile b/drivers/staging/hikey9xx/gpu/Makefile index 9177c3006b14..16a708d7faec 100644 --- a/drivers/staging/hikey9xx/gpu/Makefile +++ b/drivers/staging/hikey9xx/gpu/Makefile @@ -5,5 +5,5 @@ kirin9xx-drm-y := kirin9xx_drm_drv.o \ kirin970_defs.o kirin960_defs.o \ kirin9xx_drm_overlay_utils.o -obj-$(CONFIG_DRM_HISI_KIRIN9XX) += kirin9xx-drm.o kirin9xx_pwm.o +obj-$(CONFIG_DRM_HISI_KIRIN9XX) += kirin9xx-drm.o obj-$(CONFIG_DRM_HISI_KIRIN9XX_DSI) += kirin9xx_dw_drm_dsi.o diff --git a/drivers/staging/hikey9xx/gpu/kirin9xx_pwm.c b/drivers/staging/hikey9xx/gpu/kirin9xx_pwm.c deleted file mode 100644 index d686664b8627..000000000000 --- a/drivers/staging/hikey9xx/gpu/kirin9xx_pwm.c +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2013-2014, Hisilicon Tech. Co., Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "kirin9xx_drm_dpe_utils.h" -#include "kirin9xx_fb_panel.h" -#include "kirin9xx_dw_dsi_reg.h" - -#include "kirin9xx_dpe.h" - -/* default pwm clk */ -#define DEFAULT_PWM_CLK_RATE (80 * 1000000L) - -static char __iomem *hisifd_pwm_base; -static char __iomem *hisi_peri_crg_base; -static struct clk *g_pwm_clk; -static struct platform_device *g_pwm_pdev; -static int g_pwm_on; - -static struct pinctrl_data pwmpctrl; - -static struct pinctrl_cmd_desc pwm_pinctrl_init_cmds[] = { - {DTYPE_PINCTRL_GET, &pwmpctrl, 0}, - {DTYPE_PINCTRL_STATE_GET, &pwmpctrl, DTYPE_PINCTRL_STATE_DEFAULT}, - {DTYPE_PINCTRL_STATE_GET, &pwmpctrl, DTYPE_PINCTRL_STATE_IDLE}, -}; - -static struct pinctrl_cmd_desc pwm_pinctrl_normal_cmds[] = { - {DTYPE_PINCTRL_SET, &pwmpctrl, DTYPE_PINCTRL_STATE_DEFAULT}, -}; - -static struct pinctrl_cmd_desc pwm_pinctrl_lowpower_cmds[] = { - {DTYPE_PINCTRL_SET, &pwmpctrl, DTYPE_PINCTRL_STATE_IDLE}, -}; - -static struct pinctrl_cmd_desc pwm_pinctrl_finit_cmds[] = { - {DTYPE_PINCTRL_PUT, &pwmpctrl, 0}, -}; - -#define PWM_LOCK_OFFSET (0x0000) -#define PWM_CTL_OFFSET (0X0004) -#define PWM_CFG_OFFSET (0x0008) -#define PWM_PR0_OFFSET (0x0100) -#define PWM_PR1_OFFSET (0x0104) -#define PWM_C0_MR_OFFSET (0x0300) -#define PWM_C0_MR0_OFFSET (0x0304) - -#define PWM_OUT_PRECISION (800) - -int pinctrl_cmds_tx(struct platform_device *pdev, struct pinctrl_cmd_desc *cmds, int cnt) -{ - int ret = 0; - - int i = 0; - struct pinctrl_cmd_desc *cm = NULL; - - cm = cmds; - - for (i = 0; i < cnt; i++) { - if (!cm) { - DRM_ERROR("cm is null! index=%d\n", i); - continue; - } - - if (cm->dtype == DTYPE_PINCTRL_GET) { - if (!pdev) { - DRM_ERROR("pdev is NULL"); - return -EINVAL; - } - cm->pctrl_data->p = devm_pinctrl_get(&pdev->dev); - if (IS_ERR(cm->pctrl_data->p)) { - ret = -1; - DRM_ERROR("failed to get p, index=%d!\n", i); - goto err; - } - } else if (cm->dtype == DTYPE_PINCTRL_STATE_GET) { - if (cm->mode == DTYPE_PINCTRL_STATE_DEFAULT) { - cm->pctrl_data->pinctrl_def = pinctrl_lookup_state(cm->pctrl_data->p, PINCTRL_STATE_DEFAULT); - if (IS_ERR(cm->pctrl_data->pinctrl_def)) { - ret = -1; - DRM_ERROR("failed to get pinctrl_def, index=%d!\n", i); - goto err; - } - } else if (cm->mode == DTYPE_PINCTRL_STATE_IDLE) { - cm->pctrl_data->pinctrl_idle = pinctrl_lookup_state(cm->pctrl_data->p, PINCTRL_STATE_IDLE); - if (IS_ERR(cm->pctrl_data->pinctrl_idle)) { - ret = -1; - DRM_ERROR("failed to get pinctrl_idle, index=%d!\n", i); - goto err; - } - } else { - ret = -1; - DRM_ERROR("unknown pinctrl type to get!\n"); - goto err; - } - } else if (cm->dtype == DTYPE_PINCTRL_SET) { - if (cm->mode == DTYPE_PINCTRL_STATE_DEFAULT) { - if (cm->pctrl_data->p && cm->pctrl_data->pinctrl_def) { - ret = pinctrl_select_state(cm->pctrl_data->p, cm->pctrl_data->pinctrl_def); - if (ret) { - DRM_ERROR("could not set this pin to default state!\n"); - ret = -1; - goto err; - } - } - } else if (cm->mode == DTYPE_PINCTRL_STATE_IDLE) { - if (cm->pctrl_data->p && cm->pctrl_data->pinctrl_idle) { - ret = pinctrl_select_state(cm->pctrl_data->p, cm->pctrl_data->pinctrl_idle); - if (ret) { - DRM_ERROR("could not set this pin to idle state!\n"); - ret = -1; - goto err; - } - } - } else { - ret = -1; - DRM_ERROR("unknown pinctrl type to set!\n"); - goto err; - } - } else if (cm->dtype == DTYPE_PINCTRL_PUT) { - if (cm->pctrl_data->p) - pinctrl_put(cm->pctrl_data->p); - } else { - DRM_ERROR("not supported command type!\n"); - ret = -1; - goto err; - } - - cm++; - } - - return 0; - -err: - return ret; -} - -int hisi_pwm_set_backlight(struct backlight_device *bl, uint32_t bl_level) -{ - char __iomem *pwm_base = NULL; - u32 bl_max = bl->props.max_brightness; - - pwm_base = hisifd_pwm_base; - if (!pwm_base) { - DRM_ERROR("pwm_base is null!\n"); - return -EINVAL; - } - - DRM_INFO("bl_level=%d.\n", bl_level); - - if (bl_max < 1) { - DRM_ERROR("bl_max(%d) is out of range!!", bl_max); - return -EINVAL; - } - - if (bl_level > bl_max) - bl_level = bl_max; - - bl_level = (bl_level * PWM_OUT_PRECISION) / bl_max; - - writel(0x1acce551, pwm_base + PWM_LOCK_OFFSET); - writel(0x0, pwm_base + PWM_CTL_OFFSET); - writel(0x2, pwm_base + PWM_CFG_OFFSET); - writel(0x1, pwm_base + PWM_PR0_OFFSET); - writel(0x2, pwm_base + PWM_PR1_OFFSET); - writel(0x1, pwm_base + PWM_CTL_OFFSET); - writel((PWM_OUT_PRECISION - 1), pwm_base + PWM_C0_MR_OFFSET); - writel(bl_level, pwm_base + PWM_C0_MR0_OFFSET); - - return 0; -} - -int hisi_pwm_on(void) -{ - struct clk *clk_tmp = NULL; - char __iomem *pwm_base = NULL; - char __iomem *peri_crg_base = NULL; - int ret = 0; - - DRM_INFO(" +.\n"); - - peri_crg_base = hisi_peri_crg_base; - if (!peri_crg_base) { - DRM_ERROR("peri_crg_base is NULL"); - return -EINVAL; - } - - pwm_base = hisifd_pwm_base; - if (!pwm_base) { - DRM_ERROR("pwm_base is null!\n"); - return -EINVAL; - } - - if (g_pwm_on == 1) - return 0; - - // dis-reset pwm - writel(0x1, peri_crg_base + PERRSTDIS2); - - clk_tmp = g_pwm_clk; - if (clk_tmp) { - ret = clk_prepare(clk_tmp); - if (ret) { - DRM_ERROR("dss_pwm_clk clk_prepare failed, error=%d!\n", ret); - return -EINVAL; - } - - ret = clk_enable(clk_tmp); - if (ret) { - DRM_ERROR("dss_pwm_clk clk_enable failed, error=%d!\n", ret); - return -EINVAL; - } - - DRM_INFO("dss_pwm_clk clk_enable succeeded, ret=%d!\n", ret); - } - - ret = pinctrl_cmds_tx(g_pwm_pdev, pwm_pinctrl_normal_cmds, - ARRAY_SIZE(pwm_pinctrl_normal_cmds)); - - //if enable PWM, please set IOMG_004 in IOC_AO module - //set IOMG_004: select PWM_OUT0 - - g_pwm_on = 1; - - return ret; -} - -int hisi_pwm_off(void) -{ - struct clk *clk_tmp = NULL; - char __iomem *pwm_base = NULL; - char __iomem *peri_crg_base = NULL; - int ret = 0; - - peri_crg_base = hisi_peri_crg_base; - if (!peri_crg_base) { - DRM_ERROR("peri_crg_base is NULL"); - return -EINVAL; - } - - pwm_base = hisifd_pwm_base; - if (!pwm_base) { - DRM_ERROR("pwm_base is null!\n"); - return -EINVAL; - } - - if (g_pwm_on == 0) - return 0; - - ret = pinctrl_cmds_tx(g_pwm_pdev, pwm_pinctrl_lowpower_cmds, - ARRAY_SIZE(pwm_pinctrl_lowpower_cmds)); - - clk_tmp = g_pwm_clk; - if (clk_tmp) { - clk_disable(clk_tmp); - clk_unprepare(clk_tmp); - } - - //reset pwm - writel(0x1, peri_crg_base + PERRSTEN2); - - g_pwm_on = 0; - - return ret; -} - -static int hisi_pwm_probe(struct platform_device *pdev) -{ - struct device_node *np = NULL; - int ret = 0; - - if (!pdev) { - DRM_ERROR("pdev is NULL"); - return -EINVAL; - } - - g_pwm_pdev = pdev; - - np = of_find_compatible_node(NULL, NULL, DTS_COMP_PWM_NAME); - if (!np) { - DRM_ERROR("NOT FOUND device node %s!\n", DTS_COMP_PWM_NAME); - ret = -ENXIO; - goto err_return; - } - - /* get pwm reg base */ - hisifd_pwm_base = of_iomap(np, 0); - if (!hisifd_pwm_base) { - DRM_ERROR("failed to get pwm_base resource.\n"); - return -ENXIO; - } - - /* get peri_crg_base */ - hisi_peri_crg_base = of_iomap(np, 1); - if (!hisi_peri_crg_base) { - DRM_ERROR("failed to get peri_crg_base resource.\n"); - return -ENXIO; - } - - /* pwm pinctrl init */ - ret = pinctrl_cmds_tx(pdev, pwm_pinctrl_init_cmds, - ARRAY_SIZE(pwm_pinctrl_init_cmds)); - if (ret != 0) { - DRM_ERROR("Init pwm pinctrl failed! ret=%d.\n", ret); - goto err_return; - } - - /* get pwm clk resource */ - g_pwm_clk = of_clk_get(np, 0); - if (IS_ERR(g_pwm_clk)) { - DRM_ERROR("%s clock not found: %d!\n", - np->name, (int)PTR_ERR(g_pwm_clk)); - ret = -ENXIO; - goto err_return; - } - - DRM_INFO("dss_pwm_clk:[%lu]->[%lu].\n", - DEFAULT_PWM_CLK_RATE, clk_get_rate(g_pwm_clk)); - - return 0; - -err_return: - return ret; -} - -static int hisi_pwm_remove(struct platform_device *pdev) -{ - struct clk *clk_tmp = NULL; - int ret = 0; - - ret = pinctrl_cmds_tx(pdev, pwm_pinctrl_finit_cmds, - ARRAY_SIZE(pwm_pinctrl_finit_cmds)); - - clk_tmp = g_pwm_clk; - if (clk_tmp) { - clk_put(clk_tmp); - clk_tmp = NULL; - } - - return ret; -} - -static const struct of_device_id hisi_pwm_match_table[] = { - { - .compatible = "hisilicon,hisipwm", - .data = NULL, - }, - {}, -}; -MODULE_DEVICE_TABLE(of, hisi_pwm_match_table); - -static struct platform_driver this_driver = { - .probe = hisi_pwm_probe, - .remove = hisi_pwm_remove, - .suspend = NULL, - .resume = NULL, - .shutdown = NULL, - .driver = { - .name = DEV_NAME_PWM, - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(hisi_pwm_match_table), - }, -}; - -static int __init hisi_pwm_init(void) -{ - int ret = 0; - - ret = platform_driver_register(&this_driver); - if (ret) { - DRM_ERROR("platform_driver_register failed, error=%d!\n", ret); - return ret; - } - - return ret; -} - -module_init(hisi_pwm_init); - -MODULE_AUTHOR("cailiwei "); -MODULE_AUTHOR("zhangxiubin "); -MODULE_DESCRIPTION("hisilicon Kirin SoCs' pwm driver"); -MODULE_LICENSE("GPL v2"); From patchwork Wed Aug 19 11:46:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 11723607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5902714F6 for ; Wed, 19 Aug 2020 11:47:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32C3220885 for ; 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Wed, 19 Aug 2020 11:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597837584; bh=0s3pmtILVSiuI77kiYarCgl3FUbdNZSJJENxk4HNs1c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XPoNKr4UNTqnAzpnnXX0ra1UVzx27ph7DOeQ7Lxg7GLPBzAJk+TZgZwglUIovjO2C Ox4rol4IoNMRrIBPrZttvUxhNAQeUcTpgYcArKxrbQqhv+FTLNfCzOp3uPn61YI22K D9se5drVv7bB9w8L2f0tMtFoW2knYrdC4sR1YRZo= Received: from mchehab by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1k8MXt-00EucG-PZ; Wed, 19 Aug 2020 13:46:21 +0200 From: Mauro Carvalho Chehab To: Greg Kroah-Hartman Subject: [PATCH 49/49] dt: display: Add binds for the DPE and DSI controller for Kirin 960/970 Date: Wed, 19 Aug 2020 13:46:17 +0200 Message-Id: <6471642f74779fecfc9d5e990d90f9475d8b32d4.1597833138.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_074625_404948_C050DA9C X-CRM114-Status: GOOD ( 20.70 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jesper Dangaard Brouer , Daniel Borkmann , Manivannan Sadhasivam , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, John Fastabend , linuxarm@huawei.com, dri-devel , Alexei Starovoitov , David Airlie , Rob Herring , John Stultz , Wei Xu , Daniel Vetter , netdev@vger.kernel.org, mauro.chehab@huawei.com, Jakub Kicinski , bpf@vger.kernel.org, "David S. Miller" , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add a description of the bindings used by Kirin 960/970 Display Serial Interface (DSI) controller and by its Display Engine (DPE). Signed-off-by: Mauro Carvalho Chehab --- .../display/hisilicon,hi3660-dpe.yaml | 99 +++++++++++++++++ .../display/hisilicon,hi3660-dsi.yaml | 102 ++++++++++++++++++ .../boot/dts/hisilicon/hikey970-drm.dtsi | 4 +- 3 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml create mode 100644 Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml new file mode 100644 index 000000000000..074997354417 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dpe.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/hisilicon,hi3660-dpe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon SPMI controller + +maintainers: + - Mauro Carvalho Chehab + +description: | + The HiSilicon Display Engine (DPE) s the display controller which grab + image data from memory, do composition, do post image processing, + generate RGB timing stream and transfer to DSI. + +properties: + $nodename: + pattern: "dpe@[0-9a-f]+" + + compatible: + enum: + - hisilicon,kirin960-dpe + - hisilicon,kirin970-dpe + + reg: + minItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + description: Clocks used by the ISP and by the display + + clock-names: + description: Names for the clock lines + + dma-coherent: true + + port: + type: object + description: A port node pointing to the display output endpoint. + + + iommu-info: + type: object + description: IOMMU address and size to be used by GPU + + properties: + start-addr: + const: start address for IOMMU + size: + const: size of the mapped region + +examples: + - | + dpe: dpe@e8600000 { + compatible = "hisilicon,kirin970-dpe"; + memory-region = <&drm_dma_reserved>; + reg = <0 0xE8600000 0 0xC0000>, + <0 0xFFF35000 0 0x1000>, + <0 0xFFF0A000 0 0x1000>, + <0 0xE8A09000 0 0x1000>, + <0 0xE86C0000 0 0x10000>, + <0 0xFFF31000 0 0x1000>, + <0 0xE87FF000 0 0x1000>; + + interrupts = <0 245 4>; + + clocks = <&media1_crg HI3670_ACLK_GATE_DSS>, + <&media1_crg HI3670_PCLK_GATE_DSS>, + <&media1_crg HI3670_CLK_GATE_EDC0>, + <&media1_crg HI3670_CLK_GATE_LDI0>, + <&media1_crg HI3670_CLK_GATE_DSS_AXI_MM>, + <&media1_crg HI3670_PCLK_GATE_MMBUF>, + <&crg_ctrl HI3670_PCLK_GATE_PCTRL>; + + clock-names = "aclk_dss", + "pclk_dss", + "clk_edc0", + "clk_ldi0", + "clk_dss_axi_mm", + "pclk_mmbuf", + "pclk_pctrl"; + + dma-coherent; + + port { + dpe_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + + iommu_info { + start-addr = <0x8000>; + size = <0xbfff8000>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml new file mode 100644 index 000000000000..2265267fc53d --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon,hi3660-dsi.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/hisilicon,hi3660-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon SPMI controller + +maintainers: + - Mauro Carvalho Chehab + +description: | + The HiSilicon Display Serial Interface (DSI) Host Controller for + Kirin 960 and 970 resides in the middle of display controller and + an external HDMI converter or panel. + +properties: + $nodename: + pattern: "dsi@[0-9a-f]+" + + compatible: + enum: + - hisilicon,kirin960-dsi + - hisilicon,kirin970-dsi + + reg: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 1 + maxItems: 8 + description: Clocks used by the ISP and by the display. + + clock-names: + description: Names for the clock lines. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + mux-gpio: + description: GPIO used by the mux. + + ports: + type: object + description: Display input and output ports. + +examples: + - | + dsi: dsi@e8601000 { + compatible = "hisilicon,kirin970-dsi"; + reg = <0 0xE8601000 0 0x7F000>, + <0 0xFFF35000 0 0x1000>, + <0 0xE8A09000 0 0x1000>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_REF>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY0_CFG>, + <&crg_ctrl HI3670_CLK_GATE_TXDPHY1_CFG>, + <&crg_ctrl HI3670_PCLK_GATE_DSI0>, + <&crg_ctrl HI3670_PCLK_GATE_DSI1>; + clock-names = "clk_txdphy0_ref", + "clk_txdphy1_ref", + "clk_txdphy0_cfg", + "clk_txdphy1_cfg", + "pclk_dsi0", + "pclk_dsi1"; + + #address-cells = <1>; + #size-cells = <0>; + mux-gpio = <&gpio25 7 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dpe_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + + dsi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel0_in>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi index 503c7c9425c8..5758d7d181e5 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-drm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 / { - dpe: dpe@E8600000 { + dpe: dpe@e8600000 { compatible = "hisilicon,kirin970-dpe"; memory-region = <&drm_dma_reserved>; // DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, PMCTRL, MEDIA_CRG @@ -44,7 +44,7 @@ iommu_info { }; }; - dsi: dsi@E8601000 { + dsi: dsi@e8601000 { compatible = "hisilicon,kirin970-dsi"; reg = <0 0xE8601000 0 0x7F000>, <0 0xFFF35000 0 0x1000>,