From patchwork Fri Aug 21 09:51:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Wu X-Patchwork-Id: 11728715 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B710722 for ; Fri, 21 Aug 2020 09:52:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72F9A207DF for ; Fri, 21 Aug 2020 09:52:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Bjuznksh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728473AbgHUJwS (ORCPT ); Fri, 21 Aug 2020 05:52:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728394AbgHUJwL (ORCPT ); Fri, 21 Aug 2020 05:52:11 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41D27C061386; Fri, 21 Aug 2020 02:52:11 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id m71so827587pfd.1; Fri, 21 Aug 2020 02:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BjfQ0AkfS3kL9HDk+Q/YejZuzmMLr9t4tJRavtedkMY=; b=Bjuznksh9MDo9roP54IrWhceOK8huD7RRJ5h4yKgGVYlHY3O1yKLO48hjItK3aQWBo t9n/GPp6ToDMoa4/Jl9/iUhbxHUNoBklfx/RO5XvmY6MY3Kpgsy/9Ywh4q6kqGEdocyI LOZNOEl4/qqrHQDPd3R3uicYNFGN5HE61D7PhzXLmw7SdpZKmk7X7rSVT+An+LMOFpD5 U/YaX85co6MLwEpanPiLgbCUGZpisGPvMbVY5L1uzS6hjRdzs9kOjNfhL93MlPSvJs8Z LKKjcdYQXYesDBiK7PnUM7wXgduly5bRi4gijVDZm3JdLtddn8SGtMUFJn9Pko0uzV9N zYSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BjfQ0AkfS3kL9HDk+Q/YejZuzmMLr9t4tJRavtedkMY=; b=oPumH5uHpzAPbb+nC7j8aH4kpvetFVdFYn4YSqAFZq9ICIFF+UlmcVoYPM7J2YbxaX 9I0vlPZzJF7o58llwAdyLrhxIN4DxMgJDpGVxdEG0/gvmxwygJe98XK2OVU3TyqGZNTr pV/5Q+XTZj5FMw91FCTQ5AnFNUta/r8rrXgVAqJfkFGJOYVC9lmAObnZWPp70Gnwedmp FkUACLuyi5eaDjqM8fIVBrIGY+iQv+Ew8KC9h5Ew+Bno+3xw15N5z/NoJ0r6DHL0XSs7 14chZz+1gYB2nFcHBP3C4aEjJXA98K64XEfPjr449aqekhl+QQJhUzpbEwqTQ7VwbiJc 8zbA== X-Gm-Message-State: AOAM533JnJPDT9TDVViKLbqCn+mSS1TTSY2qIWmPwyWmHdCOHrA4vW3f zaC98PDFcA5vRniGeKJaoAA= X-Google-Smtp-Source: ABdhPJy72m5E2eieegQbRpUTXdKnkGD4TcBdXW1zoWAtWQ3yqv1JKfgZKFshq97amCbcTD5CBdnGeA== X-Received: by 2002:aa7:8285:: with SMTP id s5mr1811034pfm.226.1598003530797; Fri, 21 Aug 2020 02:52:10 -0700 (PDT) Received: from sh05419pcu.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id d5sm1479828pjw.18.2020.08.21.02.52.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Aug 2020 02:52:10 -0700 (PDT) From: Hongtao Wu To: Lorenzo Pieralisi , Rob Herring Cc: Orson Zhai , Baolin Wang , Chunyan Zhang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Billows Wu Subject: [PATCH 1/2] dt-bindings: PCI: sprd: Document Unisoc PCIe RC host controller Date: Fri, 21 Aug 2020 17:51:48 +0800 Message-Id: <1598003509-27896-2-git-send-email-wuht06@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598003509-27896-1-git-send-email-wuht06@gmail.com> References: <1598003509-27896-1-git-send-email-wuht06@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Billows Wu This series adds PCIe bindings for Uisoc SoCs. This controller is based on DesignWare PCIe IP. Signed-off-by: Billows Wu --- .../devicetree/bindings/pci/sprd-pcie.yaml | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sprd-pcie.yaml -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/sprd-pcie.yaml b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml new file mode 100644 index 0000000..6eab4b8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sprd-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SoC PCIe Host Controller Device Tree Bindings + +maintainers: + - Billows Wu + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: "sprd-pcie.yaml#" + +properties: + compatible: + items: + - const: sprd,pcie + - const: sprd,pcie-ep + + reg: + minItems: 2 + maxItems: 3 + items: + - description: Controller control and status registers. + - description: PCIe shadow registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: cfg + + ranges: + maxItems: 2 + + num-lanes: + maxItems: 1 + description: Number of lanes to use for this port. + + num-ib-windows: + maxItems: 1 + description: Number of inbound windows to use for this port. + + num-ob-windows: + maxItems: 1 + description: Number of outbound windows to use for this port. + + bus-range: + description: Range of bus numbers associated with this controller. + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - num-lanes + - ranges + - bus-range + - interrupts + - interrupt-names + +examples: + - | + #include + pcie0@2b100000 { + compatible = "sprd,pcie", "snps,dw-pcie"; + reg = <0x0 0x2b100000 0x0 0x2000>, + <0x2 0x00000000 0x0 0x2000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x01000000 0x0 0x00000000 0x2 0x00002000 0x0 0x00010000 + 0x03000000 0x0 0x10000000 0x2 0x10000000 0x1 0xefffffff>; + bus-range = <0 15>; + num-lanes = <1>; + num-viewport = <8>; + interrupts = ; + interrupt-names = "msi"; + }; From patchwork Fri Aug 21 09:51:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Wu X-Patchwork-Id: 11728711 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5960B722 for ; Fri, 21 Aug 2020 09:52:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32FE3207DF for ; Fri, 21 Aug 2020 09:52:19 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 21 Aug 2020 02:52:13 -0700 (PDT) From: Hongtao Wu To: Lorenzo Pieralisi , Rob Herring Cc: Orson Zhai , Baolin Wang , Chunyan Zhang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Billows Wu Subject: [PATCH 2/2] PCI: sprd: Add support for Unisoc SoCs' PCIe controller Date: Fri, 21 Aug 2020 17:51:49 +0800 Message-Id: <1598003509-27896-3-git-send-email-wuht06@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598003509-27896-1-git-send-email-wuht06@gmail.com> References: <1598003509-27896-1-git-send-email-wuht06@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Billows Wu This series adds PCIe controller driver for Unisoc SoCs. This controller is based on DesignWare PCIe IP. Signed-off-by: Billows Wu --- drivers/pci/controller/dwc/Kconfig | 12 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-sprd.c | 256 +++++++++++++++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-sprd.c -- 2.7.4 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 044a376..d26ce94 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -311,4 +311,16 @@ config PCIE_AL required only for DT-based platforms. ACPI platforms with the Annapurna Labs PCIe controller don't need to enable this. +config PCIE_SPRD + tristate "Unisoc PCIe controller - RC mode" + depends on ARCH_SPRD + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Some Uisoc SoCs contain two PCIe controllers as RC: One is gen2, + and the other is gen3. While other Unisoc SoCs may have only one + PCIe controller which can be configured as an Endpoint(EP) or a Root + complex(RC). In order to enable host-specific features PCIE_SPRD must + be selected, which uses the Designware core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a751553..eb546e9 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PCI_MESON) += pci-meson.o obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o +obj-$(CONFIG_PCIE_SPRD) += pcie-sprd.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-sprd.c b/drivers/pci/controller/dwc/pcie-sprd.c new file mode 100644 index 0000000..cda812d --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-sprd.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Unisoc SoCs + * + * Copyright (C) 2020 Unisoc corporation. http://www.unisoc.com + * + * Author: Billows Wu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define NUM_OF_ARGS 5 + +struct sprd_pcie { + struct dw_pcie *pci; +}; + +struct sprd_pcie_of_data { + enum dw_pcie_device_mode mode; +}; + +static int sprd_pcie_establish_link(struct dw_pcie *pci) +{ + return 0; +} + +static const struct dw_pcie_ops sprd_pcie_ops = { + .start_link = sprd_pcie_establish_link, +}; + +int sprd_pcie_syscon_setting(struct platform_device *pdev, char *env) +{ + struct device_node *np = pdev->dev.of_node; + int i, count, err; + u32 type, delay, reg, mask, val, tmp_val; + struct of_phandle_args out_args; + struct regmap *iomap; + struct device *dev = &pdev->dev; + + if (!of_find_property(np, env, NULL)) { + dev_info(dev, "There isn't property %s in dts\n", env); + return 0; + } + + count = of_property_count_elems_of_size(np, env, + (NUM_OF_ARGS + 1) * sizeof(u32)); + dev_info(dev, "Property (%s) reg count is %d :\n", env, count); + + for (i = 0; i < count; i++) { + err = of_parse_phandle_with_fixed_args(np, env, NUM_OF_ARGS, + i, &out_args); + if (err < 0) + return err; + + type = out_args.args[0]; + delay = out_args.args[1]; + reg = out_args.args[2]; + mask = out_args.args[3]; + val = out_args.args[4]; + + iomap = syscon_node_to_regmap(out_args.np); + + switch (type) { + case 0: + regmap_update_bits(iomap, reg, mask, val); + break; + + case 1: + regmap_read(iomap, reg, &tmp_val); + tmp_val &= (~mask); + tmp_val |= (val & mask); + regmap_write(iomap, reg, tmp_val); + break; + default: + break; + } + + if (delay) + usleep_range(delay, delay + 10); + + regmap_read(iomap, reg, &tmp_val); + dev_dbg(&pdev->dev, + "%2d:reg[0x%8x] mask[0x%8x] val[0x%8x] result[0x%8x]\n", + i, reg, mask, val, tmp_val); + } + + return i; +} + +static void sprd_pcie_perst_assert(struct platform_device *pdev) +{ + sprd_pcie_syscon_setting(pdev, "sprd,pcie-perst-assert"); +} + +static void sprd_pcie_perst_deassert(struct platform_device *pdev) +{ + sprd_pcie_syscon_setting(pdev, "sprd,pcie-perst-deassert"); +} + +static int sprd_pcie_host_shutdown(struct platform_device *pdev) +{ + int ret; + struct device *dev = &pdev->dev; + + ret = sprd_pcie_syscon_setting(pdev, "sprd,pcie-shutdown-syscons"); + if (ret < 0) + dev_err(dev, + "Failed to set pcie shutdown syscons, return %d\n", + ret); + + sprd_pcie_perst_assert(pdev); + + ret = pm_runtime_put(&pdev->dev); + if (ret < 0) + dev_warn(&pdev->dev, + "Failed to put runtime,return %d\n", ret); + + return ret; +} + +static int sprd_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct platform_device *pdev = to_platform_device(pci->dev); + + sprd_pcie_perst_deassert(pdev); + + dw_pcie_setup_rc(pp); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + dw_pcie_msi_init(pp); + + if (dw_pcie_wait_for_link(pci)) { + dev_warn(pci->dev, + "pcie ep may has not been powered on yet\n"); + sprd_pcie_host_shutdown(pdev); + } + + return 0; +} + +static const struct dw_pcie_host_ops sprd_pcie_host_ops = { + .host_init = sprd_pcie_host_init, +}; + +static int sprd_add_pcie_port(struct platform_device *pdev) +{ + struct resource *res; + struct device *dev = &pdev->dev; + struct sprd_pcie *ctrl = platform_get_drvdata(pdev); + struct dw_pcie *pci = ctrl->pci; + struct pcie_port *pp = &pci->pp; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + if (!res) + return -EINVAL; + + pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!pci->dbi_base) + return -ENOMEM; + + pp->ops = &sprd_pcie_host_ops; + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + pp->msi_irq = platform_get_irq_byname(pdev, "msi"); + if (pp->msi_irq < 0) { + dev_err(dev, "Failed to get msi, return %d\n", + pp->msi_irq); + return pp->msi_irq; + } + } + + return dw_pcie_host_init(pp); +} + +static int sprd_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dw_pcie *pci; + struct sprd_pcie *ctrl; + int ret; + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev = dev; + pci->ops = &sprd_pcie_ops; + ctrl->pci = pci; + + platform_set_drvdata(pdev, ctrl); + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Fialed to get runtime sync, return %d\n", ret); + goto err_get_sync; + } + + ret = sprd_pcie_syscon_setting(pdev, "sprd,pcie-startup-syscons"); + if (ret < 0) { + dev_err(dev, "Failed to get pcie syscons, return %d\n", ret); + goto err_power_off; + } + + ret = sprd_add_pcie_port(pdev); + if (ret) + dev_warn(dev, "Failed to initialize RC controller\n"); + + return 0; + +err_power_off: + sprd_pcie_syscon_setting(pdev, "sprd,pcie-shutdown-syscons"); + +err_get_sync: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(dev); + + return ret; +} + +static const struct of_device_id sprd_pcie_of_match[] = { + { + .compatible = "sprd,pcie", + }, + {}, +}; + +static struct platform_driver sprd_pcie_driver = { + .probe = sprd_pcie_probe, + .driver = { + .name = "sprd-pcie", + .of_match_table = sprd_pcie_of_match, + }, +}; + +module_platform_driver(sprd_pcie_driver); + +MODULE_DESCRIPTION("Unisoc PCIe host controller driver"); +MODULE_LICENSE("GPL v2");