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Tue, 25 Aug 2020 16:06:15 +0000 Received: from localhost.localdomain (10.169.214.112) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2044.4 via Frontend Transport; Tue, 25 Aug 2020 16:06:12 +0000 From: Wei Chen To: , , CC: , , , , Subject: [PATCH v4 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Date: Tue, 25 Aug 2020 16:06:02 +0000 Message-ID: <20200825160603.32388-2-wei.chen@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200825160603.32388-1-wei.chen@arm.com> References: <20200825160603.32388-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a5a3d10f-1eb8-4f47-92d2-08d84910d76c X-MS-TrafficTypeDiagnostic: VI1PR08MB3566:|VE1PR08MB4879: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:7691;OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2020 16:06:35.4317 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5a3d10f-1eb8-4f47-92d2-08d84910d76c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4879 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports FP/SIMD or not. But currently, these two MACROs only consider value 0 of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs that support FP/SIMD and half-precision floating-point arithmetic, the ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64). For these CPUs, xen will treat them as no FP/SIMD support, the vfp_save/restore_state will not take effect. From the TRM documents of Cortex-A75/A76/N1, we know these CPUs support basic Advanced SIMD/FP and half-precision floating-point arithmetic. In this case, on N1/A76/A75 platforms, Xen will always miss the floating pointer registers save/restore. If different vCPUs are running on the same pCPU, the floating pointer registers will be corrupted randomly. This patch fixes Xen on these new cores. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis Reviewed-by: Julien Grall --- xen/include/asm-arm/cpufeature.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 674beb0353..10878ead8a 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -13,8 +13,8 @@ #define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1) #define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2) #define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1) -#define cpu_has_fp (boot_cpu_feature64(fp) == 0) -#define cpu_has_simd (boot_cpu_feature64(simd) == 0) +#define cpu_has_fp (boot_cpu_feature64(fp) < 8) +#define cpu_has_simd (boot_cpu_feature64(simd) < 8) #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) #endif From patchwork Tue Aug 25 16:06:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 11735943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D3EB13A4 for ; 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Tue, 25 Aug 2020 16:06:15 +0000 From: Wei Chen To: , , CC: , , , , Subject: [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Date: Tue, 25 Aug 2020 16:06:03 +0000 Message-ID: <20200825160603.32388-3-wei.chen@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200825160603.32388-1-wei.chen@arm.com> References: <20200825160603.32388-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 026d899e-faf5-4516-244f-08d84910d80d X-MS-TrafficTypeDiagnostic: PR3PR08MB5786:|VE1PR08MB4928: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8273;OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 8XuaOSnvuNiVdu4lThM5VeXiBwp61ABM6nLkiJCx0fLJ6FfMcAzu9Gd9D2KSN171KDp8uXrY1VwZ43QT4/SXpO+QFpJ8gO7NwhQLRXYNemPkkFPraZq0IO76sAillmTpx/5w/1Xsm/YovASZe5IEtTbOsJXsli3hQm0TWjWnsQEYpC2ykL4gy7O3hT6eoS9ENkxTp6dB08sEfh9WRZzFcD+NkNFzhtIwdcTC+Tu6BMV79pWGG+DGKxryDht2zvnhbJXRzkr7UTHFj5ZNBghEOoBIAU/Qmc/we5eyqRAYOXRBBegy5KStIOPx2HklKFDPmVnTwnG0aMJSK4ExS/oE6ktegCnC4oohRbYzzdVuK5vmdChGiSRVaGZLdclq+bdAme7LDq0UgWiRB1/7fSccGQ== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Currently, we exactly know the meaning of 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD features presented. If there is a value 0x2 bumped in the future, Xen behaviors for value <= 0x1 can also take effect. But what Xen done for value <= 0x1 may not always cover new value 0x2 required. We throw these messages to break the silence when Xen detected unknown FP/SIMD IDs to notice user to check. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis Acked-by: Julien Grall --- xen/arch/arm/setup.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 7968cee47d..6a31eca984 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -133,6 +133,18 @@ static void __init processor_id(void) cpu_has_simd ? " AdvancedSIMD" : "", cpu_has_gicv3 ? " GICv3-SysReg" : ""); + /* Warn user if we find unknown floating-point features */ + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) ) + printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, " + "this may result to corruption on the platform\n", + boot_cpu_feature64(fp)); + + /* Warn user if we find unknown AdvancedSIMD features */ + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) ) + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, " + "this may result to corruption on the platform\n", + boot_cpu_feature64(simd)); + printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n", boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]); printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",