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Mon, 31 Aug 2020 04:44:17 -0700 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 5D89D13C051A; Mon, 31 Aug 2020 17:18:44 +0530 (IST) From: Sai Pavan Boddu To: Peter Maydell , Richard Henderson , =?utf-8?q?=27Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9=27?= , Andrew Jones , Paolo Bonzini , =?utf-8?b?J0FsZXggQmVubsOpZSc=?= , Eric Auger , "'Edgar E . Iglesias'" Subject: [PATCH] target/arm: Configure number of pmu counters Date: Mon, 31 Aug 2020 17:18:42 +0530 Message-Id: <1598874522-5186-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: d18d1460-2b75-4686-5ce6-08d84da33225 X-MS-TrafficTypeDiagnostic: BYAPR02MB4933: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cA/wWCmE5Y1TE71E5fD2IFtXXLzxLDwLc4sMkDu+hTJFHQdSxYQ2OM8oePQedfQb62xLR6gcruMWoGLQR9Py1dvMO0koVywcOuDjiyVOktRD+EMHJW0i8EigP4KA7Jx7riuCdtKqZ8dj/gSNMGhD+oJLoZeACHWJzkpv/Ijj82bwTWdK0hpBvEfCZwKEBzMz5ATjD64ILCheilQ1Rjh/AB5eahsYjBBXbOC5pc99lq5QUIk9IhrHn/3LuTHjswAu9RJx+5wAiLoVMUgxv0MclBcHlhmYg1IkwdQ9qyRoADN7M8cIao3aS+WoBz3fg4Xd0kJQO29ji+UtsilFBYD7BGkDS2EOUBEznFjEB9ky5JQXjtGUZvYP7aIIpQX9yFKx4Ldx0kJU4833RCrmroGesY+PkwDYZkKQTJnEMDYS+Os= X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(396003)(136003)(376002)(346002)(39860400002)(46966005)(5660300002)(26005)(186003)(70586007)(70206006)(336012)(36756003)(426003)(2616005)(82310400002)(42186006)(8676002)(83380400001)(107886003)(6266002)(478600001)(356005)(2906002)(47076004)(6636002)(81166007)(110136005)(8936002)(82740400003)(316002)(4326008)(42866002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2020 11:44:18.9132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d18d1460-2b75-4686-5ce6-08d84da33225 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4933 Received-SPF: pass client-ip=40.107.236.61; envelope-from=saipava@xilinx.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/31 07:44:20 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: 11 X-Spam_score: 1.1 X-Spam_bar: + X-Spam_report: (1.1 / 5.0 requ) AC_FROM_MANY_DOTS=2.999, BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sai.pavan.boddu@xilinx.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Default the pmu counters to 4 and configure it a 6 for a53 cores. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 3 +++ target/arm/cpu64.c | 1 + target/arm/helper.c | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6b382fc..805a692 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1051,6 +1051,9 @@ static void arm_cpu_initfn(Object *obj) cpu->psci_version = 1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; + /* set number of pmu counters to 4 */ + cpu->pmcrn = 4; + if (tcg_enabled()) { cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ac857bd..3b47ba8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -879,6 +879,9 @@ struct ARMCPU { */ int32_t core_count; + /* Number of pmu counters */ + uint8_t pmcrn; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dd69618..76c879a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -190,6 +190,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + cpu->pmcrn = 6; } static void aarch64_a72_initfn(Object *obj) diff --git a/target/arm/helper.c b/target/arm/helper.c index 44d6666..4afbefb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6534,7 +6534,7 @@ static void define_pmu_regs(ARMCPU *cpu) * field as main ID register, and we implement four counters in * addition to the cycle count register. */ - unsigned int i, pmcrn = 4; + unsigned int i, pmcrn = cpu->pmcrn; ARMCPRegInfo pmcr = { .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .access = PL0_RW,