From patchwork Fri Sep 4 15:55:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F21092C for ; Fri, 4 Sep 2020 15:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60C0920791 for ; Fri, 4 Sep 2020 15:56:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="f327XpYN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726937AbgIDP4E (ORCPT ); Fri, 4 Sep 2020 11:56:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726314AbgIDPzR (ORCPT ); Fri, 4 Sep 2020 11:55:17 -0400 Received: from mail-qt1-x843.google.com (mail-qt1-x843.google.com [IPv6:2607:f8b0:4864:20::843]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB6FEC061245 for ; Fri, 4 Sep 2020 08:55:16 -0700 (PDT) Received: by mail-qt1-x843.google.com with SMTP id e5so4956254qth.5 for ; Fri, 04 Sep 2020 08:55:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gCgPYkIuen689JCGS9C+yWcxF9Wf5xvuT4fGLsIR6s4=; b=f327XpYNWc6l2rv9RF9YVwix3cQ2zUGItQvb76pIc9b0ZZkAec70KgXCmFe1JTlQPX H7KHWTKF4ebNKtJJmF+TbCugfIYbU2jdqDcwNT+/YNzahtv31duzVXAfMO+ObDXFwd4P NJ5GqDhX/siqbOaqP7g3+ksdGLNPEWZWR0vlJkfD9LmXJcMQbYIk12lmuxQGqDhU7/Ru LxHMs6d/rjNQ0a8rObQ1GjEBRFMA5GiRpv4/MQnxJWg66Oe7gn0saucFFtw97AyPcssA UqaSTYkqvvnVF+4ciJRWw3mDV3o3GWfTbonqPO/r1cRQVtr3SAYaixzOl3psh9evNe5u e5wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gCgPYkIuen689JCGS9C+yWcxF9Wf5xvuT4fGLsIR6s4=; b=VKq11yV2EFoDHTh0q9NF+ExHL/QTcW3BfVln1D0js+SdLBtK7ByM9I3++56Sw3bnMi XSDOXI8B+aPGeXgM3KcRlE/ucy/hm3t8S+IO7HVfWYwi81W2Tibc8rBvEbsTGxQB1hW5 gRjip3ExoKqyn4Kz3j18ztoxFb+2FnVGK97ABUHotuznCWjaoQFV9p7KOwdEarU3/O7C pbY+StubtwgeWl4Pnc58+BIK+pk5p8h4j2tm1oT8ZL4UaWmiy+oSpPr6gp82rf9l7x/e s1lJJSes+kMFqAJNiBvPGacAGo90mlj/Ji1IgBZjJfhdq0yEk31ohePM6YY1uuM7QCKT NiVw== X-Gm-Message-State: AOAM532gLhH2nMyHgZ33KHjpila9fFvIa6mCTzGRv/81q5UHuwCgtmR0 4jtDkFeOotdc5KqdHZgJMZ5z4A== X-Google-Smtp-Source: ABdhPJwQAqxRfEZO2Wpzgm/mVc29sreI4hBEc/PRL/deVoZlJprAw461csvwoALQd2PBInXlQ29TIQ== X-Received: by 2002:ac8:3933:: with SMTP id s48mr9112374qtb.294.1599234916004; Fri, 04 Sep 2020 08:55:16 -0700 (PDT) Received: from localhost.localdomain (ec2-34-197-84-77.compute-1.amazonaws.com. [34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:15 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 1/8] iommu/arm-smmu: Refactor context bank allocation Date: Fri, 4 Sep 2020 15:55:06 +0000 Message-Id: <20200904155513.282067-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Extract the conditional invocation of the platform defined alloc_context_bank() to a separate function to keep arm_smmu_init_domain_context() cleaner. Instead pass a reference to the arm_smmu_device as parameter to the call. Also remove the count parameter, as this can be read from the newly passed object. This allows us to not assign smmu_domain->smmu before attempting to allocate the context bank and as such we don't need to roll back this assignment on failure. Signed-off-by: Bjorn Andersson Reviewed-by: Jordan Crouse Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Note that this series applies ontop of: https://lore.kernel.org/linux-arm-msm/20200901164707.2645413-1-robdclark@gmail.com/ This could either go on its own, or be squashed with "[PATCH v16 14/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation" from Rob's series. Changes since v2: - New patch drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++-- drivers/iommu/arm/arm-smmu/arm-smmu.c | 23 ++++++++++++---------- drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 ++- 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 2aa6249050ff..0663d7d26908 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -91,9 +91,10 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, } static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, - struct device *dev, int start, int count) + struct arm_smmu_device *smmu, + struct device *dev, int start) { - struct arm_smmu_device *smmu = smmu_domain->smmu; + int count; /* * Assign context bank 0 to the GPU device so the GPU hardware can @@ -104,6 +105,7 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma count = 1; } else { start = 1; + count = smmu->num_context_banks; } return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index bbec5793faf8..e19d7bdc7674 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -623,6 +623,16 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } +static int arm_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, + struct device *dev, unsigned int start) +{ + if (smmu->impl && smmu->impl->alloc_context_bank) + return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); + + return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); +} + static int arm_smmu_init_domain_context(struct iommu_domain *domain, struct arm_smmu_device *smmu, struct device *dev) @@ -741,20 +751,13 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, goto out_unlock; } - smmu_domain->smmu = smmu; - - if (smmu->impl && smmu->impl->alloc_context_bank) - ret = smmu->impl->alloc_context_bank(smmu_domain, dev, - start, smmu->num_context_banks); - else - ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, - smmu->num_context_banks); - + ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); if (ret < 0) { - smmu_domain->smmu = NULL; goto out_unlock; } + smmu_domain->smmu = smmu; + cfg->cbndx = ret; if (smmu->version < ARM_SMMU_V2) { cfg->irptndx = atomic_inc_return(&smmu->irptndx); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 2df3a70a8a41..ddf2ca4c923d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -437,7 +437,8 @@ struct arm_smmu_impl { irqreturn_t (*global_fault)(int irq, void *dev); irqreturn_t (*context_fault)(int irq, void *dev); int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain, - struct device *dev, int start, int max); + struct arm_smmu_device *smmu, + struct device *dev, int start); }; #define INVALID_SMENDX -1 From patchwork Fri Sep 4 15:55:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757967 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 140BE15AB for ; Fri, 4 Sep 2020 15:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F09092083B for ; Fri, 4 Sep 2020 15:56:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CJgMpx43" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727081AbgIDP4D (ORCPT ); Fri, 4 Sep 2020 11:56:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726937AbgIDPzT (ORCPT ); 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[34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:16 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 2/8] iommu/arm-smmu: Delay modifying domain during init Date: Fri, 4 Sep 2020 15:55:07 +0000 Message-Id: <20200904155513.282067-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Delay modifications to the domain during arm_smmu_init_domain_context() until we've allocated a context bank. This will allow us to postpone the special handling of identity domains until the platform specific context bank allocator has been executed, in a later patch. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - New patch to allow us to rely on the impl specific alloc_context_bank(). drivers/iommu/arm/arm-smmu/arm-smmu.c | 40 +++++++++++++++------------ 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index e19d7bdc7674..add2e1807e21 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -645,6 +645,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_cfg *cfg = &smmu_domain->cfg; irqreturn_t (*context_fault)(int irq, void *dev); + struct arm_smmu_cfg new_cfg = *cfg; + enum arm_smmu_domain_stage new_stage = smmu_domain->stage; + const struct iommu_flush_ops *flush_ops; mutex_lock(&smmu_domain->init_mutex); if (smmu_domain->smmu) @@ -675,9 +678,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, * Note that you can't actually request stage-2 mappings. */ if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) - smmu_domain->stage = ARM_SMMU_DOMAIN_S2; + new_stage = ARM_SMMU_DOMAIN_S2; if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) - smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + new_stage = ARM_SMMU_DOMAIN_S1; /* * Choosing a suitable context format is even more fiddly. Until we @@ -688,32 +691,32 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, * support to be a superset of AArch32 support... */ if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) - cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L; + new_cfg.fmt = ARM_SMMU_CTX_FMT_AARCH32_L; if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) && !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) && (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && - (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)) - cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S; - if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) && + (new_stage == ARM_SMMU_DOMAIN_S1)) + new_cfg.fmt = ARM_SMMU_CTX_FMT_AARCH32_S; + if ((IS_ENABLED(CONFIG_64BIT) || new_cfg.fmt == ARM_SMMU_CTX_FMT_NONE) && (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | ARM_SMMU_FEAT_FMT_AARCH64_16K | ARM_SMMU_FEAT_FMT_AARCH64_4K))) - cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64; + new_cfg.fmt = ARM_SMMU_CTX_FMT_AARCH64; - if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) { + if (new_cfg.fmt == ARM_SMMU_CTX_FMT_NONE) { ret = -EINVAL; goto out_unlock; } - switch (smmu_domain->stage) { + switch (new_stage) { case ARM_SMMU_DOMAIN_S1: - cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; + new_cfg.cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; start = smmu->num_s2_context_banks; ias = smmu->va_size; oas = smmu->ipa_size; - if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { + if (new_cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64) { fmt = ARM_64_LPAE_S1; - } else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) { + } else if (new_cfg.fmt == ARM_SMMU_CTX_FMT_AARCH32_L) { fmt = ARM_32_LPAE_S1; ias = min(ias, 32UL); oas = min(oas, 40UL); @@ -722,7 +725,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ias = min(ias, 32UL); oas = min(oas, 32UL); } - smmu_domain->flush_ops = &arm_smmu_s1_tlb_ops; + flush_ops = &arm_smmu_s1_tlb_ops; break; case ARM_SMMU_DOMAIN_NESTED: /* @@ -730,11 +733,11 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, * involved. */ case ARM_SMMU_DOMAIN_S2: - cfg->cbar = CBAR_TYPE_S2_TRANS; + new_cfg.cbar = CBAR_TYPE_S2_TRANS; start = 0; ias = smmu->ipa_size; oas = smmu->pa_size; - if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { + if (new_cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64) { fmt = ARM_64_LPAE_S2; } else { fmt = ARM_32_LPAE_S2; @@ -742,9 +745,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, oas = min(oas, 40UL); } if (smmu->version == ARM_SMMU_V2) - smmu_domain->flush_ops = &arm_smmu_s2_tlb_ops_v2; + flush_ops = &arm_smmu_s2_tlb_ops_v2; else - smmu_domain->flush_ops = &arm_smmu_s2_tlb_ops_v1; + flush_ops = &arm_smmu_s2_tlb_ops_v1; break; default: ret = -EINVAL; @@ -757,6 +760,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, } smmu_domain->smmu = smmu; + smmu_domain->cfg = new_cfg; + smmu_domain->stage = new_stage; + smmu_domain->flush_ops = flush_ops; cfg->cbndx = ret; if (smmu->version < ARM_SMMU_V2) { From patchwork Fri Sep 4 15:55:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757965 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7A2D92C for ; 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[34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:17 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 3/8] iommu/arm-smmu: Consult context bank allocator for identify domains Date: Fri, 4 Sep 2020 15:55:08 +0000 Message-Id: <20200904155513.282067-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For implementations of the ARM SMMU where stream mappings of bypass type are prohibited identity domains can be implemented by using context banks with translation disabled. Postpone the decision to skip allocating a context bank until the implementation specific context bank allocator has been consulted and if it decides to use a context bank for the identity map, don't enable translation (i.e. omit ARM_SMMU_SCTLR_M). Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - Tie this to alloc_context_bank rather than carrying a Qualcomm specific quirk in the generic code. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++++ drivers/iommu/arm/arm-smmu/arm-smmu.c | 23 +++++++++++++++------- drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 0663d7d26908..229fc8ff8cea 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -94,8 +94,12 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma struct arm_smmu_device *smmu, struct device *dev, int start) { + struct iommu_domain *domain = &smmu_domain->domain; int count; + if (domain->type == IOMMU_DOMAIN_IDENTITY) + return ARM_SMMU_CBNDX_BYPASS; + /* * Assign context bank 0 to the GPU device so the GPU hardware can * switch pagetables diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index add2e1807e21..eb5c6ca5c138 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -611,7 +611,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) /* SCTLR */ reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | ARM_SMMU_SCTLR_AFE | - ARM_SMMU_SCTLR_TRE | ARM_SMMU_SCTLR_M; + ARM_SMMU_SCTLR_TRE; + if (cfg->m) + reg |= ARM_SMMU_SCTLR_M; if (stage1) reg |= ARM_SMMU_SCTLR_S1_ASIDPNE; if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) @@ -627,9 +629,14 @@ static int arm_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, struct device *dev, unsigned int start) { + struct iommu_domain *domain = &smmu_domain->domain; + if (smmu->impl && smmu->impl->alloc_context_bank) return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); + if (domain->type == IOMMU_DOMAIN_IDENTITY) + return ARM_SMMU_CBNDX_BYPASS; + return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); } @@ -653,12 +660,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, if (smmu_domain->smmu) goto out_unlock; - if (domain->type == IOMMU_DOMAIN_IDENTITY) { - smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; - smmu_domain->smmu = smmu; - goto out_unlock; - } - /* * Mapping the requested stage onto what we support is surprisingly * complicated, mainly because the spec allows S1+S2 SMMUs without @@ -757,6 +758,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); if (ret < 0) { goto out_unlock; + } else if (ret == ARM_SMMU_CBNDX_BYPASS) { + smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; + smmu_domain->smmu = smmu; + goto out_unlock; } smmu_domain->smmu = smmu; @@ -813,6 +818,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, domain->geometry.force_aperture = true; + /* Enable translation for non-identity context banks */ + if (domain->type != IOMMU_DOMAIN_IDENTITY) + cfg->m = true; + /* Initialise the context bank with our page table cfg */ arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); arm_smmu_write_context_bank(smmu, cfg->cbndx); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index ddf2ca4c923d..235d9a3a6ab6 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -243,6 +243,8 @@ enum arm_smmu_cbar_type { #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ #define TLB_SPIN_COUNT 10 +#define ARM_SMMU_CBNDX_BYPASS 0xffff + /* Shared driver definitions */ enum arm_smmu_arch_version { ARM_SMMU_V1, @@ -346,6 +348,7 @@ struct arm_smmu_cfg { u32 sctlr_clr; /* bits to mask in SCTLR */ enum arm_smmu_cbar_type cbar; enum arm_smmu_context_fmt fmt; + bool m; }; #define ARM_SMMU_INVALID_IRPTNDX 0xff From patchwork Fri Sep 4 15:55:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757963 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95DC692C for ; Fri, 4 Sep 2020 15:56:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7901B2074D for ; Fri, 4 Sep 2020 15:56:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SJb3QhpY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726658AbgIDP4C (ORCPT ); Fri, 4 Sep 2020 11:56:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726968AbgIDPz0 (ORCPT ); Fri, 4 Sep 2020 11:55:26 -0400 Received: from mail-qt1-x842.google.com (mail-qt1-x842.google.com [IPv6:2607:f8b0:4864:20::842]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ADEAC06125F for ; Fri, 4 Sep 2020 08:55:22 -0700 (PDT) Received: by mail-qt1-x842.google.com with SMTP id v54so4956858qtj.7 for ; Fri, 04 Sep 2020 08:55:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A7svwNgsY0UiMpV566sgNDGzXgT7VfisHtnxe6fo6Bo=; b=SJb3QhpYN6eU3JoTjsYO9t+QvUwc0b/xpfl5OAl/hynvIxgP9pQtQGZ7Q8P6XbdYOx 4ZmHDqCeABKsnyHLKLa/r1yj5s7wu0jme98WGPofmclJAqP1x8v1Qtsto93CKB8eFPbS d0rLzoytt+cTrw2VjSrbaM+Jqq9LKRqgmjXUemY119lVYuf68vDkVWFjJVhE+nfRUonE c+jT35sndJqqYDxgbHkVUFha3/taxEbjypD0TJEBf074vc1FB/fhvmH75GtEaBIZeTux WPHSblA16beNt6kLF9KBDd0tdQPNYaE9UaVzy8GYZnTEREbL71aqBcNgXIlp/WpxPsOV eUBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A7svwNgsY0UiMpV566sgNDGzXgT7VfisHtnxe6fo6Bo=; b=VjFoW6fcgyy/SG9Mb8ICbQZdUvpjSWevdRU1LAFgV7NGMQC4IKtK+StO1Y8vbJlKnm MYhrMS3sicAhmOkV8qy0Xfllxx42dBoJetTPpytRZ5i+mxQ61wGi0A2v+Bq+r+7Np0/V fKoP96AvnnfTStyx3WdPZNja5OXVtiJAzu4a771f799woFpDSsFMMuym1Sx5VS3IRN6c 685m2sAwBjz5ZY47Ab2j67DOJRez1Q9SueLL4TkUkd8/fxqUMr6Pm8pzkGXAsKCwYKzD 4YBgDhwKb8vEDY4wuZzy9itNIjo0kgh5eNzUxTdBqoMUU2QfJq1WC56+JV+aajz+A26Z XWHw== X-Gm-Message-State: AOAM532CTk+yqr1F0ubRE+x00Nug7PkJSq5AHqGk9Ca+rAG9U+Onsnat cQ3VNgZkrsU6wjUBKvfcvXWTbw== X-Google-Smtp-Source: ABdhPJw7ASxjDOGw6iPxO7Q3Ca/q5gyDB0Ac6+j7ID3GwnYiQlbkA7Cf3QrRkFvCmJF9BhJscynS1w== X-Received: by 2002:ac8:7145:: with SMTP id h5mr9707917qtp.110.1599234919674; Fri, 04 Sep 2020 08:55:19 -0700 (PDT) Received: from localhost.localdomain (ec2-34-197-84-77.compute-1.amazonaws.com. [34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:18 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 4/8] iommu/arm-smmu-qcom: Emulate bypass by using context banks Date: Fri, 4 Sep 2020 15:55:09 +0000 Message-Id: <20200904155513.282067-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some firmware found on various Qualcomm platforms traps writes to S2CR of type BYPASS and writes FAULT into the register. In particular, this prevents us from marking the streams for the display controller as BYPASS to allow continued scanout of the screen through the initialization of the ARM SMMU. This adds a Qualcomm specific cfg_probe function, which probes for the broken behavior of the S2CR registers and implements a custom alloc_context_bank() that when necessary allocates a context bank (without translation) for these domains as well. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - Move quirk from arm_smmudevice to qcom_smmu, as we localize the quirk handling to the Qualcomm specific implemntation. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 229fc8ff8cea..284761a1cd8e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -11,8 +11,14 @@ struct qcom_smmu { struct arm_smmu_device smmu; + bool bypass_broken; }; +static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) +{ + return container_of(smmu, struct qcom_smmu, smmu); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -162,6 +168,50 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { } }; +static int qcom_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, + struct device *dev, int start) +{ + struct iommu_domain *domain = &smmu_domain->domain; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + + /* Keep identity domains as bypass, unless bypass is broken */ + if (domain->type == IOMMU_DOMAIN_IDENTITY && !qsmmu->bypass_broken) + return ARM_SMMU_CBNDX_BYPASS; + + /* + * The identity domain to emulate bypass is the only domain without a + * dev, use the last context bank for this to avoid collisions with + * active contexts during initialization. + */ + if (!dev) + start = smmu->num_context_banks - 1; + + return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); +} + +static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) +{ + unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + u32 reg; + + /* + * With some firmware writes to S2CR of type FAULT are ignored, and + * writing BYPASS will end up as FAULT in the register. Perform a write + * to S2CR to detect if this is the case with the current firmware. + */ + reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); + arm_smmu_gr0_write(smmu, last_s2cr, reg); + reg = arm_smmu_gr0_read(smmu, last_s2cr); + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + qsmmu->bypass_broken = true; + + return 0; +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -200,6 +250,8 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) } static const struct arm_smmu_impl qcom_smmu_impl = { + .alloc_context_bank = qcom_smmu_alloc_context_bank, + .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, }; From patchwork Fri Sep 4 15:55:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABB1415AB for ; Fri, 4 Sep 2020 15:55:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91CF520770 for ; Fri, 4 Sep 2020 15:55:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nq7Yq52d" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726407AbgIDPzq (ORCPT ); Fri, 4 Sep 2020 11:55:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726947AbgIDPz0 (ORCPT ); Fri, 4 Sep 2020 11:55:26 -0400 Received: from mail-qt1-x844.google.com (mail-qt1-x844.google.com [IPv6:2607:f8b0:4864:20::844]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0F68C06125E for ; Fri, 4 Sep 2020 08:55:21 -0700 (PDT) Received: by mail-qt1-x844.google.com with SMTP id 92so4957328qtb.6 for ; Fri, 04 Sep 2020 08:55:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2fCr1AJs9wuitAEKSrgAGHFGKqH8nNlJ97BjXbXmjcA=; b=nq7Yq52dWK2MdT4FH7gxEZp0TjsJOGIfGdo6BK1+4OqJeoDIhKTf2aDFJDTv6cwKiL AAfJNraihxLVh8bWslR94j/0QKdKlYNtwIv3yMrxjDSCQOWEIxYc6ZiE65lUItOWUTtY BqFB1frX+GcyJ5SqFnJy0mLNzYc7wuu3R+iYFenJhV6MSs9oxnxjXrbEGZ1RDpM5GY+T y8WqyyGYcT8oYzHDGnZ8tQ7tfYTprXqknoa5mg/+T0r8ub6dJ9lD13U53ryGD9+UKow6 LAJ62Z/mLSjcPYmkMHcOGBIr5g7C3xlrml3u8u7TkDz6TWwCAA8+9cceeXtB6w+uWVVB vqhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2fCr1AJs9wuitAEKSrgAGHFGKqH8nNlJ97BjXbXmjcA=; b=FSZFHlRzWUIm6lQkAVB+c6ITrpR5lwf6ne4lR64ajJsbMj43IntV1R0BaHOC8E4Ke4 fsKGm8TmhIONFoNXFHf9ebbtw1c2L3Zp7c5unO+s+Q5nf2BmKU+o+gTw7M2RUwrbcvPG XICdW56pZuhfSYETvp/VKbXKNU3Z8019RHjK+/hwu0omB4+VsxQ6kREdY5wo7BCod6DI UvRZnx7orbgQ2t0VyQCQGIWxnXnjKZL5ANQVFrrbDUTfazgZCko4Cn+HbIiLXORT33Ij vzFPBayryZ8o0wpbbEj/uwmIJqLXKy+nmE9cvzDi+HQ6N/BJf39o/mvoGybE466HNe3I Ac9A== X-Gm-Message-State: AOAM533Fxf14JcEiZyQYJEQcAGp/rB7/FRY2aNA0d7qgz3SgfYPQDKng +mMEtYXik16rV5qKhcK1xm/KMg== X-Google-Smtp-Source: ABdhPJx6yG/QL52OZ4xkujRCTRW3+fj5Lott15EzPUVbvzCJ+ggkUIXMR0Jjrj7i70Ud68y/ORLM9w== X-Received: by 2002:ac8:66d3:: with SMTP id m19mr9426297qtp.276.1599234920832; Fri, 04 Sep 2020 08:55:20 -0700 (PDT) Received: from localhost.localdomain (ec2-34-197-84-77.compute-1.amazonaws.com. [34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:20 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 5/8] iommu/arm-smmu-qcom: Consistently initialize stream mappings Date: Fri, 4 Sep 2020 15:55:10 +0000 Message-Id: <20200904155513.282067-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Firmware that traps writes to S2CR to translate BYPASS into FAULT also ignores writes of type FAULT. As such booting with "disable_bypass" set will result in all S2CR registers left as configured by the bootloader. This has been seen to result in indeterministic results, as these mappings might linger and reference context banks that Linux is reconfiguring. Use the fact that BYPASS writes result in FAULT type to force all stream mappings to FAULT. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - None drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 284761a1cd8e..70a1eaa52e14 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -195,6 +195,7 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); u32 reg; + int i; /* * With some firmware writes to S2CR of type FAULT are ignored, and @@ -206,9 +207,24 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); arm_smmu_gr0_write(smmu, last_s2cr, reg); reg = arm_smmu_gr0_read(smmu, last_s2cr); - if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { qsmmu->bypass_broken = true; + /* + * With firmware ignoring writes of type FAULT, booting the + * Linux kernel with disable_bypass disabled (i.e. "enable + * bypass") the initialization during probe will leave mappings + * in an inconsistent state. Avoid this by configuring all + * S2CRs to BYPASS. + */ + for (i = 0; i < smmu->num_mapping_groups; i++) { + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].count = 0; + } + } + return 0; } From patchwork Fri Sep 4 15:55:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757961 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D977992C for ; Fri, 4 Sep 2020 15:56:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE23C20772 for ; Fri, 4 Sep 2020 15:56:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tb1Sd+n9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726441AbgIDPzs (ORCPT ); Fri, 4 Sep 2020 11:55:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726971AbgIDPz0 (ORCPT ); Fri, 4 Sep 2020 11:55:26 -0400 Received: from mail-qt1-x842.google.com (mail-qt1-x842.google.com [IPv6:2607:f8b0:4864:20::842]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B20DBC061261 for ; Fri, 4 Sep 2020 08:55:22 -0700 (PDT) Received: by mail-qt1-x842.google.com with SMTP id e7so4927724qtj.11 for ; Fri, 04 Sep 2020 08:55:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ls6xTeazp01VU5rx1tZcn8CZ6m3ZwOm0FhCvNs4H/UM=; b=tb1Sd+n9qybC0+ro/HdiC+RBRiJc3INwSffhtqG6iMH+37s6uZXFul1N9db1cLf0O+ W0rjcAJiucucmVQfVxG2MUkMAVBzL72kxYXPDM94Y8Eog3yqNAhbIBZ0SvhdqCqHjDss eqJnjUevNWz0I2ajfvSEgBRETGT0byopb7rb3HjelVEJIa/NYG7qIZZfDuUsq9UT8H2o wmlglYCueMqRUyXl0caryl5xIGgDggZeBNuaZUM8AtvG0YPJM0pCBnwyWbzDQmzoIDUC 8377oUebGf4yS6DRCQMoNRh9frdfOYrnjbWjR3K67Znyzlh8ybqe7mNP7I9znqOGTQSk sGjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ls6xTeazp01VU5rx1tZcn8CZ6m3ZwOm0FhCvNs4H/UM=; b=HDJYyDgs+8gUXj8VHaKl2oEvGb57ZDpFejdKU+yuFKw4fKkUB1cfWiuBtr2R/sMRjk GKe113eod/mYek28+6EGZyGCuM0d0imZMQx1qZUOopKYDPAJZtPOwdpGzwchUe5HJRHO N9Z2qLpKjMZhj9B+dcCtHCitPmFWGgZwbc0Q9D7daydrzgXwf3X4dfci4FQD9DUs4/8C 7FZ5nGai61spj25z2/AF+cL+ZFzFhC2l6w71GXwKlOGsWUy1XF8P87Suk6jjaLfH+oZV olhB6W+GjHu5Lnyijx+7RdYwnXXJebhajlOvDzJ6J2oMsynxq1s8xxe3gqEEJVYi8g/q mc4g== X-Gm-Message-State: AOAM532o3t3ySVuTiit1lyU0+e8x9aYZ9fgeOmDyY6SO8Z+DiGLuybIM STlXa5Clg7bMw9KHNjB0v3rnqQ== X-Google-Smtp-Source: ABdhPJyL88SwYtdr8vsyF/Q0nFNgzaGMkmnx++yP3wUNifIJQkEY1cF7fewzAafVU/vEqfUIMi+MHg== X-Received: by 2002:ac8:17af:: with SMTP id o44mr9239269qtj.343.1599234921881; Fri, 04 Sep 2020 08:55:21 -0700 (PDT) Received: from localhost.localdomain (ec2-34-197-84-77.compute-1.amazonaws.com. [34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:21 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 6/8] iommu/arm-smmu: Add impl hook for inherit boot mappings Date: Fri, 4 Sep 2020 15:55:11 +0000 Message-Id: <20200904155513.282067-7-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a new operation to allow platform implementations to inherit any stream mappings from the boot loader. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - New patch/interface drivers/iommu/arm/arm-smmu/arm-smmu.c | 11 ++++++----- drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 ++++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index eb5c6ca5c138..4c4d302cd747 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -85,11 +85,6 @@ static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) pm_runtime_put_autosuspend(smmu->dev); } -static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) -{ - return container_of(dom, struct arm_smmu_domain, domain); -} - static struct platform_driver arm_smmu_driver; static struct iommu_ops arm_smmu_ops; @@ -2188,6 +2183,12 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + if (smmu->impl->inherit_mappings) { + err = smmu->impl->inherit_mappings(smmu); + if (err) + return err; + } + if (smmu->version == ARM_SMMU_V2) { if (smmu->num_context_banks > smmu->num_context_irqs) { dev_err(dev, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 235d9a3a6ab6..f58164976e74 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -378,6 +378,11 @@ struct arm_smmu_domain { struct iommu_domain domain; }; +static inline struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) +{ + return container_of(dom, struct arm_smmu_domain, domain); +} + struct arm_smmu_master_cfg { struct arm_smmu_device *smmu; s16 smendx[]; @@ -442,6 +447,7 @@ struct arm_smmu_impl { int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, struct device *dev, int start); + int (*inherit_mappings)(struct arm_smmu_device *smmu); }; #define INVALID_SMENDX -1 From patchwork Fri Sep 4 15:55:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757955 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2636C92C for ; Fri, 4 Sep 2020 15:55:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C8872074D for ; Fri, 4 Sep 2020 15:55:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fH/8s/Vs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726947AbgIDPzt (ORCPT ); Fri, 4 Sep 2020 11:55:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726979AbgIDPz0 (ORCPT ); Fri, 4 Sep 2020 11:55:26 -0400 Received: from mail-qv1-xf41.google.com (mail-qv1-xf41.google.com [IPv6:2607:f8b0:4864:20::f41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3504C061262 for ; Fri, 4 Sep 2020 08:55:23 -0700 (PDT) Received: by mail-qv1-xf41.google.com with SMTP id f11so3243602qvw.3 for ; Fri, 04 Sep 2020 08:55:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I9v8itQxrG/5qOmlIkuGPstFjTonnbsCxHmLWx5pBPk=; b=fH/8s/VsjUJd9NSfQnY9KSqjr01isFkiTOEHv966Pm+qJr0SntP+xw7DkVPurY+FVA TGhOoJlnm9Ues2qE+3G7rkDWz7QaZWbR3ioFcET9S2eEFANNMRSLMlEwWT+67pEu3h/J gtFEX/W6HDjTk/bNacLk+NKv/yYQfcg4gHrZ8cvLLQd7heB4VMYFsmq5HuYBHzojcJzM jvbXrNuQYord9V5/QeTX2bg15dsqvN7uIXH2fypYBVmveFk3IlBSq5h0rr0SsYd92wbL r3AXp+pONiHH4M+LMJeGIBSd2WYLFWvUSPInCsoZgV6fJqA9+OEe5uEsFaU2oP25C6v1 PfpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I9v8itQxrG/5qOmlIkuGPstFjTonnbsCxHmLWx5pBPk=; b=cxHMezF7XWFjF+yfaZU9Vsjokttn7Xfj5bLZ8eDfFRFPpFgnjEwcEmSHqTKPEKW22v C86PRX6obUI2a+BHbqrYF5k+ZZJ9+tHIAAy0e4XOId0wms/nMdpd2XSZJyP53gMfIr/G WW5pKxU+obN5z9YWNxe28NrIysNfhNhVNVvb4dbOYNU+0WqdpnZIwjprm0YYP1aNJqOI yYiuNhMc3Odxt2Wym1QSpm4RDtO7JO0aDQdxIboh6phINBJyHUKm2EmGmYydndDp89pw xB0H081g4Xyupuo35mzPn242w0rQQB6rsV0wUmkHeaiflW3AgFesNxRDuSGF9RwgnXR/ 0Eqw== X-Gm-Message-State: AOAM530vMGAci10MPi5y94lhrB9EDTcsH0ZGjwFE7Y3JWyobcXthqkIc LC2twQH5glTSox9Y1E3Bi3G3wA== X-Google-Smtp-Source: ABdhPJxQteuxg6Yjoj7fVR6WxdpZueTzVWR2/XBC+gGtJOSWv7p5AUuXED5I8jk4ofSy9cwnePazOA== X-Received: by 2002:a0c:c988:: with SMTP id b8mr7690156qvk.192.1599234922927; Fri, 04 Sep 2020 08:55:22 -0700 (PDT) Received: from localhost.localdomain (ec2-34-197-84-77.compute-1.amazonaws.com. [34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:22 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 7/8] iommu/arm-smmu: Provide helper for allocating identity domain Date: Fri, 4 Sep 2020 15:55:12 +0000 Message-Id: <20200904155513.282067-8-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some platform implementations needs to be able to allocate a domain for emulating identity mappings using a context bank without translation. Provide a helper function to allocate such a domain. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - Extracted from previous arm_smmu_setup_identity() implementation drivers/iommu/arm/arm-smmu/arm-smmu.c | 25 +++++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 4c4d302cd747..3c06146dfdb9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1924,6 +1924,31 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) return 0; } +struct iommu_domain *arm_smmu_alloc_identity_domain(struct arm_smmu_device *smmu) +{ + struct iommu_domain *identity; + int ret; + + /* Create a IDENTITY domain to use for all inherited streams */ + identity = arm_smmu_domain_alloc(IOMMU_DOMAIN_IDENTITY); + if (!identity) { + dev_err(smmu->dev, "failed to create identity domain\n"); + return ERR_PTR(-ENOMEM); + } + + identity->pgsize_bitmap = smmu->pgsize_bitmap; + identity->type = IOMMU_DOMAIN_IDENTITY; + identity->ops = &arm_smmu_ops; + + ret = arm_smmu_init_domain_context(identity, smmu, NULL); + if (ret < 0) { + dev_err(smmu->dev, "failed to initialize identity domain: %d\n", ret); + return ERR_PTR(ret); + } + + return identity; +} + struct arm_smmu_match_data { enum arm_smmu_arch_version version; enum arm_smmu_implementation model; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index f58164976e74..fbdf3d7ca70d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -537,4 +537,6 @@ struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); +struct iommu_domain *arm_smmu_alloc_identity_domain(struct arm_smmu_device *smmu); + #endif /* _ARM_SMMU_H */ From patchwork Fri Sep 4 15:55:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11757951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 524CD14EB for ; Fri, 4 Sep 2020 15:55:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3447820770 for ; Fri, 4 Sep 2020 15:55:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="e29uwL+E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726114AbgIDPzq (ORCPT ); Fri, 4 Sep 2020 11:55:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727004AbgIDPz0 (ORCPT ); Fri, 4 Sep 2020 11:55:26 -0400 Received: from mail-qk1-x742.google.com (mail-qk1-x742.google.com [IPv6:2607:f8b0:4864:20::742]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A5E1C061263 for ; Fri, 4 Sep 2020 08:55:25 -0700 (PDT) Received: by mail-qk1-x742.google.com with SMTP id u3so6706960qkd.9 for ; Fri, 04 Sep 2020 08:55:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D1yn3SCzU30h04jFGZXM8u3sA7NFVzSbPZqsPP+oWTg=; b=e29uwL+EpSoES/+z1K7U/GWcIt61CkRtvS0de6u87FjQ4LIGnpTSAeb20AmUaBcCZ8 qtWzRwMAkZO+FFYyxWZgTURdUzTgq6bhfj60DTRKFmf9wWPT10+0oU/yOGpjFBtn9Yab oAuX8ffQuctwoR52w0eq8k+Qv0iHkXxsn4ZzCB7xDfRKFO6+vWmJc2uHQb5HuinMDXj0 4x11oTIlnbY00jrQyfglYGC0moCfhrkmlrCmXpOejfircLaXWuz1uHJerPmGG6PAYKWP Bep1fwiC1Nn43wd0BDxFgDLF5fMFxZJxsemZJJfrYPg9oMu1dtnkwBanuwslteLyGari kW2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D1yn3SCzU30h04jFGZXM8u3sA7NFVzSbPZqsPP+oWTg=; b=BorM+mne5vzGRCpPVaunQ+2KQCFJ5n3F+8fpsbe/5HBTiKX9iTN8UoMKSn41VyrMme Si/GvP/IppN1eOn5EsnYilEZjuJNk7Uh7TiTY9FCiY7mwXcqUx/3Q4UQRKxN/ft39Jd9 tF0FncvG1TSQGQA7aYUrm5yJbj49drVDwcMnBmO1CoaJTd7b8iwMcMKPGqAz+70inQZT XW0NSAa/RBhO6oIKUSXsethuyYZgCXcPZR29RNjJpdtbp2H8TogbkJNJcKoKdxGjByt/ J5ry6hvYgFiRHq1L+rGSn2168Tf8U9vf8dhArlifiLVOHT74PzQspWJuattBqXRaC8LU +u4A== X-Gm-Message-State: AOAM532DYb0e5Krn+upRj8N/OSVd7rVlSgIDCx50MgAbqhNIo2BAWZXr Iwvu5qnRFJztScRUkn0W+G4iiQ== X-Google-Smtp-Source: ABdhPJyFYlEUGi9gN4pbIp7iXdUMIwRXrisWYKCYwXf+631ilHcizfoLcG9kkcGDBzyGaKjC1Bz+iw== X-Received: by 2002:a37:6108:: with SMTP id v8mr7108268qkb.264.1599234924005; Fri, 04 Sep 2020 08:55:24 -0700 (PDT) Received: from localhost.localdomain (ec2-34-197-84-77.compute-1.amazonaws.com. [34.197.84.77]) by smtp.gmail.com with ESMTPSA id v18sm4724473qtq.15.2020.09.04.08.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 08:55:23 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Sai Prakash Ranjan , Jordan Crouse , Rob Clark Cc: Sibi Sankar , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 8/8] iommu/arm-smmu-qcom: Setup identity domain for boot mappings Date: Fri, 4 Sep 2020 15:55:13 +0000 Message-Id: <20200904155513.282067-9-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200904155513.282067-1-bjorn.andersson@linaro.org> References: <20200904155513.282067-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With many Qualcomm platforms not having functional S2CR BYPASS a temporary IOMMU domain, without translation, needs to be allocated in order to allow these memory transactions. Unfortunately the boot loader uses the first few context banks, so rather than overwriting a active bank the last context bank is used and streams are diverted here during initialization. This also performs the readback of SMR registers for the Qualcomm platform, to trigger the mechanism. This is based on prior work by Thierry Reding and Laurentiu Tudor. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan --- Changes since v2: - Combined from pieces spread between the Qualcomm impl and generic code in v2. - Moved to use the newly introduced inherit_mapping op. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 70a1eaa52e14..a54302190932 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -12,6 +12,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; bool bypass_broken; + struct iommu_domain *identity; }; static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) @@ -228,6 +229,37 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) return 0; } +static int qcom_smmu_inherit_mappings(struct arm_smmu_device *smmu) +{ + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + int cbndx; + u32 smr; + int i; + + qsmmu->identity = arm_smmu_alloc_identity_domain(smmu); + if (IS_ERR(qsmmu->identity)) + return PTR_ERR(qsmmu->identity); + + cbndx = to_smmu_domain(qsmmu->identity)->cfg.cbndx; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + + if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + + smmu->s2crs[i].type = S2CR_TYPE_TRANS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = cbndx; + smmu->s2crs[i].count++; + } + } + + return 0; +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -270,6 +302,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = { .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, + .inherit_mappings = qcom_smmu_inherit_mappings, }; static const struct arm_smmu_impl qcom_adreno_smmu_impl = {