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[93.23.19.208]) by smtp.gmail.com with ESMTPSA id p18sm4490311wrx.47.2020.09.06.10.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2020 10:23:46 -0700 (PDT) From: Fabien Parent To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/2] dt-bindings: mediatek: add MT8167 power dt-bindings Date: Sun, 6 Sep 2020 19:23:36 +0200 Message-Id: <20200906172337.1052933-1-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200906_132348_603013_959C6901 X-CRM114-Status: GOOD ( 15.84 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:341 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, krzk@kernel.org, Fabien Parent , robh+dt@kernel.org, mars.cheng@mediatek.com, macpaul.lin@mediatek.com, matthias.bgg@gmail.com, owen.chen@mediatek.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the SCPSYS binding documentation for MediaTek MT8167 SoCs. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +++ include/dt-bindings/power/mt8167-power.h | 14 ++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/dt-bindings/power/mt8167-power.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 2bc367793aec..08cb8438a35d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -10,6 +10,7 @@ domain control. The driver implements the Generic PM domain bindings described in power/power-domain.yaml. It provides the power domains defined in - include/dt-bindings/power/mt8173-power.h +- include/dt-bindings/power/mt8167-power.h - include/dt-bindings/power/mt6797-power.h - include/dt-bindings/power/mt6765-power.h - include/dt-bindings/power/mt2701-power.h @@ -26,6 +27,7 @@ Required properties: - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC - "mediatek,mt7623a-scpsys": For MT7623A SoC - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC + - "mediatek,mt8167-scpsys" - "mediatek,mt8173-scpsys" - #power-domain-cells: Must be 1 - reg: Address range of the SCPSYS unit @@ -42,6 +44,7 @@ Required properties: Required clocks for MT6797: "mm", "mfg", "vdec" Required clocks for MT7622 or MT7629: "hif_sel" Required clocks for MT7623A: "ethif" + Required clocks for MT8167: "mm", "mfg", "vdec", "axi_mfg" Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" Optional properties: diff --git a/include/dt-bindings/power/mt8167-power.h b/include/dt-bindings/power/mt8167-power.h new file mode 100644 index 000000000000..8e7bcb4834dc --- /dev/null +++ b/include/dt-bindings/power/mt8167-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT8167_POWER_H +#define _DT_BINDINGS_POWER_MT8167_POWER_H + +#define MT8167_POWER_DOMAIN_MM 0 +#define MT8167_POWER_DOMAIN_DISP 0 +#define MT8167_POWER_DOMAIN_VDEC 1 +#define MT8167_POWER_DOMAIN_ISP 2 +#define MT8167_POWER_DOMAIN_CONN 3 +#define MT8167_POWER_DOMAIN_MFG_ASYNC 4 +#define MT8167_POWER_DOMAIN_MFG_2D 5 +#define MT8167_POWER_DOMAIN_MFG 6 + +#endif /* _DT_BINDINGS_POWER_MT8167_POWER_H */ From patchwork Sun Sep 6 17:23:37 2020 Content-Type: text/plain; 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[93.23.19.208]) by smtp.gmail.com with ESMTPSA id p18sm4490311wrx.47.2020.09.06.10.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2020 10:23:49 -0700 (PDT) From: Fabien Parent To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 2/2] soc: mediatek: add SCPSYS power dmain for MT8167 SoC Date: Sun, 6 Sep 2020 19:23:37 +0200 Message-Id: <20200906172337.1052933-2-fparent@baylibre.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200906172337.1052933-1-fparent@baylibre.com> References: <20200906172337.1052933-1-fparent@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200906_132351_144823_8686DBF2 X-CRM114-Status: GOOD ( 16.45 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, krzk@kernel.org, Fabien Parent , robh+dt@kernel.org, mars.cheng@mediatek.com, macpaul.lin@mediatek.com, matthias.bgg@gmail.com, owen.chen@mediatek.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add SCPSYS power domain support for MT8167 SoC. Signed-off-by: Fabien Parent --- drivers/soc/mediatek/mtk-scpsys.c | 99 +++++++++++++++++++++++++++ include/linux/soc/mediatek/infracfg.h | 8 +++ 2 files changed, 107 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index f669d3754627..ce897720ef17 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #define MTK_POLL_DELAY_US 10 @@ -89,6 +90,7 @@ enum clk_id { CLK_HIFSEL, CLK_JPGDEC, CLK_AUDIO, + CLK_AXI_MFG, CLK_MAX, }; @@ -103,6 +105,7 @@ static const char * const clk_names[] = { "hif_sel", "jpgdec", "audio", + "axi_mfg", NULL, }; @@ -911,6 +914,87 @@ static const struct scp_domain_data scp_domain_data_mt7623a[] = { }, }; +/* + * MT8167 power domain support + */ +#define PWR_STATUS_MFG_2D_MT8167 BIT(24) +#define PWR_STATUS_MFG_ASYNC_MT8167 BIT(25) + +static const struct scp_domain_data scp_domain_data_mt8167[] = { + [MT8167_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bus_prot_mask = MT8167_TOP_AXI_PROT_EN_MM_EMI | + MT8167_TOP_AXI_PROT_EN_MCU_MM, + .clk_id = {CLK_MM}, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8167_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_MM, CLK_VDEC}, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8167_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_MM}, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8167_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC_MT8167, + .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bus_prot_mask = MT8167_TOP_AXI_PROT_EN_MCU_MFG | + MT8167_TOP_AXI_PROT_EN_MFG_EMI, + .clk_id = {CLK_MFG, CLK_AXI_MFG}, + }, + [MT8167_POWER_DOMAIN_MFG_2D] = { + .name = "mfg_2d", + .sta_mask = PWR_STATUS_MFG_2D_MT8167, + .ctl_offs = SPM_MFG_2D_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_NONE}, + }, + [MT8167_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_NONE}, + }, + [MT8167_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = 0, + .bus_prot_mask = MT8167_TOP_AXI_PROT_EN_CONN_EMI | + MT8167_TOP_AXI_PROT_EN_CONN_MCU | + MT8167_TOP_AXI_PROT_EN_MCU_CONN, + .clk_id = {CLK_NONE}, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8167[] = { + {MT8167_POWER_DOMAIN_MFG_ASYNC, MT8167_POWER_DOMAIN_MFG_2D}, + {MT8167_POWER_DOMAIN_MFG_2D, MT8167_POWER_DOMAIN_MFG}, +}; + /* * MT8173 power domain support */ @@ -1064,6 +1148,18 @@ static const struct scp_soc_data mt7623a_data = { .bus_prot_reg_update = true, }; +static const struct scp_soc_data mt8167_data = { + .domains = scp_domain_data_mt8167, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8167), + .subdomains = scp_subdomain_mt8167, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8167), + .regs = { + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + }, + .bus_prot_reg_update = true, +}; + static const struct scp_soc_data mt8173_data = { .domains = scp_domain_data_mt8173, .num_domains = ARRAY_SIZE(scp_domain_data_mt8173), @@ -1096,6 +1192,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { }, { .compatible = "mediatek,mt7623a-scpsys", .data = &mt7623a_data, + }, { + .compatible = "mediatek,mt8167-scpsys", + .data = &mt8167_data, }, { .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index fd25f0148566..6ee49bf90acf 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,14 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H +#define MT8167_TOP_AXI_PROT_EN_MM_EMI BIT(1) +#define MT8167_TOP_AXI_PROT_EN_MCU_MFG BIT(2) +#define MT8167_TOP_AXI_PROT_EN_CONN_EMI BIT(4) +#define MT8167_TOP_AXI_PROT_EN_MFG_EMI BIT(5) +#define MT8167_TOP_AXI_PROT_EN_CONN_MCU BIT(8) +#define MT8167_TOP_AXI_PROT_EN_MCU_CONN BIT(9) +#define MT8167_TOP_AXI_PROT_EN_MCU_MM BIT(11) + #define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) #define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) #define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)