From patchwork Mon Sep 7 08:18:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11760125 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE2CA618 for ; Mon, 7 Sep 2020 08:18:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 93509208C7 for ; Mon, 7 Sep 2020 08:18:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="jgO6nuaR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 93509208C7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D18D6E372; Mon, 7 Sep 2020 08:18:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F0C26E2D5 for ; Mon, 7 Sep 2020 08:18:33 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id s13so13452923wmh.4 for ; Mon, 07 Sep 2020 01:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=miWW6H6jXaFE/FyCEk5bY4nk7z7nkaDQEzvoX6DPlkA=; b=jgO6nuaRnlo0R2OYFX2vcDkqIExJA3JJthDEk7bvwcmzptmlrdmL9LVBaBYN+tgFno 3Xy+PA6367n1pTE12o5y1KJC0pJan5XYQdAxgLIvpfe0/eYP3DeMjz+ck5qtw8SYM9qo J0AaFTHJ0hi2U58MsHU8vsIOh8yMo6JhUTSVtPjedZCyBClJAtST6EI2aUNnERV67TZa YxodpFCjL3Zli9Wgpg53hQ9fkU0GKZpETAQypmWG5MaFv9H51Mv0klk23hVicKOVW4iG 3DaIltmO1vFQnyrBIMtX5/Sg2ECwSDcurrC2TGyBfPUxu9o94hsBvBuknTsJsT/RjFZT ZI1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=miWW6H6jXaFE/FyCEk5bY4nk7z7nkaDQEzvoX6DPlkA=; b=XePy0rTo4yqGa0a2BLFIUIjehCJ4zGcbf6fqnsSkcU/oKy4ujnpUsHG+hsqaddFGWh w7WS5UvNNREyKIJAumcfdykj4cC386RmV7wYChIWBZMIOm55x51Dq4yGYy6pgD69tg81 GNZRokTsq6fBE33JrDBofDBTr3kHLmF3CKRq7GWsdJPv43hmLpqUAGZvoPZrnthrK6A5 nRxDIeuTExwkZzPyUz1bKPiwdvZ35ye4VvqMqYbekBP4S55z8VsGuOCsbzuvHCd+xABh xDX9C0cSTOE3dA2xwVR7+etN90FRTpYbO5+b1zJhRyia7mjuDa4JrNjneRGyR9RmA0eh nORg== X-Gm-Message-State: AOAM5307rWU5+5mUCbQVY0qnznTdbfs3yU/QURfnxRZEraJRWhql4hie y4OFLZgQouoEyi5k61n7F9d+3w== X-Google-Smtp-Source: ABdhPJzt7+ODbEr1nL9IMe4B5idhevglKUu034LrO7TAnTPbUIolpz1hDb42Mq+Viw7CjTrnT2KwwQ== X-Received: by 2002:a1c:5605:: with SMTP id k5mr14600574wmb.142.1599466711691; Mon, 07 Sep 2020 01:18:31 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5405:9623:e2f1:b2ac]) by smtp.gmail.com with ESMTPSA id q186sm28032205wma.45.2020.09.07.01.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 01:18:31 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, devicetree@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: display: amlogic, meson-vpu: add bindings for VPU found in AXG SoCs Date: Mon, 7 Sep 2020 10:18:20 +0200 Message-Id: <20200907081825.1654-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200907081825.1654-1-narmstrong@baylibre.com> References: <20200907081825.1654-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic AXG SoC family has a downgraded VPU supporting only MIPI-DSI output after it's ENCL DPI encoder output. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../bindings/display/amlogic,meson-vpu.yaml | 36 +++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index a8d202c9d004..e2e7d99d8ace 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -31,8 +31,10 @@ description: | The Video Input Unit is in charge of the pixel scanout from the DDR memory. It fetches the frames addresses, stride and parameters from the "Canvas" memory. + On the AXG family, the Video Input Unit direclty reads from DDR memory. This part is also in charge of the CSC (Colorspace Conversion). It can handle 2 OSD Planes and 2 Video Planes. + On the AXG family, only a single OSD plane without scalins is supported. VPP: Video Post Processing -------------------------- @@ -49,11 +51,13 @@ description: | The VENC is composed of the multiple pixel encoders - ENCI : Interlace Video encoder for CVBS and Interlace HDMI - ENCP : Progressive Video Encoder for HDMI - - ENCL : LCD LVDS Encoder + - ENCL : LCD DPI Encoder The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock tree and provides the scanout clock to the VPP and VIU. The ENCI is connected to a single VDAC for Composite Output. The ENCI and ENCP are connected to an on-chip HDMI Transceiver. + On the AXG and G12A family, the ENCL is connected to a DPI-to-DSI + transceiver. properties: compatible: @@ -65,6 +69,7 @@ properties: - amlogic,meson-gxm-vpu # GXM (S912) - const: amlogic,meson-gx-vpu - enum: + - amlogic,meson-axg-vpu # AXG (A113D, A113X) - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2) reg: @@ -92,6 +97,11 @@ properties: description: A port node pointing to the HDMI-TX port node. + port@2: + type: object + description: + A port node pointing to the DPI port node. + "#address-cells": const: 1 @@ -102,11 +112,31 @@ required: - compatible - reg - interrupts - - port@0 - - port@1 - "#address-cells" - "#size-cells" +allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-vpu + - amlogic,meson-g12a-vpu + + then: + required: + - port@0 + - port@1 + - if: + properties: + compatible: + enum: + - amlogic,meson-axg-vpu + + then: + required: + - port@2 + additionalProperties: false examples: From patchwork Mon Sep 7 08:18:21 2020 Content-Type: text/plain; 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Mon, 07 Sep 2020 01:18:32 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, devicetree@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Date: Mon, 7 Sep 2020 10:18:21 +0200 Message-Id: <20200907081825.1654-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200907081825.1654-1-narmstrong@baylibre.com> References: <20200907081825.1654-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other Amlogic SoCs. Signed-off-by: Neil Armstrong --- .../display/amlogic,meson-dw-mipi-dsi.yaml | 115 ++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml new file mode 100644 index 000000000000..6177f45ea1a6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller + +maintainers: + - Neil Armstrong + +description: | + The Amlogic Meson Synopsys Designware Integration is composed of + - A Synopsys DesignWare MIPI DSI Host Controller IP + - A TOP control block controlling the Clocks & Resets of the IP + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,meson-axg-dw-mipi-dsi + + reg: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + minItems: 2 + items: + - const: pclk + - const: px_clk + - const: meas_clk + + resets: + minItems: 1 + + reset-names: + items: + - const: top + + phys: + minItems: 1 + + phy-names: + items: + - const: dphy + + ports: + type: object + + properties: + port@0: + type: object + description: Input node to receive pixel data. + port@1: + type: object + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +additionalProperties: false + +examples: + - | + dsi@7000 { + compatible = "amlogic,meson-axg-dw-mipi-dsi"; + reg = <0x6000 0x400>; + resets = <&reset_top>; + reset-names = "top"; + clocks = <&clk_pclk>, <&clk_px>; + clock-names = "pclk", "px_clk"; + phys = <&mipi_dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VPU VENC Input */ + mipi_dsi_venc_port: port@0 { + reg = <0>; + + mipi_dsi_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + /* DSI Output */ + mipi_dsi_panel_port: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + }; From patchwork Mon Sep 7 08:18:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11760131 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C11BA13B1 for ; Mon, 7 Sep 2020 08:18:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 960CD2145D for ; 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Mon, 07 Sep 2020 01:18:34 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5405:9623:e2f1:b2ac]) by smtp.gmail.com with ESMTPSA id q186sm28032205wma.45.2020.09.07.01.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 01:18:33 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch Subject: [PATCH 3/6] drm/meson: add support for VPU found in AXG SoCs Date: Mon, 7 Sep 2020 10:18:22 +0200 Message-Id: <20200907081825.1654-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200907081825.1654-1-narmstrong@baylibre.com> References: <20200907081825.1654-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic AXG SoC family has a downgraded VPU with the following changes : - Only a single OSD plane, no overlay video plane - The primary plane doesn't support HW scaling - The pixels are read directly from DDR without any Canvas module - Doesn't support HDMI or CVBS - Ouputs only with ENCL encoder to a DPI-to-DSI Synopsys DW-MIPI-DSI transceiver Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_crtc.c | 8 +- drivers/gpu/drm/meson/meson_drv.c | 115 ++++++++++++++++-------- drivers/gpu/drm/meson/meson_drv.h | 10 ++- drivers/gpu/drm/meson/meson_plane.c | 74 +++++++++++++-- drivers/gpu/drm/meson/meson_registers.h | 1 + drivers/gpu/drm/meson/meson_viu.c | 50 ++++++++++- drivers/gpu/drm/meson/meson_vpp.c | 6 +- 7 files changed, 215 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index 2854272dc2d9..430599caa5a0 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -366,7 +366,13 @@ void meson_crtc_irq(struct meson_drm *priv) writel_relaxed(priv->viu.osd_sc_v_ctrl0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); - if (!priv->viu.osd1_afbcd) + /* AXG doesn't use CANVAS since it support a single plane */ + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) { + writel_relaxed(priv->viu.osd1_addr, + priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4)); + writel_relaxed(priv->viu.osd1_blk2_cfg4, + priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4)); + } else if (!priv->viu.osd1_afbcd) meson_canvas_config(priv->canvas, priv->canvas_id_osd1, priv->viu.osd1_addr, priv->viu.osd1_stride, diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 8b9c8dd788c4..92346653223f 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -223,6 +223,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) drm->dev_private = priv; priv->drm = drm; priv->dev = dev; + priv->data = match; priv->compat = match->compat; priv->afbcd.ops = match->afbcd_ops; @@ -255,32 +256,34 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) goto free_drm; } - priv->canvas = meson_canvas_get(dev); - if (IS_ERR(priv->canvas)) { - ret = PTR_ERR(priv->canvas); - goto free_drm; - } + if (priv->data->requires_canvas) { + priv->canvas = meson_canvas_get(dev); + if (IS_ERR(priv->canvas)) { + ret = PTR_ERR(priv->canvas); + goto free_drm; + } - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1); - if (ret) - goto free_drm; - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0); - if (ret) { - meson_canvas_free(priv->canvas, priv->canvas_id_osd1); - goto free_drm; - } - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1); - if (ret) { - meson_canvas_free(priv->canvas, priv->canvas_id_osd1); - meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); - goto free_drm; - } - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2); - if (ret) { - meson_canvas_free(priv->canvas, priv->canvas_id_osd1); - meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); - meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); - goto free_drm; + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1); + if (ret) + goto free_drm; + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0); + if (ret) { + meson_canvas_free(priv->canvas, priv->canvas_id_osd1); + goto free_drm; + } + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1); + if (ret) { + meson_canvas_free(priv->canvas, priv->canvas_id_osd1); + meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); + goto free_drm; + } + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2); + if (ret) { + meson_canvas_free(priv->canvas, priv->canvas_id_osd1); + meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); + meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); + goto free_drm; + } } priv->vsync_irq = platform_get_irq(pdev, 0); @@ -303,8 +306,8 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) ret = drmm_mode_config_init(drm); if (ret) goto free_drm; - drm->mode_config.max_width = 3840; - drm->mode_config.max_height = 2160; + drm->mode_config.max_width = priv->data->max_width; + drm->mode_config.max_height = priv->data->max_height; drm->mode_config.funcs = &meson_mode_config_funcs; drm->mode_config.helper_private = &meson_mode_config_helpers; @@ -322,9 +325,11 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) /* Encoder Initialization */ - ret = meson_venc_cvbs_create(priv); - if (ret) - goto free_drm; + if (priv->data->provides_cvbs) { + ret = meson_venc_cvbs_create(priv); + if (ret) + goto free_drm; + } if (has_components) { ret = component_bind_all(drm->dev, drm); @@ -334,13 +339,17 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) } } - ret = meson_plane_create(priv); - if (ret) - goto free_drm; + if (priv->data->osd_count) { + ret = meson_plane_create(priv); + if (ret) + goto free_drm; + } - ret = meson_overlay_create(priv); - if (ret) - goto free_drm; + if (priv->data->vd_count) { + ret = meson_overlay_create(priv); + if (ret) + goto free_drm; + } ret = meson_crtc_create(priv); if (ret) @@ -516,20 +525,52 @@ static int meson_drv_probe(struct platform_device *pdev) static struct meson_drm_match_data meson_drm_gxbb_data = { .compat = VPU_COMPATIBLE_GXBB, + .requires_canvas = true, + .provides_cvbs = true, + .osd_count = 2, + .vd_count = 2, + .max_width = 3840, + .max_height = 2160, }; static struct meson_drm_match_data meson_drm_gxl_data = { .compat = VPU_COMPATIBLE_GXL, + .requires_canvas = true, + .provides_cvbs = true, + .osd_count = 2, + .vd_count = 2, + .max_width = 3840, + .max_height = 2160, }; static struct meson_drm_match_data meson_drm_gxm_data = { .compat = VPU_COMPATIBLE_GXM, .afbcd_ops = &meson_afbcd_gxm_ops, + .requires_canvas = true, + .provides_cvbs = true, + .osd_count = 2, + .vd_count = 2, + .max_width = 3840, + .max_height = 2160, +}; + +static struct meson_drm_match_data meson_drm_axg_data = { + .compat = VPU_COMPATIBLE_AXG, + .osd_count = 1, + .vd_count = 0, + .max_width = 1920, + .max_height = 1080, }; static struct meson_drm_match_data meson_drm_g12a_data = { .compat = VPU_COMPATIBLE_G12A, .afbcd_ops = &meson_afbcd_g12a_ops, + .requires_canvas = true, + .provides_cvbs = true, + .osd_count = 4, + .vd_count = 2, + .max_width = 3840, + .max_height = 2160, }; static const struct of_device_id dt_match[] = { @@ -539,6 +580,8 @@ static const struct of_device_id dt_match[] = { .data = (void *)&meson_drm_gxl_data }, { .compatible = "amlogic,meson-gxm-vpu", .data = (void *)&meson_drm_gxm_data }, + { .compatible = "amlogic,meson-axg-vpu", + .data = (void *)&meson_drm_axg_data }, { .compatible = "amlogic,meson-g12a-vpu", .data = (void *)&meson_drm_g12a_data }, {} diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h index 177dac3ca3be..5d67f97ec298 100644 --- a/drivers/gpu/drm/meson/meson_drv.h +++ b/drivers/gpu/drm/meson/meson_drv.h @@ -22,12 +22,19 @@ enum vpu_compatible { VPU_COMPATIBLE_GXBB = 0, VPU_COMPATIBLE_GXL = 1, VPU_COMPATIBLE_GXM = 2, - VPU_COMPATIBLE_G12A = 3, + VPU_COMPATIBLE_AXG = 3, + VPU_COMPATIBLE_G12A = 4, }; struct meson_drm_match_data { enum vpu_compatible compat; struct meson_afbcd_ops *afbcd_ops; + bool requires_canvas; + bool provides_cvbs; + unsigned int osd_count; + unsigned int vd_count; + unsigned int max_width; + unsigned int max_height; }; struct meson_drm_soc_limits { @@ -52,6 +59,7 @@ struct meson_drm { struct drm_plane *primary_plane; struct drm_plane *overlay_plane; + const struct meson_drm_match_data *data; const struct meson_drm_soc_limits *limits; /* Components Data */ diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c index 35338ed18209..9111b3540bdf 100644 --- a/drivers/gpu/drm/meson/meson_plane.c +++ b/drivers/gpu/drm/meson/meson_plane.c @@ -93,6 +93,25 @@ static int meson_plane_atomic_check(struct drm_plane *plane, false, true); } +static int meson_plane_atomic_check_axg(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct drm_crtc_state *crtc_state; + + if (!state->crtc) + return 0; + + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + /* AXG VPU OSD plane doesn't support scaling */ + return drm_atomic_helper_check_plane_state(state, crtc_state, + DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_HELPER_NO_SCALING, + true, true); +} + #define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \ AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \ AFBC_FORMAT_MOD_YTR | \ @@ -125,6 +144,29 @@ static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv) return ((line_stride + 1) >> 1) << 1; } +static u32 meson_axg_line_stride(struct meson_drm *priv, u32 format) +{ + u32 line_stride = 0; + u32 bwidth; + + switch (format) { + case DRM_FORMAT_RGB565: + bwidth = priv->viu.osd1_stride >> 1; + line_stride = ((bwidth << 4) + 127) >> 7; + break; + case DRM_FORMAT_RGB888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + bwidth = priv->viu.osd1_stride >> 2; + line_stride = ((bwidth << 5) + 127) >> 7; + break; + } + + return ((line_stride + 1) >> 1) << 1; +} + static void meson_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { @@ -161,15 +203,20 @@ static void meson_plane_atomic_update(struct drm_plane *plane, else priv->viu.osd1_afbcd = false; - /* Enable OSD and BLK0, set max global alpha */ - priv->viu.osd1_ctrl_stat = OSD_ENABLE | - (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | - OSD_BLK0_ENABLE; + priv->viu.osd1_ctrl_stat = OSD_ENABLE | OSD_BLK0_ENABLE; + + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + priv->viu.osd1_ctrl_stat |= 0x100 << OSD_GLOBAL_ALPHA_SHIFT; + else + priv->viu.osd1_ctrl_stat |= 0xFF << OSD_GLOBAL_ALPHA_SHIFT; priv->viu.osd1_ctrl_stat2 = readl(priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); - canvas_id_osd1 = priv->canvas_id_osd1; + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + canvas_id_osd1 = 0x40; + else + canvas_id_osd1 = priv->canvas_id_osd1; /* Set up BLK0 to point to the right canvas */ priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL; @@ -366,7 +413,10 @@ static void meson_plane_atomic_update(struct drm_plane *plane, priv->viu.osd1_height = fb->height; priv->viu.osd1_width = fb->width; - if (priv->viu.osd1_afbcd) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + priv->viu.osd1_blk2_cfg4 = meson_axg_line_stride(priv, + fb->format->format); + else if (priv->viu.osd1_afbcd) { priv->afbcd.modifier = fb->modifier; priv->afbcd.format = fb->format->format; @@ -413,6 +463,13 @@ static void meson_plane_atomic_disable(struct drm_plane *plane, priv->viu.osd1_enabled = false; } +static const struct drm_plane_helper_funcs meson_plane_helper_funcs_axg = { + .atomic_check = meson_plane_atomic_check_axg, + .atomic_disable = meson_plane_atomic_disable, + .atomic_update = meson_plane_atomic_update, + .prepare_fb = drm_gem_fb_prepare_fb, +}; + static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { .atomic_check = meson_plane_atomic_check, .atomic_disable = meson_plane_atomic_disable, @@ -550,7 +607,10 @@ int meson_plane_create(struct meson_drm *priv) format_modifiers, DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); - drm_plane_helper_add(plane, &meson_plane_helper_funcs); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + drm_plane_helper_add(plane, &meson_plane_helper_funcs_axg); + else + drm_plane_helper_add(plane, &meson_plane_helper_funcs); /* For now, OSD Primary plane is always on the front */ drm_plane_create_zpos_immutable_property(plane, 1); diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h index 446e7961da48..18396b59e6cb 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -588,6 +588,7 @@ #define VPP_OSD_SCALE_COEF_IDX 0x1dcc #define VPP_OSD_SCALE_COEF 0x1dcd #define VPP_INT_LINE_NUM 0x1dce +#define VPP_MATRIX_CLIP 0x1dde #define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60 #define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61 diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index aede0c67a57f..9b644e598211 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -423,19 +423,63 @@ void meson_viu_init(struct meson_drm *priv) /* On GXL/GXM, Use the 10bit HDR conversion matrix */ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) meson_viu_load_matrix(priv); else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff, true); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) { + writel_bits_relaxed(BIT(0), BIT(0), + priv->io_base + _REG(VPP_MATRIX_CTRL)); + writel_bits_relaxed(0x3 << 8, 0, + priv->io_base + _REG(VPP_MATRIX_CTRL)); + + writel_relaxed(0x0fc00e00, + priv->io_base + _REG(VPP_MATRIX_PRE_OFFSET0_1)); + writel_relaxed(0x00000e00, + priv->io_base + _REG(VPP_MATRIX_PRE_OFFSET2)); + + /* + * ycbcr limit range, 709 to RGB + * -16 1.164 0 1.793 0 + * -128 1.164 -0.213 -0.534 0 + * -128 1.164 2.115 0 0 + */ + writel_relaxed(0x04a80000, + priv->io_base + _REG(VPP_MATRIX_COEF00_01)); + writel_relaxed(0x072c04a8, + priv->io_base + _REG(VPP_MATRIX_COEF02_10)); + writel_relaxed(0x1f261ddd, + priv->io_base + _REG(VPP_MATRIX_COEF11_12)); + writel_relaxed(0x04a80876, + priv->io_base + _REG(VPP_MATRIX_COEF20_21)); + writel_relaxed(0x0, priv->io_base + _REG(VPP_MATRIX_COEF22)); + writel_relaxed(0x0, priv->io_base + _REG(VPP_MATRIX_OFFSET0_1)); + writel_relaxed(0x0, priv->io_base + _REG(VPP_MATRIX_OFFSET2)); + + writel_bits_relaxed(0x1f << 3, 0, + priv->io_base + _REG(VPP_MATRIX_CLIP)); + } + /* Initialize OSD1 fifo control register */ reg = VIU_OSD_DDR_PRIORITY_URGENT | - VIU_OSD_HOLD_FIFO_LINES(31) | - VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */ VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */ + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + reg |= VIU_OSD_HOLD_FIFO_LINES(24); + else + reg |= VIU_OSD_HOLD_FIFO_LINES(31); + + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + reg |= VIU_OSD_FIFO_DEPTH_VAL(32); /* fifo_depth_val: 32*8=256 */ + else + reg |= VIU_OSD_FIFO_DEPTH_VAL(64); /* fifo_depth_val: 64*8=512 */ + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) reg |= VIU_OSD_BURST_LENGTH_32; else diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c index 154837688ab0..069f527d42c6 100644 --- a/drivers/gpu/drm/meson/meson_vpp.c +++ b/drivers/gpu/drm/meson/meson_vpp.c @@ -91,7 +91,8 @@ static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv, void meson_vpp_init(struct meson_drm *priv) { /* set dummy data default YUV black */ - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { writel_bits_relaxed(0xff << 16, 0xff << 16, @@ -107,6 +108,9 @@ void meson_vpp_init(struct meson_drm *priv) if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, priv->io_base + _REG(VPP_OFIFO_SIZE)); + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) + writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x400, + priv->io_base + _REG(VPP_OFIFO_SIZE)); else writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE)); From patchwork Mon Sep 7 08:18:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11760129 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9BB5618 for ; Mon, 7 Sep 2020 08:18:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B02B6208C7 for ; Mon, 7 Sep 2020 08:18:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="mHnwiHES" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B02B6208C7 Authentication-Results: mail.kernel.org; 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Mon, 07 Sep 2020 01:18:35 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch Subject: [PATCH 4/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Date: Mon, 7 Sep 2020 10:18:23 +0200 Message-Id: <20200907081825.1654-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200907081825.1654-1-narmstrong@baylibre.com> References: <20200907081825.1654-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver on the Amlogic AXG SoCs. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++++++++++++++++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_vpp.h | 2 + 3 files changed, 236 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index f93c725b6f02..3090418deffb 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -6,6 +6,7 @@ */ #include +#include #include @@ -1557,6 +1558,224 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, } EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); +static unsigned short meson_encl_gamma_table[256] = { + 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, + 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, + 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, + 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, + 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, + 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, + 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444, + 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508, + 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, + 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, + 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, + 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, + 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828, + 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892, + 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956, + 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020, +}; + +#define GAMMA_VCOM_POL 7 /* RW */ +#define GAMMA_RVS_OUT 6 /* RW */ +#define ADR_RDY 5 /* Read Only */ +#define WR_RDY 4 /* Read Only */ +#define RD_RDY 3 /* Read Only */ +#define GAMMA_TR 2 /* RW */ +#define GAMMA_SET 1 /* RW */ +#define GAMMA_EN 0 /* RW */ + +#define H_RD 12 +#define H_AUTO_INC 11 +#define H_SEL_R 10 +#define H_SEL_G 9 +#define H_SEL_B 8 +#define HADR_MSB 7 /* 7:0 */ +#define HADR 0 /* 7:0 */ + +#define GAMMA_RETRY 1000 + +static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data, + u32 rgb_mask) +{ + int i, ret; + u32 reg; + + writel_bits_relaxed(BIT(GAMMA_EN), 0, + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); + + ret = readl_relaxed_poll_timeout(priv->io_base + + _REG(L_GAMMA_CNTL_PORT), + reg, reg & BIT(ADR_RDY), 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(BIT(H_AUTO_INC) | + BIT(rgb_mask) | + (0 << HADR), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); + + for (i = 0; i < 256; i++) { + ret = readl_relaxed_poll_timeout(priv->io_base + + _REG(L_GAMMA_CNTL_PORT), + reg, reg & BIT(WR_RDY), + 10, 10000); + if (ret) + pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__); + + writel_relaxed(data[i], + priv->io_base + _REG(L_GAMMA_DATA_PORT)); + } + + ret = readl_relaxed_poll_timeout(priv->io_base + + _REG(L_GAMMA_CNTL_PORT), + reg, reg & BIT(ADR_RDY), 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(BIT(H_AUTO_INC) | + BIT(rgb_mask) | + (0x23 << HADR), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); +} + +void meson_encl_load_gamma(struct meson_drm *priv) +{ + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_R); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_G); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_B); + + writel_bits_relaxed(BIT(GAMMA_EN), BIT(GAMMA_EN), + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); +} + +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + struct drm_display_mode *mode) +{ + unsigned int max_pxcnt; + unsigned int max_lncnt; + unsigned int havon_begin; + unsigned int havon_end; + unsigned int vavon_bline; + unsigned int vavon_eline; + unsigned int hso_begin; + unsigned int hso_end; + unsigned int vso_begin; + unsigned int vso_end; + unsigned int vso_bline; + unsigned int vso_eline; + + max_pxcnt = mode->htotal - 1; + max_lncnt = mode->vtotal - 1; + havon_begin = mode->htotal - mode->hsync_start; + havon_end = havon_begin + mode->hdisplay - 1; + vavon_bline = mode->vtotal - mode->vsync_start; + vavon_eline = vavon_bline + mode->vdisplay - 1; + hso_begin = 0; + hso_end = mode->hsync_end - mode->hsync_start; + vso_begin = 0; + vso_end = 0; + vso_bline = 0; + vso_eline = mode->vsync_end - mode->vsync_start; + + meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(0x8000, priv->io_base + _REG(ENCL_VIDEO_MODE)); + writel_relaxed(0x0418, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(0x1000, priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL)); + writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT)); + writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT)); + writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN)); + writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END)); + writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE)); + writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE)); + + writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN)); + writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END)); + writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN)); + writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END)); + writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE)); + writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE)); + writel_relaxed(3, priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL)); + + /* default black pattern */ + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR)); + writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN)); + writel_bits_relaxed(BIT(3), 0, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR)); + writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); + writel_relaxed(0x400, priv->io_base + _REG(L_DITH_CNTL_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR)); + + /* Hsync signal for TTL */ + if (mode->flags & DRM_MODE_FLAG_PHSYNC) { + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR)); + } else { + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR)); + } + writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR)); + + /* Vsync signal for TTL */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR)); + if (mode->flags & DRM_MODE_FLAG_PVSYNC) { + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } else { + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } + + /* DE signal */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR)); + + /* Hsync signal */ + writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR)); + writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR)); + + /* Vsync signal */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR)); + + writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR)); + writel_relaxed(BIT(4) | BIT(5), + priv->io_base + _REG(L_TCON_MISC_SEL_ADDR)); + + priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI; +} +EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set); + void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode) { @@ -1747,8 +1966,15 @@ unsigned int meson_venci_get_field(struct meson_drm *priv) void meson_venc_enable_vsync(struct meson_drm *priv) { - writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, - priv->io_base + _REG(VENC_INTCTRL)); + switch (priv->venc.current_mode) { + case MESON_VENC_MODE_MIPI_DSI: + writel_relaxed(0x200, + priv->io_base + _REG(VENC_INTCTRL)); + break; + default: + writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + } regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); } diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 9138255ffc9e..15f9a5effb40 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -21,6 +21,7 @@ enum { MESON_VENC_MODE_CVBS_PAL, MESON_VENC_MODE_CVBS_NTSC, MESON_VENC_MODE_HDMI, + MESON_VENC_MODE_MIPI_DSI, }; struct meson_cvbs_enci_mode { @@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode { unsigned int analog_sync_adj; }; +/* LCD Encoder gamma setup */ +void meson_encl_load_gamma(struct meson_drm *priv); + /* HDMI Clock parameters */ enum drm_mode_status meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode); @@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, unsigned int ycrcb_map, bool yuv420_mode, const struct drm_display_mode *mode); +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv); void meson_venc_enable_vsync(struct meson_drm *priv); diff --git a/drivers/gpu/drm/meson/meson_vpp.h b/drivers/gpu/drm/meson/meson_vpp.h index afc9553ed8d3..b790042a1650 100644 --- a/drivers/gpu/drm/meson/meson_vpp.h +++ b/drivers/gpu/drm/meson/meson_vpp.h @@ -12,6 +12,8 @@ struct drm_rect; struct meson_drm; +/* Mux VIU/VPP to ENCL */ +#define MESON_VIU_VPP_MUX_ENCL 0x0 /* Mux VIU/VPP to ENCI */ #define MESON_VIU_VPP_MUX_ENCI 0x5 /* Mux VIU/VPP to ENCP */ From patchwork Mon Sep 7 08:18:24 2020 Content-Type: text/plain; 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Mon, 07 Sep 2020 01:18:36 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch Subject: [PATCH 5/6] drm/meson: remove useless recursive components matching Date: Mon, 7 Sep 2020 10:18:24 +0200 Message-Id: <20200907081825.1654-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200907081825.1654-1-narmstrong@baylibre.com> References: <20200907081825.1654-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The initial design was recursive to cover all port/endpoints, but only the first layer of endpoints should be covered by the components list. This also breaks the MIPI-DSI init/bridge attach sequence, thus only parse the first endpoints instead of recursing. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_drv.c | 48 +++++-------------------------- 1 file changed, 7 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 92346653223f..1a4cf910c6a0 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -449,46 +449,6 @@ static int compare_of(struct device *dev, void *data) return dev->of_node == data; } -/* Possible connectors nodes to ignore */ -static const struct of_device_id connectors_match[] = { - { .compatible = "composite-video-connector" }, - { .compatible = "svideo-connector" }, - { .compatible = "hdmi-connector" }, - { .compatible = "dvi-connector" }, - {} -}; - -static int meson_probe_remote(struct platform_device *pdev, - struct component_match **match, - struct device_node *parent, - struct device_node *remote) -{ - struct device_node *ep, *remote_node; - int count = 1; - - /* If node is a connector, return and do not add to match table */ - if (of_match_node(connectors_match, remote)) - return 1; - - component_match_add(&pdev->dev, match, compare_of, remote); - - for_each_endpoint_of_node(remote, ep) { - remote_node = of_graph_get_remote_port_parent(ep); - if (!remote_node || - remote_node == parent || /* Ignore parent endpoint */ - !of_device_is_available(remote_node)) { - of_node_put(remote_node); - continue; - } - - count += meson_probe_remote(pdev, match, remote, remote_node); - - of_node_put(remote_node); - } - - return count; -} - static int meson_drv_probe(struct platform_device *pdev) { struct component_match *match = NULL; @@ -503,8 +463,14 @@ static int meson_drv_probe(struct platform_device *pdev) continue; } - count += meson_probe_remote(pdev, &match, np, remote); + DRM_DEBUG_DRIVER("parent %pOF remote %pOF\n", np, remote); + + DRM_DEBUG_DRIVER("match add %pOF parent %s\n", remote, dev_name(&pdev->dev)); + component_match_add(&pdev->dev, &match, compare_of, remote); + of_node_put(remote); + + ++count; } if (count && !match) From patchwork Mon Sep 7 08:18:25 2020 Content-Type: text/plain; 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Mon, 07 Sep 2020 01:18:38 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch Subject: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Date: Mon, 7 Sep 2020 10:18:25 +0200 Message-Id: <20200907081825.1654-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200907081825.1654-1-narmstrong@baylibre.com> References: <20200907081825.1654-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other Amlogic SoCs. This adds support for the Glue managing the transceiver, mimicing the init flow provided by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the Analog PHY in the proper way. The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock is derived and feeds the ENCL encoder and the VIU pixel reader. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 1 + drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++ 3 files changed, 570 insertions(+) create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig index 9f9281dd49f8..385f6f23839b 100644 --- a/drivers/gpu/drm/meson/Kconfig +++ b/drivers/gpu/drm/meson/Kconfig @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI default y if DRM_MESON select DRM_DW_HDMI imply DRM_DW_HDMI_I2S_AUDIO + +config DRM_MESON_DW_MIPI_DSI + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display" + depends on DRM_MESON + default y if DRM_MESON + select DRM_DW_MIPI_DSI + select GENERIC_PHY_MIPI_DPHY diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 28a519cdf66b..2cc870e91182 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c new file mode 100644 index 000000000000..bbe1294fce7c --- /dev/null +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include