From patchwork Mon Sep 7 09:53:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Zhang X-Patchwork-Id: 11760375 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8CC8592C for ; Mon, 7 Sep 2020 10:02:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5977621473 for ; Mon, 7 Sep 2020 10:02:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Qp7He8HH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5977621473 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Owner; bh=kS89jcTx49Xkod58Q4E0lAbkOOt/jwcrikPaJamwui4=; b=Qp7He8HH26fG49cpTo9TiE7xIc HcpCnKKDpRADrMO1Pj7IKLbAGXEmNh0xiBaIgRq0HtBAHobR1IefpxSjcOFvNRzJVQkZ77UAl0R2x QETi5THG9c/N+ttzgjJqHIRJFACNZtcsK2kXdqJISd3uRz6FgLqQaBemIwYOmhfTT8DXAWYDUCQhs dJqzq+XPO7rFGZ+XTd7OuXJR7ITKlMEYLHD66fP/DrR5L/nrlRNiZXc6o8zL96A13JHuTY8izbtNm sIfdO+KZXbjrHcHrBPHdXEBdLiQ/GCXEbMA7iZ6SBeh9C4jM06w35S/hYbNfSpZokhdvGEncozBYs dfnzgpMg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFDx0-000701-Mt; Mon, 07 Sep 2020 10:00:38 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFDwy-0006zS-QE for linux-arm-kernel@lists.infradead.org; Mon, 07 Sep 2020 10:00:37 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0A2C41A16FB; Mon, 7 Sep 2020 12:00:34 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1582F1A172E; Mon, 7 Sep 2020 12:00:31 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id AF69B402DD; Mon, 7 Sep 2020 12:00:24 +0200 (CEST) From: Joakim Zhang To: will@kernel.org, mark.rutland@arm.com, robin.murphy@arm.com Subject: [PATCH] perf/imx_ddr: Add stop event counters support for i.MX8MP Date: Mon, 7 Sep 2020 17:53:59 +0800 Message-Id: <1599472439-22770-1-git-send-email-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200907_060037_028964_3328445B X-CRM114-Status: GOOD ( 24.15 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [92.121.34.13 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, Joakim Zhang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DDR Perf driver only supports free-running event counters(counter1/2/3) now, this patch adds support for stop event counters. Legacy SoCs: Cycle counter(counter0) is a special counter, only count cycles. When cycle counter overflow, it will lock all counters and generate an interrupt. In ddr_perf_irq_handler, disable cycle counter then all counters would stop at the same time, update all counters' count, then enable cycle counter that all counters count again. During this process, only clear cycle counter, no need to clear event counters since they are free-running counters. They would continue counting after overflow and do/while loop from ddr_perf_event_update can handle event counters overflow case. i.MX8MP: Almost all is the same as legacy SoCs, the only difference is that, event counters are not free-running any more. Like cycle counter, when event counters overflow, they would stop counting unless clear the counter, and no interrupt generate for event counters. So we should clear event counters that let them re-count when cycle counter overflow, which ensure event counters will not lose data. Take one case into consideration, from cycle counter interrupt context, when invoke ddr_perf_counter_enable to clear event counters, but have not set prev_count equal 0 yet. Concurrently, ddr_perf_event_update from another thread context invokes ddr_perf_read_counter to read that event counter value, it will return 0. Delta(new_raw_count - prev_raw_count) calculate is incorrect. So I add a spinlock, for that clear event counters and update event counters never happened concurrently. It is save for cycle counter to clear then update the counter, since it is exactly overflow. This patch adds stop event counters support which would be compatible to free-running event counters. Hi Will, I resend the patch for your review since last mail time span is too long. I am not sure whether it is a formal solution or not. If any better solution, please share me how to implement it? Thanks. Signed-off-by: Joakim Zhang --- drivers/perf/fsl_imx8_ddr_perf.c | 52 +++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 7 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 90884d14f95f..057e361eb391 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #define COUNTER_CNTL 0x0 @@ -82,6 +83,7 @@ struct ddr_pmu { const struct fsl_ddr_devtype_data *devtype_data; int irq; int id; + spinlock_t lock; }; enum ddr_perf_filter_capabilities { @@ -368,16 +370,19 @@ static void ddr_perf_event_update(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; u64 delta, prev_raw_count, new_raw_count; int counter = hwc->idx; + unsigned long flags; - do { - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = ddr_perf_read_counter(pmu, counter); - } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count); + spin_lock_irqsave(&pmu->lock, flags); + + prev_raw_count = local64_read(&hwc->prev_count); + new_raw_count = ddr_perf_read_counter(pmu, counter); delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; local64_add(delta, &event->count); + local64_set(&hwc->prev_count, new_raw_count); + + spin_unlock_irqrestore(&pmu->lock, flags); } static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, @@ -404,6 +409,15 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, } } +static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) +{ + int val; + + val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); + + return val & CNTL_OVER ? true : false; +} + static void ddr_perf_event_start(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -534,7 +548,7 @@ static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, static irqreturn_t ddr_perf_irq_handler(int irq, void *p) { - int i; + int i, ret; struct ddr_pmu *pmu = (struct ddr_pmu *) p; struct perf_event *event, *cycle_event = NULL; @@ -546,7 +560,7 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) /* * When the cycle counter overflows, all counters are stopped, * and an IRQ is raised. If any other counter overflows, it - * continues counting, and no IRQ is raised. + * continues counting (stop counting for i.MX8MP), and no IRQ is raised. * * Cycles occur at least 4 times as often as other events, so we * can update all events on a cycle counter overflow and not @@ -566,6 +580,29 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) cycle_event = event; } + /* Clear event counters to avoid they stop counting when overflow, such as i.MX8MP */ + spin_lock(&pmu->lock); + for (i = 0; i < NUM_COUNTERS; i++) { + if (!pmu->events[i]) + continue; + + event = pmu->events[i]; + + if (event->hw.idx == EVENT_CYCLES_COUNTER) + continue; + + /* check event counters overflow */ + ret = ddr_perf_counter_overflow(pmu, event->hw.idx); + if (ret) + dev_warn(pmu->dev, "Event Counter%d overflow happened, data incorrect!!\n", i); + + /* clear event counters */ + ddr_perf_counter_enable(pmu, event->attr.config, event->hw.idx, true); + + local64_set(&event->hw.prev_count, 0); + } + spin_unlock(&pmu->lock); + ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER, @@ -619,6 +656,7 @@ static int ddr_perf_probe(struct platform_device *pdev) num = ddr_perf_init(pmu, base, &pdev->dev); platform_set_drvdata(pdev, pmu); + spin_lock_init(&pmu->lock); name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", num);