From patchwork Mon Sep 7 14:31:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761539 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8F7A59D for ; Mon, 7 Sep 2020 16:25:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB868206E7 for ; Mon, 7 Sep 2020 16:25:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="lu0duZYy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729838AbgIGOdC (ORCPT ); Mon, 7 Sep 2020 10:33:02 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:55816 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729896AbgIGObz (ORCPT ); Mon, 7 Sep 2020 10:31:55 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087EVm53113911; Mon, 7 Sep 2020 09:31:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599489108; bh=9zdhcOMR7Ccf+ysTWrNasl7P6ckqRz+nS1O8WjwH018=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lu0duZYyQh7/VdKn07lhW1meZp3a1NzzWpzFzfFAdotOzBNBvc11FBYaJhP9u0Wwf TxR2bhxdmL7aikSAllJu2kS5ytyQL6OjTsY03da+0rubrnviM+aHAeyo8QUjYMH9sW eBNFEL5mV0hrPU8IjJFcZxz2EPSua3dkUZun1FRM= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 087EVmTe095335 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Sep 2020 09:31:48 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:31:47 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:47 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVkNt072909; Mon, 7 Sep 2020 09:31:47 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 1/9] net: ethernet: ti: ale: add cpsw_ale_get_num_entries api Date: Mon, 7 Sep 2020 17:31:35 +0300 Message-ID: <20200907143143.13735-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add cpsw_ale_get_num_entries() API to return number of ALE table entries and update existing drivers to use it. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 10 ++++++---- drivers/net/ethernet/ti/cpsw_ale.c | 5 +++++ drivers/net/ethernet/ti/cpsw_ale.h | 1 + drivers/net/ethernet/ti/cpsw_ethtool.c | 3 ++- 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c index 496dafb25128..6e4d4f9e32e0 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c +++ b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c @@ -572,13 +572,14 @@ static int am65_cpsw_nway_reset(struct net_device *ndev) static int am65_cpsw_get_regs_len(struct net_device *ndev) { struct am65_cpsw_common *common = am65_ndev_to_common(ndev); - u32 i, regdump_len = 0; + u32 ale_entries, i, regdump_len = 0; + ale_entries = cpsw_ale_get_num_entries(common->ale); for (i = 0; i < ARRAY_SIZE(am65_cpsw_regdump); i++) { if (am65_cpsw_regdump[i].hdr.module_id == AM65_CPSW_REGDUMP_MOD_CPSW_ALE_TBL) { regdump_len += sizeof(struct am65_cpsw_regdump_hdr); - regdump_len += common->ale->params.ale_entries * + regdump_len += ale_entries * ALE_ENTRY_WORDS * sizeof(u32); continue; } @@ -592,10 +593,11 @@ static void am65_cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p) { struct am65_cpsw_common *common = am65_ndev_to_common(ndev); - u32 i, j, pos, *reg = p; + u32 ale_entries, i, j, pos, *reg = p; /* update CPSW IP version */ regs->version = AM65_CPSW_REGDUMP_VER; + ale_entries = cpsw_ale_get_num_entries(common->ale); pos = 0; for (i = 0; i < ARRAY_SIZE(am65_cpsw_regdump); i++) { @@ -603,7 +605,7 @@ static void am65_cpsw_get_regs(struct net_device *ndev, if (am65_cpsw_regdump[i].hdr.module_id == AM65_CPSW_REGDUMP_MOD_CPSW_ALE_TBL) { - u32 ale_tbl_len = common->ale->params.ale_entries * + u32 ale_tbl_len = ale_entries * ALE_ENTRY_WORDS * sizeof(u32) + sizeof(struct am65_cpsw_regdump_hdr); reg[pos++] = ale_tbl_len; diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 9ad872bfae3a..a94aef3f54a5 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1079,3 +1079,8 @@ void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) data += ALE_ENTRY_WORDS; } } + +u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) +{ + return ale ? ale->params.ale_entries : 0; +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 6a3cb6898728..735692f066bf 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -119,6 +119,7 @@ int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control); int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, int value); void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data); +u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale); static inline int cpsw_ale_get_vlan_p0_untag(struct cpsw_ale *ale, u16 vid) { diff --git a/drivers/net/ethernet/ti/cpsw_ethtool.c b/drivers/net/ethernet/ti/cpsw_ethtool.c index fa54efe3be63..4d02c5135611 100644 --- a/drivers/net/ethernet/ti/cpsw_ethtool.c +++ b/drivers/net/ethernet/ti/cpsw_ethtool.c @@ -339,7 +339,8 @@ int cpsw_get_regs_len(struct net_device *ndev) { struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); + return cpsw_ale_get_num_entries(cpsw->ale) * + ALE_ENTRY_WORDS * sizeof(u32); } void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p) From patchwork Mon Sep 7 14:31:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761555 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2516B13B1 for ; Mon, 7 Sep 2020 16:29:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 028FC207DE for ; Mon, 7 Sep 2020 16:29:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cEwyQuR0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730574AbgIGQ2G (ORCPT ); Mon, 7 Sep 2020 12:28:06 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:55818 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729898AbgIGObz (ORCPT ); Mon, 7 Sep 2020 10:31:55 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087EVnR7113918; Mon, 7 Sep 2020 09:31:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599489109; bh=EKYl7mQIBm5oIDjkydzatKB4BPZHHjRPDKZKyEOhuak=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cEwyQuR0WBzO4KwlDHzW8fVlOIig4GgwESQBnjcvqR/GH6MA6xJjGQ9c7lMHBl1ue yNbV/OXCWtXoh78oMOJNAz4goVlONfAhQkFL/Swj184vctBecGzQ4Oh4/f0aFTclaF FyuNPZkcH25HQ7hUk74sah7H0sm9bmjwRnFF+JQU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVnun001324; Mon, 7 Sep 2020 09:31:49 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:31:49 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:49 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVmGF072934; Mon, 7 Sep 2020 09:31:49 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 2/9] net: ethernet: ti: ale: add static configuration Date: Mon, 7 Sep 2020 17:31:36 +0300 Message-ID: <20200907143143.13735-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org As existing, as newly introduced CPSW ALE versions have differences in supported features and ALE table formats. Especially it's actual for the recent AM65x/J721E/J7200 SoC and feature AM64x, which supports features like: auto-aging, classifiers, Link aggregation, additional hw filtering, etc. Existing ALE configuration interface is not practical in terms of adding new features and requires consumers to program a lot static parameters. Any attempt to add new options will case endless adding and maintaining different combination of flags and options. Hence CPSW ALE configuration is static and fixed for SoC (or set of SoC) It is reasonable to add support for static ALE configurations inside ALE module. This patch adds static ALE configuration table for different ALE versions and provides option for consumers to select required ALE configuration by providing ALE const char *dev_id identifier. This feature is not enabled by default until existing CPSW drivers will be modified by follow up patches. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 84 +++++++++++++++++++++++++++++- drivers/net/ethernet/ti/cpsw_ale.h | 1 + 2 files changed, 83 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index a94aef3f54a5..766197003971 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -46,6 +46,29 @@ #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 +enum { + CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */ + CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */ + + CPSW_ALE_F_COUNT +}; + +/** + * struct ale_dev_id - The ALE version/SoC specific configuration + * @dev_id: ALE version/SoC id + * @features: features supported by ALE + * @tbl_entries: number of ALE entries + * @major_ver_mask: mask of ALE Major Version Value in ALE_IDVER reg. + * @nu_switch_ale: NU Switch ALE + */ +struct cpsw_ale_dev_id { + const char *dev_id; + u32 features; + u32 tbl_entries; + u32 major_ver_mask; + bool nu_switch_ale; +}; + #define ALE_TABLE_WRITE BIT(31) #define ALE_TYPE_FREE 0 @@ -979,11 +1002,70 @@ void cpsw_ale_stop(struct cpsw_ale *ale) cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } +static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { + { + /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */ + .dev_id = "cpsw", + .tbl_entries = 1024, + .major_ver_mask = 0xff, + }, + { + /* 66ak2h_xgbe */ + .dev_id = "66ak2h-xgbe", + .tbl_entries = 2048, + .major_ver_mask = 0xff, + }, + { + .dev_id = "66ak2el", + .features = CPSW_ALE_F_STATUS_REG, + .major_ver_mask = 0x7, + .nu_switch_ale = true, + }, + { + .dev_id = "66ak2g", + .features = CPSW_ALE_F_STATUS_REG, + .tbl_entries = 64, + .major_ver_mask = 0x7, + .nu_switch_ale = true, + }, + { + .dev_id = "am65x-cpsw2g", + .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, + .tbl_entries = 64, + .major_ver_mask = 0x7, + .nu_switch_ale = true, + }, + { }, +}; + +static const struct +cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id, + const char *dev_id) +{ + if (!dev_id) + return NULL; + + while (id->dev_id) { + if (strcmp(dev_id, id->dev_id) == 0) + return id; + id++; + } + return NULL; +} + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) { + const struct cpsw_ale_dev_id *ale_dev_id; struct cpsw_ale *ale; u32 rev, ale_entries; + ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); + if (ale_dev_id) { + params->ale_entries = ale_dev_id->tbl_entries; + params->major_ver_mask = ale_dev_id->major_ver_mask; + params->nu_switch_ale = ale_dev_id->nu_switch_ale; + } + ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); if (!ale) return ERR_PTR(-ENOMEM); @@ -999,8 +1081,6 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ale->ageout = ale->params.ale_ageout * HZ; rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); - if (!ale->params.major_ver_mask) - ale->params.major_ver_mask = 0xff; ale->version = (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) | ALE_VERSION_MINOR(rev); diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 735692f066bf..53ad4246617e 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -24,6 +24,7 @@ struct cpsw_ale_params { * pass it from caller. */ u32 major_ver_mask; + const char *dev_id; }; struct cpsw_ale { From patchwork Mon Sep 7 14:31:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761147 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E4C6618 for ; Mon, 7 Sep 2020 14:33:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 52A4B20714 for ; Mon, 7 Sep 2020 14:33:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="n/aJ0Ev9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729914AbgIGOdL (ORCPT ); Mon, 7 Sep 2020 10:33:11 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53906 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729900AbgIGOb4 (ORCPT ); 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Mon, 7 Sep 2020 09:31:51 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVo5r072974; Mon, 7 Sep 2020 09:31:50 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 3/9] net: ethernet: ti: cpsw: use dev_id for ale configuration Date: Mon, 7 Sep 2020 17:31:37 +0300 Message-ID: <20200907143143.13735-4-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The previous patch has introduced possibility to select CPSW ALE by using ALE dev_id identifier. Switch TI cpsw driver to use dev_id="cpsw" and perform clean up by removing "ale_entries" configuration code. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 6 ------ drivers/net/ethernet/ti/cpsw_new.c | 1 - drivers/net/ethernet/ti/cpsw_priv.c | 2 +- drivers/net/ethernet/ti/cpsw_priv.h | 2 -- 4 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 4a65edc5a375..9b425f184f3c 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1278,12 +1278,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, } data->channels = prop; - if (of_property_read_u32(node, "ale_entries", &prop)) { - dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n"); - return -EINVAL; - } - data->ale_entries = prop; - if (of_property_read_u32(node, "bd_ram_size", &prop)) { dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n"); return -EINVAL; diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 8ed78577cded..a3528c5c823f 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -1243,7 +1243,6 @@ static int cpsw_probe_dt(struct cpsw_common *cpsw) data->active_slave = 0; data->channels = CPSW_MAX_QUEUES; - data->ale_entries = CPSW_ALE_NUM_ENTRIES; data->dual_emac = true; data->bd_ram_size = CPSW_BD_RAM_SIZE; data->mac_control = 0; diff --git a/drivers/net/ethernet/ti/cpsw_priv.c b/drivers/net/ethernet/ti/cpsw_priv.c index 482a1a451e43..51cc29f39038 100644 --- a/drivers/net/ethernet/ti/cpsw_priv.c +++ b/drivers/net/ethernet/ti/cpsw_priv.c @@ -500,8 +500,8 @@ int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, ale_params.dev = dev; ale_params.ale_ageout = ale_ageout; - ale_params.ale_entries = data->ale_entries; ale_params.ale_ports = CPSW_ALE_PORTS_NUM; + ale_params.dev_id = "cpsw"; cpsw->ale = cpsw_ale_create(&ale_params); if (IS_ERR(cpsw->ale)) { diff --git a/drivers/net/ethernet/ti/cpsw_priv.h b/drivers/net/ethernet/ti/cpsw_priv.h index bf4e179b4ca4..7b7f3596b20d 100644 --- a/drivers/net/ethernet/ti/cpsw_priv.h +++ b/drivers/net/ethernet/ti/cpsw_priv.h @@ -117,7 +117,6 @@ do { \ #define CPSW_MAX_QUEUES 8 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 #define CPSW_ALE_AGEOUT_DEFAULT 10 /* sec */ -#define CPSW_ALE_NUM_ENTRIES 1024 #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 #define CPSW_FIFO_SHAPE_EN_SHIFT 16 #define CPSW_FIFO_RATE_EN_SHIFT 20 @@ -294,7 +293,6 @@ struct cpsw_platform_data { u32 channels; /* number of cpdma channels (symmetric) */ u32 slaves; /* number of slave cpgmac ports */ u32 active_slave;/* time stamping, ethtool and SIOCGMIIPHY slave */ - u32 ale_entries; /* ale table size */ u32 bd_ram_size; /*buffer descriptor ram size */ u32 mac_control; /* Mac control register */ u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ From patchwork Mon Sep 7 14:31:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761549 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B193013B1 for ; Mon, 7 Sep 2020 16:28:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 952A8208C7 for ; Mon, 7 Sep 2020 16:28:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IUhN0vEi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730593AbgIGQZ4 (ORCPT ); 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Mon, 7 Sep 2020 09:31:52 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:52 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVpWP106437; Mon, 7 Sep 2020 09:31:52 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 4/9] net: netcp: ethss: use dev_id for ale configuration Date: Mon, 7 Sep 2020 17:31:38 +0300 Message-ID: <20200907143143.13735-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The previous patch has introduced possibility to select CPSW ALE by using ALE dev_id identifier. Switch TI Keystone 2 NETCP driver to use dev_id and perform clean up by removing "ale_entries" configuration code. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/netcp_ethss.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/ti/netcp_ethss.c b/drivers/net/ethernet/ti/netcp_ethss.c index 28093923a7fb..33c1592d5381 100644 --- a/drivers/net/ethernet/ti/netcp_ethss.c +++ b/drivers/net/ethernet/ti/netcp_ethss.c @@ -51,7 +51,6 @@ #define GBE13_CPTS_OFFSET 0x500 #define GBE13_ALE_OFFSET 0x600 #define GBE13_HOST_PORT_NUM 0 -#define GBE13_NUM_ALE_ENTRIES 1024 /* 1G Ethernet NU SS defines */ #define GBENU_MODULE_NAME "netcp-gbenu" @@ -101,7 +100,6 @@ #define XGBE10_ALE_OFFSET 0x700 #define XGBE10_HW_STATS_OFFSET 0x800 #define XGBE10_HOST_PORT_NUM 0 -#define XGBE10_NUM_ALE_ENTRIES 2048 #define GBE_TIMER_INTERVAL (HZ / 2) @@ -711,7 +709,6 @@ struct gbe_priv { struct netcp_device *netcp_device; struct timer_list timer; u32 num_slaves; - u32 ale_entries; u32 ale_ports; bool enable_ale; u8 max_num_slaves; @@ -3309,7 +3306,6 @@ static int set_xgbe_ethss10_priv(struct gbe_priv *gbe_dev, gbe_dev->cpts_reg = gbe_dev->switch_regs + XGBE10_CPTS_OFFSET; gbe_dev->ale_ports = gbe_dev->max_num_ports; gbe_dev->host_port = XGBE10_HOST_PORT_NUM; - gbe_dev->ale_entries = XGBE10_NUM_ALE_ENTRIES; gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1; /* Subsystem registers */ @@ -3433,7 +3429,6 @@ static int set_gbe_ethss14_priv(struct gbe_priv *gbe_dev, gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET; gbe_dev->ale_ports = gbe_dev->max_num_ports; gbe_dev->host_port = GBE13_HOST_PORT_NUM; - gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES; gbe_dev->stats_en_mask = GBE13_REG_VAL_STAT_ENABLE_ALL; /* Subsystem registers */ @@ -3697,12 +3692,15 @@ static int gbe_probe(struct netcp_device *netcp_device, struct device *dev, ale_params.dev = gbe_dev->dev; ale_params.ale_regs = gbe_dev->ale_reg; ale_params.ale_ageout = GBE_DEFAULT_ALE_AGEOUT; - ale_params.ale_entries = gbe_dev->ale_entries; ale_params.ale_ports = gbe_dev->ale_ports; - if (IS_SS_ID_MU(gbe_dev)) { - ale_params.major_ver_mask = 0x7; - ale_params.nu_switch_ale = true; - } + ale_params.dev_id = "cpsw"; + if (IS_SS_ID_NU(gbe_dev)) + ale_params.dev_id = "66ak2el"; + else if (IS_SS_ID_2U(gbe_dev)) + ale_params.dev_id = "66ak2g"; + else if (IS_SS_ID_XGBE(gbe_dev)) + ale_params.dev_id = "66ak2h-xgbe"; + gbe_dev->ale = cpsw_ale_create(&ale_params); if (IS_ERR(gbe_dev->ale)) { dev_err(gbe_dev->dev, "error initializing ale engine\n"); From patchwork Mon Sep 7 14:31:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C510B13B1 for ; Mon, 7 Sep 2020 16:29:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A078D208C7 for ; Mon, 7 Sep 2020 16:29:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cfSJxA9V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730565AbgIGQ2G (ORCPT ); Mon, 7 Sep 2020 12:28:06 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53912 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729903AbgIGOcx (ORCPT ); Mon, 7 Sep 2020 10:32:53 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087EVscW015797; Mon, 7 Sep 2020 09:31:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599489114; bh=aLrHDDzUSZnntyTRNgcA+XJgDx0ERfOCTms6pbod928=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cfSJxA9VjX4kNisNtiVKVK+pk90QaKvWgn7TSxMQez5jnc4FjuosIJ+1cOsjOnLiy u9l/ZoWC2txxI6km0lvAusOAyVTF6D044z9Qvh/mHD+kPiFHk6tfDonSC2XKZbTKfD U+H+FRiQABu2waEUBxXbZgxdRNCBeVJUMptaMF3w= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 087EVsxL066835 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Sep 2020 09:31:54 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:31:54 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:54 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVrdR106465; Mon, 7 Sep 2020 09:31:54 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 5/9] net: ethernet: ti: am65-cpsw: use dev_id for ale configuration Date: Mon, 7 Sep 2020 17:31:39 +0300 Message-ID: <20200907143143.13735-6-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The previous patch has introduced possibility to select CPSW ALE by using ALE dev_id identifier. Switch TI TI AM65x/J721E CPSW NUSS driver to use dev_id. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 9baf3f3da91e..bec47e794359 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2131,10 +2131,9 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) /* init common data */ ale_params.dev = dev; ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; - ale_params.ale_entries = 0; ale_params.ale_ports = common->port_num + 1; ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; - ale_params.nu_switch_ale = true; + ale_params.dev_id = "am65x-cpsw2g"; common->ale = cpsw_ale_create(&ale_params); if (IS_ERR(common->ale)) { From patchwork Mon Sep 7 14:31:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF3B159D for ; Mon, 7 Sep 2020 16:28:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B26B4208C7 for ; Mon, 7 Sep 2020 16:28:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Dprr/Pdy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729980AbgIGQ2F (ORCPT ); Mon, 7 Sep 2020 12:28:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:53916 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729905AbgIGOcx (ORCPT ); Mon, 7 Sep 2020 10:32:53 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087EVujc015802; Mon, 7 Sep 2020 09:31:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599489116; bh=vSX2SLuTk0cAacN2wnopN/GO0s/2FaryB38zuY2OUQw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Dprr/PdyQCskZDYmd0/cJ+hbQ/mqcgP3JNL70Iq0CTl8DWVxjHXrTSYLOOGiLTzzK h14eozt3QFZYAmDXWX+bBg5Ae6S0u0pVUf6TyezJ5CjiXxfk5ieQVcDRBAh6qEv88m HpGboZJNYsXkQ72paQnm7T4N/gkEWz9C4m6Zwha8= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVuZh001425; Mon, 7 Sep 2020 09:31:56 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:31:56 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:56 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVtvu106496; Mon, 7 Sep 2020 09:31:55 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 6/9] net: ethernet: ti: ale: make usage of ale dev_id mandatory Date: Mon, 7 Sep 2020 17:31:40 +0300 Message-ID: <20200907143143.13735-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hence all existing driver updated to use ALE dev_id the usage of ale dev_id can be made mandatory and cpsw_ale_create() can be updated to use "features" property from ALE static configuration. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 28 +++++++++++++--------------- drivers/net/ethernet/ti/cpsw_ale.h | 1 + 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 766197003971..524920a4bff0 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -83,7 +83,6 @@ struct cpsw_ale_dev_id { #define ALE_TABLE_SIZE_MULTIPLIER 1024 #define ALE_STATUS_SIZE_MASK 0x1f -#define ALE_TABLE_SIZE_DEFAULT 64 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) { @@ -1060,11 +1059,12 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) u32 rev, ale_entries; ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); - if (ale_dev_id) { - params->ale_entries = ale_dev_id->tbl_entries; - params->major_ver_mask = ale_dev_id->major_ver_mask; - params->nu_switch_ale = ale_dev_id->nu_switch_ale; - } + if (!ale_dev_id) + return ERR_PTR(-EINVAL); + + params->ale_entries = ale_dev_id->tbl_entries; + params->major_ver_mask = ale_dev_id->major_ver_mask; + params->nu_switch_ale = ale_dev_id->nu_switch_ale; ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); if (!ale) @@ -1079,6 +1079,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ale->params = *params; ale->ageout = ale->params.ale_ageout * HZ; + ale->features = ale_dev_id->features; rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); ale->version = @@ -1088,7 +1089,8 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask), ALE_VERSION_MINOR(rev)); - if (!ale->params.ale_entries) { + if (ale->features & CPSW_ALE_F_STATUS_REG && + !ale->params.ale_entries) { ale_entries = readl_relaxed(ale->params.ale_regs + ALE_STATUS) & ALE_STATUS_SIZE_MASK; @@ -1097,16 +1099,12 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) * table which shows the size as a multiple of 1024 entries. * For these, params.ale_entries will be set to zero. So * read the register and update the value of ale_entries. - * ALE table on NetCP lite, is much smaller and is indicated - * by a value of zero in ALE_STATUS. So use a default value - * of ALE_TABLE_SIZE_DEFAULT for this. Caller is expected - * to set the value of ale_entries for all other versions - * of ALE. + * return error if ale_entries is zero in ALE_STATUS. */ if (!ale_entries) - ale_entries = ALE_TABLE_SIZE_DEFAULT; - else - ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; + return ERR_PTR(-EINVAL); + + ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; ale->params.ale_entries = ale_entries; } dev_info(ale->params.dev, diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 53ad4246617e..27b30802b384 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -32,6 +32,7 @@ struct cpsw_ale { struct timer_list timer; unsigned long ageout; u32 version; + u32 features; /* These bits are different on NetCP NU Switch ALE */ u32 port_mask_bits; u32 port_num_bits; From patchwork Mon Sep 7 14:31:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06FD5618 for ; Mon, 7 Sep 2020 14:33:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2E23215A4 for ; Mon, 7 Sep 2020 14:33:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QbABM8cR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729922AbgIGOdS (ORCPT ); Mon, 7 Sep 2020 10:33:18 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58960 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729819AbgIGOcy (ORCPT ); Mon, 7 Sep 2020 10:32:54 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087EVvim057833; Mon, 7 Sep 2020 09:31:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599489118; bh=HrZ4Mx/oHWVRRLQAVP1FDSf+iiLcOYDsomSCa4jZahw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QbABM8cROcn773eu8TUcXC5IF1fjXWQ8a3xr7D5zW2TKj4dpWJqFvOI3LTW2mJQb8 Kpn+dN8B9EHQP5pCJEWf0mYyfYiZ1zAUYhJdJMfRXcjQoNLeoqlxpaDQ3rOnplcFRg K7H9+FdqkZFgv36AoB7IWKVmAy7ke/f3GEa3byEI= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVvPp001448; Mon, 7 Sep 2020 09:31:57 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:31:57 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:57 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVu2I048692; Mon, 7 Sep 2020 09:31:57 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 7/9] net: ethernet: ti: am65-cpsw: enable hw auto ageing Date: Mon, 7 Sep 2020 17:31:41 +0300 Message-ID: <20200907143143.13735-8-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The AM65x ALE supports HW auto-ageing which can be enabled by programming ageing interval in ALE_AGING_TIMER register. For this CPSW fck_clk frequency has to be know by ALE. This patch extends cpsw_ale_params with bus_freq field and enables ALE HW auto ageing for AM65x CPSW2G ALE version. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 13 +++++ drivers/net/ethernet/ti/am65-cpsw-nuss.h | 1 + drivers/net/ethernet/ti/cpsw_ale.c | 61 +++++++++++++++++++++--- drivers/net/ethernet/ti/cpsw_ale.h | 1 + 4 files changed, 70 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index bec47e794359..501d676fd88b 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include @@ -2038,6 +2039,7 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) struct am65_cpsw_common *common; struct device_node *node; struct resource *res; + struct clk *clk; int ret, i; common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); @@ -2086,6 +2088,16 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) if (!common->ports) return -ENOMEM; + clk = devm_clk_get(dev, "fck"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + + if (ret != -EPROBE_DEFER) + dev_err(dev, "error getting fck clock %d\n", ret); + return ret; + } + common->bus_freq = clk_get_rate(clk); + pm_runtime_enable(dev); ret = pm_runtime_get_sync(dev); if (ret < 0) { @@ -2134,6 +2146,7 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) ale_params.ale_ports = common->port_num + 1; ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; ale_params.dev_id = "am65x-cpsw2g"; + ale_params.bus_freq = common->bus_freq; common->ale = cpsw_ale_create(&ale_params); if (IS_ERR(common->ale)) { diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index 94f666ea0e53..993e1d4d3222 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -106,6 +106,7 @@ struct am65_cpsw_common { u32 nuss_ver; u32 cpsw_ver; + unsigned long bus_freq; bool pf_p0_rx_ptype_rrobin; struct am65_cpts *cpts; int est_enabled; diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 524920a4bff0..7b54e9911b1e 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -32,6 +32,7 @@ #define ALE_STATUS 0x04 #define ALE_CONTROL 0x08 #define ALE_PRESCALE 0x10 +#define ALE_AGING_TIMER 0x14 #define ALE_UNKNOWNVLAN 0x18 #define ALE_TABLE_CONTROL 0x20 #define ALE_TABLE 0x34 @@ -46,6 +47,9 @@ #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 +/* ALE_AGING_TIMER */ +#define ALE_AGING_TIMER_MASK GENMASK(23, 0) + enum { CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */ CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */ @@ -982,21 +986,66 @@ static void cpsw_ale_timer(struct timer_list *t) } } +static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale) +{ + u32 aging_timer; + + aging_timer = ale->params.bus_freq / 1000000; + aging_timer *= ale->params.ale_ageout; + + if (aging_timer & ~ALE_AGING_TIMER_MASK) { + aging_timer = ALE_AGING_TIMER_MASK; + dev_warn(ale->params.dev, + "ALE aging timer overflow, set to max\n"); + } + + writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER); +} + +static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale) +{ + writel(0, ale->params.ale_regs + ALE_AGING_TIMER); +} + +static void cpsw_ale_aging_start(struct cpsw_ale *ale) +{ + if (!ale->params.ale_ageout) + return; + + if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { + cpsw_ale_hw_aging_timer_start(ale); + return; + } + + timer_setup(&ale->timer, cpsw_ale_timer, 0); + ale->timer.expires = jiffies + ale->ageout; + add_timer(&ale->timer); +} + +static void cpsw_ale_aging_stop(struct cpsw_ale *ale) +{ + if (!ale->params.ale_ageout) + return; + + if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { + cpsw_ale_hw_aging_timer_stop(ale); + return; + } + + del_timer_sync(&ale->timer); +} + void cpsw_ale_start(struct cpsw_ale *ale) { cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1); cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); - timer_setup(&ale->timer, cpsw_ale_timer, 0); - if (ale->ageout) { - ale->timer.expires = jiffies + ale->ageout; - add_timer(&ale->timer); - } + cpsw_ale_aging_start(ale); } void cpsw_ale_stop(struct cpsw_ale *ale) { - del_timer_sync(&ale->timer); + cpsw_ale_aging_stop(ale); cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 27b30802b384..9c6da58183c9 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -25,6 +25,7 @@ struct cpsw_ale_params { */ u32 major_ver_mask; const char *dev_id; + unsigned long bus_freq; }; struct cpsw_ale { From patchwork Mon Sep 7 14:31:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 179CB59D for ; Mon, 7 Sep 2020 16:28:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5F9D208C7 for ; Mon, 7 Sep 2020 16:28:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="sAySucem" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729924AbgIGQZw (ORCPT ); Mon, 7 Sep 2020 12:25:52 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39226 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729906AbgIGOcz (ORCPT ); Mon, 7 Sep 2020 10:32:55 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087EVxV9078601; Mon, 7 Sep 2020 09:31:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599489119; bh=T0vEyaZIzK+YOhVL1aT2Hj7/oC3d1nw3F+zKDemup3A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sAySucemIdR0gWvIWqyaP7EOrbj9EC0r69XbDvO5s3TeKm4ES6Jnk0DYk5aB0zLHP GdPuhJt6pQzP4eY6oyXV6Q+bdW1OePqEOAH4zooPyHQZCnI6jNZIkwS0sfA0P2GFeJ docmuzVpv1OnNK/jyFGyJkI7F+qcqUReernypGZY= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 087EVxgA095485 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Sep 2020 09:31:59 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:31:59 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:31:59 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EVwPe106549; Mon, 7 Sep 2020 09:31:58 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 8/9] net: ethernet: ti: ale: switch to use tables for vlan entry description Date: Mon, 7 Sep 2020 17:31:42 +0300 Message-ID: <20200907143143.13735-9-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The ALE VLAN entries are too much differ between different TI CPSW ALE versions. So, handling them using flags, defines and get/set functions became over-complicated. This patch introduces tables to describe the ALE VLAN entries fields, which are different between TI CPSW ALE versions, and new get/set access functions. It also allows to detect incorrect access to not available ALL entry fields. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 239 ++++++++++++++++++++++------- drivers/net/ethernet/ti/cpsw_ale.h | 3 + 2 files changed, 188 insertions(+), 54 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7b54e9911b1e..0dd0c3329dee 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -50,6 +50,18 @@ /* ALE_AGING_TIMER */ #define ALE_AGING_TIMER_MASK GENMASK(23, 0) +/** + * struct ale_entry_fld - The ALE tbl entry field description + * @start_bit: field start bit + * @num_bits: field bit length + * @flags: field flags + */ +struct ale_entry_fld { + u8 start_bit; + u8 num_bits; + u8 flags; +}; + enum { CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */ CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */ @@ -64,6 +76,7 @@ enum { * @tbl_entries: number of ALE entries * @major_ver_mask: mask of ALE Major Version Value in ALE_IDVER reg. * @nu_switch_ale: NU Switch ALE + * @vlan_entry_tbl: ALE vlan entry fields description tbl */ struct cpsw_ale_dev_id { const char *dev_id; @@ -71,6 +84,7 @@ struct cpsw_ale_dev_id { u32 tbl_entries; u32 major_ver_mask; bool nu_switch_ale; + const struct ale_entry_fld *vlan_entry_tbl; }; #define ALE_TABLE_WRITE BIT(31) @@ -132,6 +146,51 @@ static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \ cpsw_ale_set_field(ale_entry, start, bits, value); \ } +enum { + ALE_ENT_VID_MEMBER_LIST = 0, + ALE_ENT_VID_UNREG_MCAST_MSK, + ALE_ENT_VID_REG_MCAST_MSK, + ALE_ENT_VID_FORCE_UNTAGGED_MSK, + ALE_ENT_VID_UNREG_MCAST_IDX, + ALE_ENT_VID_REG_MCAST_IDX, + ALE_ENT_VID_LAST, +}; + +#define ALE_FLD_ALLOWED BIT(0) +#define ALE_FLD_SIZE_PORT_MASK_BITS BIT(1) +#define ALE_FLD_SIZE_PORT_NUM_BITS BIT(2) + +#define ALE_ENTRY_FLD(id, start, bits) \ +[id] = { \ + .start_bit = start, \ + .num_bits = bits, \ + .flags = ALE_FLD_ALLOWED, \ +} + +#define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start) \ +[id] = { \ + .start_bit = start, \ + .num_bits = 0, \ + .flags = ALE_FLD_ALLOWED | \ + ALE_FLD_SIZE_PORT_MASK_BITS, \ +} + +/* dm814x, am3/am4/am5, k2hk */ +static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = { + ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3), + ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3), + ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3), + ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3), +}; + +/* k2e/k2l, k3 am65/j721e cpsw2g */ +static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = { + ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), + ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3), + ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), + ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3), +}; + DEFINE_ALE_FIELD(entry_type, 60, 2) DEFINE_ALE_FIELD(vlan_id, 48, 12) DEFINE_ALE_FIELD(mcast_state, 62, 2) @@ -141,17 +200,76 @@ DEFINE_ALE_FIELD(ucast_type, 62, 2) DEFINE_ALE_FIELD1(port_num, 66) DEFINE_ALE_FIELD(blocked, 65, 1) DEFINE_ALE_FIELD(secure, 64, 1) -DEFINE_ALE_FIELD1(vlan_untag_force, 24) -DEFINE_ALE_FIELD1(vlan_reg_mcast, 16) -DEFINE_ALE_FIELD1(vlan_unreg_mcast, 8) -DEFINE_ALE_FIELD1(vlan_member_list, 0) DEFINE_ALE_FIELD(mcast, 40, 1) -/* ALE NetCP nu switch specific */ -DEFINE_ALE_FIELD(vlan_unreg_mcast_idx, 20, 3) -DEFINE_ALE_FIELD(vlan_reg_mcast_idx, 44, 3) #define NU_VLAN_UNREG_MCAST_IDX 1 +static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale, + u32 *ale_entry, + const struct ale_entry_fld *entry_tbl, + int fld_id) +{ + const struct ale_entry_fld *entry_fld; + u32 bits; + + if (!ale || !ale_entry) + return -EINVAL; + + entry_fld = &entry_tbl[fld_id]; + if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { + dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id); + return -ENOENT; + } + + bits = entry_fld->num_bits; + if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) + bits = ale->port_mask_bits; + + return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits); +} + +static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale, + u32 *ale_entry, + const struct ale_entry_fld *entry_tbl, + int fld_id, + u32 value) +{ + const struct ale_entry_fld *entry_fld; + u32 bits; + + if (!ale || !ale_entry) + return; + + entry_fld = &entry_tbl[fld_id]; + if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { + dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id); + return; + } + + bits = entry_fld->num_bits; + if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) + bits = ale->port_mask_bits; + + cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value); +} + +static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale, + u32 *ale_entry, + int fld_id) +{ + return cpsw_ale_entry_get_fld(ale, ale_entry, + ale->vlan_entry_tbl, fld_id); +} + +static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale, + u32 *ale_entry, + int fld_id, + u32 value) +{ + cpsw_ale_entry_set_fld(ale, ale_entry, + ale->vlan_entry_tbl, fld_id, value); +} + /* The MAC address field in the ALE entry cannot be macroized as above */ static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) { @@ -446,19 +564,22 @@ static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, int idx; /* Set VLAN registered multicast flood mask */ - idx = cpsw_ale_get_vlan_reg_mcast_idx(ale_entry); + idx = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_REG_MCAST_IDX); writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); /* Set VLAN unregistered multicast flood mask */ - idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry); + idx = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_IDX); writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); } static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, u16 vid, int untag_mask) { - cpsw_ale_set_vlan_untag_force(ale_entry, - untag_mask, ale->vlan_field_bits); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_FORCE_UNTAGGED_MSK, + untag_mask); if (untag_mask & ALE_PORT_HOST) bitmap_set(ale->p0_untag_vid_mask, vid, 1); else @@ -480,17 +601,19 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); if (!ale->params.nu_switch_ale) { - cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, - ale->vlan_field_bits); - cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, - ale->vlan_field_bits); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); } else { - cpsw_ale_set_vlan_unreg_mcast_idx(ale_entry, - NU_VLAN_UNREG_MCAST_IDX); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_IDX, + NU_VLAN_UNREG_MCAST_IDX); cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); } - cpsw_ale_set_vlan_member_list(ale_entry, port_mask, - ale->vlan_field_bits); + + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_MEMBER_LIST, port_mask); if (idx < 0) idx = cpsw_ale_match_free(ale); @@ -509,20 +632,20 @@ static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry, int reg_mcast, unreg_mcast; int members, untag; - members = cpsw_ale_get_vlan_member_list(ale_entry, - ale->vlan_field_bits); + members = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_MEMBER_LIST); members &= ~port_mask; if (!members) { cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); return; } - untag = cpsw_ale_get_vlan_untag_force(ale_entry, - ale->vlan_field_bits); - reg_mcast = cpsw_ale_get_vlan_reg_mcast(ale_entry, - ale->vlan_field_bits); - unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry, - ale->vlan_field_bits); + untag = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_FORCE_UNTAGGED_MSK); + reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_REG_MCAST_MSK); + unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK); untag &= members; reg_mcast &= members; unreg_mcast &= members; @@ -530,16 +653,16 @@ static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry, cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); if (!ale->params.nu_switch_ale) { - cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, - ale->vlan_field_bits); - cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, - ale->vlan_field_bits); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); } else { cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); } - cpsw_ale_set_vlan_member_list(ale_entry, members, - ale->vlan_field_bits); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_MEMBER_LIST, members); } int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) @@ -577,15 +700,15 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, if (idx >= 0) cpsw_ale_read(ale, idx, ale_entry); - vlan_members = cpsw_ale_get_vlan_member_list(ale_entry, - ale->vlan_field_bits); - reg_mcast_members = cpsw_ale_get_vlan_reg_mcast(ale_entry, - ale->vlan_field_bits); + vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_MEMBER_LIST); + reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_REG_MCAST_MSK); unreg_mcast_members = - cpsw_ale_get_vlan_unreg_mcast(ale_entry, - ale->vlan_field_bits); - untag_members = cpsw_ale_get_vlan_untag_force(ale_entry, - ale->vlan_field_bits); + cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK); + untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_FORCE_UNTAGGED_MSK); vlan_members |= port_mask; untag_members = (untag_members & ~port_mask) | untag_mask; @@ -618,14 +741,15 @@ void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, continue; unreg_members = - cpsw_ale_get_vlan_unreg_mcast(ale_entry, - ale->vlan_field_bits); + cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK); if (add) unreg_members |= unreg_mcast_mask; else unreg_members &= ~unreg_mcast_mask; - cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_members, - ale->vlan_field_bits); + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK, + unreg_members); cpsw_ale_write(ale, idx, ale_entry); } } @@ -635,15 +759,15 @@ static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry, { int unreg_mcast; - unreg_mcast = - cpsw_ale_get_vlan_unreg_mcast(ale_entry, - ale->vlan_field_bits); + unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK); if (allmulti) unreg_mcast |= ALE_PORT_HOST; else unreg_mcast &= ~ALE_PORT_HOST; - cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, - ale->vlan_field_bits); + + cpsw_ale_vlan_set_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); } static void @@ -653,7 +777,8 @@ cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry, int unreg_mcast; int idx; - idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry); + idx = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_UNREG_MCAST_IDX); unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); @@ -677,9 +802,9 @@ void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) type = cpsw_ale_get_entry_type(ale_entry); if (type != ALE_TYPE_VLAN) continue; - vlan_members = - cpsw_ale_get_vlan_member_list(ale_entry, - ale->vlan_field_bits); + + vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, + ALE_ENT_VID_MEMBER_LIST); if (port != -1 && !(vlan_members & BIT(port))) continue; @@ -1056,18 +1181,21 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .dev_id = "cpsw", .tbl_entries = 1024, .major_ver_mask = 0xff, + .vlan_entry_tbl = vlan_entry_cpsw, }, { /* 66ak2h_xgbe */ .dev_id = "66ak2h-xgbe", .tbl_entries = 2048, .major_ver_mask = 0xff, + .vlan_entry_tbl = vlan_entry_cpsw, }, { .dev_id = "66ak2el", .features = CPSW_ALE_F_STATUS_REG, .major_ver_mask = 0x7, .nu_switch_ale = true, + .vlan_entry_tbl = vlan_entry_nu, }, { .dev_id = "66ak2g", @@ -1075,6 +1203,7 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .tbl_entries = 64, .major_ver_mask = 0x7, .nu_switch_ale = true, + .vlan_entry_tbl = vlan_entry_nu, }, { .dev_id = "am65x-cpsw2g", @@ -1082,6 +1211,7 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .tbl_entries = 64, .major_ver_mask = 0x7, .nu_switch_ale = true, + .vlan_entry_tbl = vlan_entry_nu, }, { }, }; @@ -1129,6 +1259,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ale->params = *params; ale->ageout = ale->params.ale_ageout * HZ; ale->features = ale_dev_id->features; + ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl; rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); ale->version = diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 9c6da58183c9..5e4a69662c5f 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -28,6 +28,8 @@ struct cpsw_ale_params { unsigned long bus_freq; }; +struct ale_entry_fld; + struct cpsw_ale { struct cpsw_ale_params params; struct timer_list timer; @@ -39,6 +41,7 @@ struct cpsw_ale { u32 port_num_bits; u32 vlan_field_bits; unsigned long *p0_untag_vid_mask; + const struct ale_entry_fld *vlan_entry_tbl; }; enum cpsw_ale_control { From patchwork Mon Sep 7 14:31:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 11761559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1FB2513B1 for ; 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Mon, 7 Sep 2020 09:32:01 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:32:00 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:32:00 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087EW08r106572; Mon, 7 Sep 2020 09:32:00 -0500 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Vignesh Raghavendra , Murali Karicheri CC: Sekhar Nori , , , Grygorii Strashko Subject: [PATCH net-next v2 9/9] net: ethernet: ti: ale: add support for multi port k3 cpsw versions Date: Mon, 7 Sep 2020 17:31:43 +0300 Message-ID: <20200907143143.13735-10-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907143143.13735-1-grygorii.strashko@ti.com> References: <20200907143143.13735-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The TI J721E (CPSW9g) ALE version is similar, in general, to Sitara AM3/4/5 CPSW ALE, but has more extended functions and different ALE VLAN entry format. This patch adds support for for multi port TI J721E (CPSW9g) ALE variant. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 0dd0c3329dee..a6a455c32628 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -191,6 +191,14 @@ static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = { ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3), }; +/* K3 j721e/j7200 cpsw9g/5g, am64x cpsw3g */ +static const struct ale_entry_fld vlan_entry_k3_cpswxg[] = { + ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), + ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_UNREG_MCAST_MSK, 12), + ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), + ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_REG_MCAST_MSK, 36), +}; + DEFINE_ALE_FIELD(entry_type, 60, 2) DEFINE_ALE_FIELD(vlan_id, 48, 12) DEFINE_ALE_FIELD(mcast_state, 62, 2) @@ -1213,6 +1221,12 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, + { + .dev_id = "j721e-cpswxg", + .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, + .major_ver_mask = 0x7, + .vlan_entry_tbl = vlan_entry_k3_cpswxg, + }, { }, };