From patchwork Tue Sep 8 10:24:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0BC615E4 for ; Tue, 8 Sep 2020 10:28:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7856721D79 for ; Tue, 8 Sep 2020 10:28:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Jl9X2oZV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7856721D79 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CzDFi5r+IKHHmqjXtcGsvu644xqtIBgmaTllSxLrnhM=; b=Jl9X2oZVyD8fbs68G/6DEmhbU0 sibD/981OXcL8Cz5WMGhuV30AsopyRfbE+qOaXo2ORzINw0AnaEsUcB4apXP13m06wbvYIcaH6Gyz a0f5IANnrpJQ26P1bpZmIJu/+6UJDww9rRS2eyEFBzZLsGHXq5VBfzFqfBQaON0F/MGfzJJ4iq25r rPKb7yD1UbGsIK03m2AY1//ON7kejivs51H4LWoXfgQRDnc2d1suY3GtkbxhbF/IoGHbuE+qsMc6j 7O2MJK5FqRg8ABJ3BadzyuqwHti7WghX8D/qHoTnhqfgi2JEuneu0k5BFDcb6fJO4s+BeDJk1mgOz cALZuf9Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFapL-0000nk-Vf; Tue, 08 Sep 2020 10:26:16 +0000 Received: from inva021.nxp.com ([92.121.34.21]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFapD-0000kA-97 for linux-arm-kernel@lists.infradead.org; Tue, 08 Sep 2020 10:26:08 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7333320021E; Tue, 8 Sep 2020 12:26:06 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 64A29201595; Tue, 8 Sep 2020 12:26:06 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 9677D2036D; Tue, 8 Sep 2020 12:26:05 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl Date: Tue, 8 Sep 2020 13:24:38 +0300 Message-Id: <1599560691-3763-2-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062607_590368_6A51B02E X-CRM114-Status: GOOD ( 11.01 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In the reference manual the actual name is Audio BLK_CTL. Lets make it more obvious here by renaming from audiomix to audio_blk_ctl. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fb..89c67b7 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,66 +324,66 @@ #define IMX8MP_CLK_END 313 -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG 25 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG 31 +#define IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY 38 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL 54 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL 56 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT 58 -#define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 #endif From patchwork Tue Sep 8 10:24:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763141 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D13D746 for ; Tue, 8 Sep 2020 10:26:36 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E35420C09 for ; Tue, 8 Sep 2020 10:26:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="x5oBWGyQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5E35420C09 Authentication-Results: mail.kernel.org; dmarc=fail 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12:26:06 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs Date: Tue, 8 Sep 2020 13:24:39 +0300 Message-Id: <1599560691-3763-3-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062608_199791_AA3E85D9 X-CRM114-Status: GOOD ( 11.35 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/reset/imx8mp-reset.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 2e8c910..6c7f17f 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -47,4 +47,9 @@ #define IMX8MP_RESET_NUM 38 +#define IMX8MP_AUDIO_BLK_CTL_EARC_RESET 0 +#define IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET 1 + +#define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 + #endif From patchwork Tue Sep 8 10:24:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A86E6746 for ; Tue, 8 Sep 2020 10:28:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 784D021532 for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFapV-0000qq-Pz; Tue, 08 Sep 2020 10:26:25 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFapF-0000l3-FK for linux-arm-kernel@lists.infradead.org; Tue, 08 Sep 2020 10:26:10 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 07BD91A032D; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EC12A1A0335; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 3DBB820327; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate Date: Tue, 8 Sep 2020 13:24:40 +0300 Message-Id: <1599560691-3763-4-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062609_694838_C13AAE07 X-CRM114-Status: GOOD ( 11.04 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.13 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 89c67b7..5fc2c40 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -322,7 +322,17 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 313 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 314 +#define IMX8MP_CLK_SAI1_ROOT 315 +#define IMX8MP_CLK_SAI2_ROOT 316 +#define IMX8MP_CLK_SAI3_ROOT 317 +#define IMX8MP_CLK_SAI5_ROOT 318 +#define IMX8MP_CLK_SAI6_ROOT 319 +#define IMX8MP_CLK_SAI7_ROOT 320 +#define IMX8MP_CLK_PDM_ROOT 321 + +#define IMX8MP_CLK_END 322 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 From patchwork Tue Sep 8 10:24:41 2020 Content-Type: text/plain; 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Tue, 08 Sep 2020 10:26:10 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BCEFD1A0335; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id ABEB91A032F; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 078FE2036D; Tue, 8 Sep 2020 12:26:07 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs Date: Tue, 8 Sep 2020 13:24:41 +0300 Message-Id: <1599560691-3763-5-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062609_742347_4ADBC4AB X-CRM114-Status: GOOD ( 10.76 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.13 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 5fc2c40..12632fa 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -396,4 +396,32 @@ #define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK 0 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF 1 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK 2 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK 3 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL 4 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB 5 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC 6 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB 7 +#define IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK 8 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK 9 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK 10 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL 11 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB 12 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR 13 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI 14 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB 15 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR 16 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI 17 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB 18 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR 19 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI 20 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB 21 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2 22 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI 23 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI 24 + +#define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 + #endif From patchwork Tue Sep 8 10:24:42 2020 Content-Type: text/plain; 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Tue, 08 Sep 2020 10:26:13 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7B5711A034D; Tue, 8 Sep 2020 12:26:09 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6E96E1A0344; Tue, 8 Sep 2020 12:26:09 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id BBBF220327; Tue, 8 Sep 2020 12:26:08 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs Date: Tue, 8 Sep 2020 13:24:42 +0300 Message-Id: <1599560691-3763-6-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062610_538336_2811B095 X-CRM114-Status: GOOD ( 10.57 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.13 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/reset/imx8mp-reset.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 6c7f17f..ba70248 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -52,4 +52,32 @@ #define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK 0 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF 1 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK 3 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL 4 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB 5 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC 6 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB 7 +#define IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK 8 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK 9 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK 10 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL 11 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB 12 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR 13 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI 14 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB 15 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR 16 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI 17 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB 18 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR 19 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI 20 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB 21 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2 22 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI 23 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI 24 + +#define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 + #endif From patchwork Tue Sep 8 10:24:43 2020 Content-Type: text/plain; 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Tue, 08 Sep 2020 10:26:14 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3CA701A035F; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2ED6A1A0339; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 7E33220327; Tue, 8 Sep 2020 12:26:09 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs Date: Tue, 8 Sep 2020 13:24:43 +0300 Message-Id: <1599560691-3763-7-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062611_409946_5BFAE4A7 X-CRM114-Status: GOOD ( 10.94 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.13 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/clock/imx8mp-clock.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 12632fa..de7d522 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -424,4 +424,44 @@ #define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK 0 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK 1 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK 2 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK 3 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK 4 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK 5 +#define IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK 6 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK 7 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK 8 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK 9 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK 10 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK 11 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK 12 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK 13 +#define IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK 14 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK 15 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK 16 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK 17 +#define IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK 18 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK 19 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK 20 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK 21 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK 22 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK 23 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK 24 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK 26 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK 27 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK 28 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK 29 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK 30 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK 31 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK 32 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK 33 +#define IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL 34 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL 35 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL 36 + +#define IMX8MP_CLK_HDMI_BLK_CTL_END 37 + #endif From patchwork Tue Sep 8 10:24:44 2020 Content-Type: text/plain; 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Tue, 08 Sep 2020 10:26:14 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 05E632011C1; Tue, 8 Sep 2020 12:26:11 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id EDEF7201198; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 3EB4420327; Tue, 8 Sep 2020 12:26:10 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs Date: Tue, 8 Sep 2020 13:24:44 +0300 Message-Id: <1599560691-3763-8-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062612_041172_10E7013D X-CRM114-Status: GOOD ( 10.20 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org These will be used imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Dong Aisheng --- include/dt-bindings/reset/imx8mp-reset.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index ba70248..eb9ed21 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -80,4 +80,16 @@ #define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET 0 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET 1 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET 2 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PVI_RESET 3 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET 4 +#define IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET 5 +#define IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET 6 +#define IMX8MP_HDMI_BLK_CTL_LCDIF_RESET 7 + +#define IMX8MP_HDMI_BLK_CTL_RESET_NUM 8 + + #endif From patchwork Tue Sep 8 10:24:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF7E8746 for ; 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Tue, 8 Sep 2020 12:26:11 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 0B28120327; Tue, 8 Sep 2020 12:26:11 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 08/14] clk: imx8mp: Add audio shared gate Date: Tue, 8 Sep 2020 13:24:45 +0300 Message-Id: <1599560691-3763-9-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062612_929155_CF4FD190 X-CRM114-Status: GOOD ( 11.80 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT Signed-off-by: Abel Vesa Reviewed-by: Dong Aisheng --- drivers/clk/imx/clk-imx8mp.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 12ce477..6812a01 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -17,6 +17,7 @@ static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -725,7 +726,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, From patchwork Tue Sep 8 10:24:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89A88138E for ; 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Tue, 8 Sep 2020 12:26:12 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id C0E0C20327; Tue, 8 Sep 2020 12:26:11 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL Date: Tue, 8 Sep 2020 13:24:46 +0300 Message-Id: <1599560691-3763-10-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062613_578581_BEA88B1B X-CRM114-Status: GOOD ( 14.92 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.13 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Document the i.MX BLK_CTL with its devicetree properties. Signed-off-by: Abel Vesa Reviewed-by: Dong Aisheng Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml new file mode 100644 index 00000000..5e9eb40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTL + +maintainers: + - Abel Vesa + +description: + i.MX BLK_CTL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. Because it usually contains + clocks amongst other things, it needs access to the i.MX clocks + API. All the other functionalities it provides can work just fine + from the clock subsystem tree. + +properties: + compatible: + items: + - enum: + - fsl,imx8mp-audio-blk-ctl + - fsl,imx8mp-hdmi-blk-ctl + - fsl,imx8mp-media-blk-ctl + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x10000>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Tue Sep 8 10:24:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E36D746 for ; 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bh=0ZIE2ojhhIyN1xbsaHIoTkFROGyhAm0WmvD5wHkyCFo=; b=X1Vl4jueO3IpzEhq/2lxoa9tvx XzdE1ParWVdA9DlBipC4UjWo1Zq9q5pBkbQHi8SlhJb4dx8etST2/GjIOny6QAfcnsmzJPv3x+2FL NbDtC0Uk8Yt9R/V70MIBrvn5o4esVh71yoexDd3hA/Wh3Py5CI/au5TxaZS97wMosRSfONEhCQaiN RAu+jTuJe/X5SG3BQn1MwZ+Z9tud+r2bl2ljxRxOlNEAnFUtCw0UI4XVUUT84xuZnVJx9rzOvUi9J UHTh1WI5jwvtRJdyXbLXjefeA0sejU/JZzQK3qR8kJZ3K8wI+4Fl4ZaujEKZvfQYgnpil/nMu+f1y D5NB0ZMA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFaqo-0001Hq-HD; Tue, 08 Sep 2020 10:27:46 +0000 Received: from inva021.nxp.com ([92.121.34.21]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFapK-0000nX-5K for linux-arm-kernel@lists.infradead.org; Tue, 08 Sep 2020 10:26:18 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4D010201592; Tue, 8 Sep 2020 12:26:13 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3497820158F; Tue, 8 Sep 2020 12:26:13 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 8465120327; Tue, 8 Sep 2020 12:26:12 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 10/14] clk: imx: Add generic blk-ctl driver Date: Tue, 8 Sep 2020 13:24:47 +0300 Message-Id: <1599560691-3763-11-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062614_469661_9A430861 X-CRM114-Status: GOOD ( 25.77 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The i.MX8MP platform introduces a new type of IP which is called BLK_CTL in RM and usually is comprised of some GPRs that are considered too generic to be part of any dedicated IP from that specific subsystem. In general, some of the GPRs have some clock bits, some have reset bits, so in order to be able to use the imx clock API, this needs to be in a clock driver. From there it can use the reset controller API and leave the rest to the syscon. Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl.c | 297 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.h | 80 ++++++++++++ 3 files changed, 378 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctl.c create mode 100644 drivers/clk/imx/clk-blk-ctl.h diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 79e53f2..105c117 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c new file mode 100644 index 00000000..1a6f1eb --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-blk-ctl.h" + +struct imx_reset_hw { + u32 offset; + u32 shift; + u32 mask; + volatile unsigned long asserted; +}; + +struct imx_pm_safekeep_info { + uint32_t *regs_values; + uint32_t *regs_offsets; + uint32_t regs_num; +}; + +struct imx_blk_ctl_drvdata { + void __iomem *base; + struct reset_controller_dev rcdev; + struct imx_reset_hw *rst_hws; + struct imx_pm_safekeep_info pm_info; + + spinlock_t lock; +}; + +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, + bool write) +{ + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; + void __iomem *base = drvdata->base; + int i; + + if (!pm_info->regs_num) + return; + + for (i = 0; i < pm_info->regs_num; i++) { + u32 offset = pm_info->regs_offsets[i]; + + if (write) + writel(pm_info->regs_values[i], base + offset); + else + pm_info->regs_values[i] = readl(base + offset); + } + +} + +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device *dev) +{ + imx_blk_ctl_read_write(dev, false); + + return 0; +} + +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device *dev) +{ + imx_blk_ctl_read_write(dev, true); + + return 0; +} + +const struct dev_pm_ops imx_blk_ctl_pm_ops = { + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, + imx_blk_ctl_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); + +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, + struct imx_blk_ctl_drvdata, rcdev); + unsigned int offset = drvdata->rst_hws[id].offset; + unsigned int shift = drvdata->rst_hws[id].shift; + unsigned int mask = drvdata->rst_hws[id].mask; + void __iomem *reg_addr = drvdata->base + offset; + unsigned long flags; + u32 reg; + + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_get_sync(rcdev->dev); + + spin_lock_irqsave(&drvdata->lock, flags); + + reg = readl(reg_addr); + if (assert) + writel(reg & ~(mask << shift), reg_addr); + else + writel(reg | (mask << shift), reg_addr); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_put(rcdev->dev); + + return 0; +} + +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctl_reset_set(rcdev, id, true); +} + +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctl_reset_set(rcdev, id, false); +} + +static const struct reset_control_ops imx_blk_ctl_reset_ops = { + .assert = imx_blk_ctl_reset_assert, + .deassert = imx_blk_ctl_reset_deassert, +}; + +static int imx_blk_ctl_register_reset_controller(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + int max = dev_data->resets_max; + struct imx_reset_hw *hws; + int i; + + spin_lock_init(&drvdata->lock); + + drvdata->rcdev.owner = THIS_MODULE; + drvdata->rcdev.nr_resets = max; + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; + drvdata->rcdev.of_node = dev->of_node; + drvdata->rcdev.dev = dev; + + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), + GFP_KERNEL); + hws = drvdata->rst_hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; + + if (hw->type != BLK_CTL_RESET) + continue; + + hws[hw->id].offset = hw->offset; + hws[hw->id].shift = hw->shift; + hws[hw->id].mask = hw->mask; + } + + return devm_reset_controller_register(dev, &drvdata->rcdev); +} +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, + struct imx_blk_ctl_hw *hw) +{ + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + void __iomem *base = drvdata->base; + struct clk_hw *clk_hw = NULL; + + switch (hw->type) { + case BLK_CTL_CLK_MUX: + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, + base + hw->offset, + hw->shift, hw->width, + hw->parents, + hw->parents_count, + hw->flags); + break; + case BLK_CTL_CLK_GATE: + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, + base + hw->offset, hw->shift); + break; + case BLK_CTL_CLK_SHARED_GATE: + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, + hw->parents, + base + hw->offset, + hw->shift, + hw->shared_count); + break; + case BLK_CTL_CLK_PLL14XX: + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, + base + hw->offset, hw->pll_tbl); + break; + }; + + return clk_hw; +} + +static int imx_blk_ctl_register_clock_controller(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct clk_hw_onecell_data *clk_hw_data; + struct clk_hw **hws; + int i; + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + dev_data->hws_num), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = dev_data->clocks_max; + hws = clk_hw_data->hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; + + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); + WARN(IS_ERR(hws[hw->id]), "failed to register clock %d", hw->id); + } + + imx_check_clk_hws(hws, dev_data->clocks_max); + + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_hw_data); +} + +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; + u32 regs_num = dev_data->pm_runtime_saved_regs_num; + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; + + if (!dev_data->pm_runtime_saved_regs_num) + return 0; + + pm_info->regs_values = devm_kzalloc(dev, + sizeof(u32) * regs_num, + GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_values))) + return PTR_ERR(pm_info->regs_values); + + pm_info->regs_offsets = kmemdup(regs_offsets, + regs_num * sizeof(u32), GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) + return PTR_ERR(pm_info->regs_offsets); + + pm_info->regs_num = regs_num; + + return 0; +} + +int imx_blk_ctl_probe(struct platform_device *pdev) +{ + struct imx_blk_ctl_drvdata *drvdata; + struct device *dev = &pdev->dev; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (WARN_ON(!drvdata)) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(drvdata->base))) + return PTR_ERR(drvdata->base); + + dev_set_drvdata(dev, drvdata); + + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret = imx_blk_ctl_register_clock_controller(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + + ret = imx_blk_ctl_register_reset_controller(dev); + + pm_runtime_put(dev); + + return ret; +} +EXPORT_SYMBOL_GPL(imx_blk_ctl_probe); diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h new file mode 100644 index 00000000..e5bf723 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MACH_IMX_CLK_BLK_CTL_H +#define __MACH_IMX_CLK_BLK_CTL_H + +enum imx_blk_ctl_hw_type { + BLK_CTL_CLK_MUX, + BLK_CTL_CLK_GATE, + BLK_CTL_CLK_SHARED_GATE, + BLK_CTL_CLK_PLL14XX, + BLK_CTL_RESET, +}; + +struct imx_blk_ctl_hw { + int type; + char *name; + u32 offset; + u32 shift; + u32 mask; + u32 width; + u32 flags; + u32 id; + const void *parents; + u32 parents_count; + int *shared_count; + const struct imx_pll14xx_clk *pll_tbl; +}; + +struct imx_blk_ctl_dev_data { + struct imx_blk_ctl_hw *hws; + u32 hws_num; + + u32 clocks_max; + u32 resets_max; + + u32 pm_runtime_saved_regs_num; + u32 pm_runtime_saved_regs[]; +}; + +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ + { \ + .type = _type, \ + .name = _name, \ + .id = _id, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mask = _mask, \ + .parents = _parents, \ + .parents_count = _parents_count, \ + .flags = _flags, \ + .shared_count = sh_count, \ + .pll_tbl = _pll_tbl, \ + } + +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) + +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) + +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) + +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) + +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) + +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) + +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) + +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; + +int imx_blk_ctl_probe(struct platform_device *pdev); + +#endif From patchwork Tue Sep 8 10:24:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA966746 for ; Tue, 8 Sep 2020 10:28:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A703208C7 for ; Tue, 8 Sep 2020 10:28:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="IJTqH/zV" DMARC-Filter: OpenDMARC Filter v1.3.2 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by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 4490D20327; Tue, 8 Sep 2020 12:26:13 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 11/14] clk: imx: Add blk-ctl driver for i.MX8MP Date: Tue, 8 Sep 2020 13:24:48 +0300 Message-Id: <1599560691-3763-12-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062615_396405_13489B2E X-CRM114-Status: GOOD ( 17.23 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This driver is intended to work with the following BLK_CTL IPs found in i.MX8MP: - Audio - Media - HDMI Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl-imx8mp.c | 313 +++++++++++++++++++++++++++++++++++ 2 files changed, 314 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 105c117..e3aaf76 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o clk-blk-ctl-imx8mp.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git a/drivers/clk/imx/clk-blk-ctl-imx8mp.c b/drivers/clk/imx/clk-blk-ctl-imx8mp.c new file mode 100644 index 00000000..eacecbe --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl-imx8mp.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-blk-ctl.h" + +#define IMX_AUDIO_BLK_CTL_CLKEN0 0x0 +#define IMX_AUDIO_BLK_CTL_CLKEN1 0x4 +#define IMX_AUDIO_BLK_CTL_EARC 0x200 +#define IMX_AUDIO_BLK_CTL_SAI1_MCLK_SEL 0x300 +#define IMX_AUDIO_BLK_CTL_SAI2_MCLK_SEL 0x304 +#define IMX_AUDIO_BLK_CTL_SAI3_MCLK_SEL 0x308 +#define IMX_AUDIO_BLK_CTL_SAI5_MCLK_SEL 0x30C +#define IMX_AUDIO_BLK_CTL_SAI6_MCLK_SEL 0x310 +#define IMX_AUDIO_BLK_CTL_SAI7_MCLK_SEL 0x314 +#define IMX_AUDIO_BLK_CTL_PDM_CLK 0x318 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_GNRL_CTL 0x400 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL0 0x404 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL1 0x408 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_SSCG_CTL 0x40C +#define IMX_AUDIO_BLK_CTL_SAI_PLL_MNIT_CTL 0x410 +#define IMX_AUDIO_BLK_CTL_IPG_LP_CTRL 0x504 + +#define IMX_MEDIA_BLK_CTL_SFT_RSTN 0x0 +#define IMX_MEDIA_BLK_CTL_CLK_EN 0x4 + +static int shared_count_pdm; + +static const struct imx_pll14xx_rate_table imx_blk_ctl_sai_pll_tbl[] = { + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +}; + +static const struct imx_pll14xx_clk imx_blk_ctl_sai_pll = { + .type = PLL_1443X, + .rate_table = imx_blk_ctl_sai_pll_tbl, +}; + +static const char * const imx_sai_mclk2_sels[] = {"sai1_root", "sai2_root", "sai3_root", "dummy", + "sai5_root", "sai6_root", "sai7_root", "sai1_mclk", + "sai2_mclk", "sai3_mclk", "dummy", + "sai5_mclk", "sai6_mclk", "sai7_mclk", "spdif1_ext_clk"}; +static const char * const imx_sai1_mclk1_sels[] = {"sai1_root", "sai1_mclk", }; +static const char * const imx_sai2_mclk1_sels[] = {"sai2_root", "sai2_mclk", }; +static const char * const imx_sai3_mclk1_sels[] = {"sai3_root", "sai3_mclk", }; +static const char * const imx_sai5_mclk1_sels[] = {"sai5_root", "sai5_mclk", }; +static const char * const imx_sai6_mclk1_sels[] = {"sai6_root", "sai6_mclk", }; +static const char * const imx_sai7_mclk1_sels[] = {"sai7_root", "sai7_mclk", }; +static const char * const imx_pdm_sels[] = {"pdm_root", "sai_pll_div2", "dummy", "dummy" }; +static const char * const imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; +static const char * const imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; + +static const char * const imx_hdmi_phy_clks_sels[] = {"hdmi_glb_24m", "dummy", }; +static const char * const imx_lcdif_clks_sels[] = {"dummy", "hdmi_glb_pix", }; +static const char * const imx_hdmi_pipe_clks_sels[] = {"dummy", "hdmi_glb_pix", }; + +static struct imx_blk_ctl_hw imx8mp_hdmi_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_GATE("hdmi_glb_apb", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK, 0x40, 0, "hdmi_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_b", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK, 0x40, 1, "hdmi_axi"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_ref_266m", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK, 0x40, 2, "hdmi_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_24m", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK, 0x40, 4, "hdmi_24m"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_32k", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK, 0x40, 5, "osc_32k"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_pix", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK, 0x40, 7, "hdmi_phy"), + IMX_BLK_CTL_CLK_GATE("hdmi_irq_steer", IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK, 0x40, 9, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_noc", IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK, 0x40, 10, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdcp_noc", IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK, 0x40, 11, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_apb", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK, 0x40, 16, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_b", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK, 0x40, 17, "hdmi_glb_b"), + IMX_BLK_CTL_CLK_GATE("lcdif3_pdi", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK, 0x40, 18, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_pxl", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK, 0x40, 19, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("lcdif3_spu", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK, 0x40, 20, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_fdcc_ref", IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK, 0x50, 2, "hdmi_fdcc_tst"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_apb", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK, 0x50, 3, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_b", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK, 0x50, 4, "hdmi_glb_axi"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_cea", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK, 0x50, 5, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("vsfd_cea", IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK, 0x50, 6, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_hpi", IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK, 0x50, 13, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK, 0x50, 14, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_cec", IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK, 0x50, 15, "hdmi_glb_32k"), + IMX_BLK_CTL_CLK_GATE("hdmi_esm", IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK, 0x50, 16, "hdmi_glb_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_gpa", IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK, 0x50, 17, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_pix", IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK, 0x50, 18, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_sfr", IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK, 0x50, 19, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_skp", IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK, 0x50, 20, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_prep", IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK, 0x50, 21, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_phy_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK, 0x50, 22, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_phy_int", IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK, 0x50, 24, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_sec_mem", IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK, 0x50, 25, "hdmi_glb_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_trng_skp", IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK, 0x50, 27, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_vid_pix", IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK, 0x50, 28, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("hdmi_trng_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK, 0x50, 30, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_MUX("hdmi_phy_sel", IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL, 0x50, 10, 1, imx_hdmi_phy_clks_sels), + IMX_BLK_CTL_CLK_MUX("lcdif_clk_sel", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL, 0x50, 11, 1, imx_lcdif_clks_sels), + IMX_BLK_CTL_CLK_MUX("hdmi_pipe_sel", IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL, 0x50, 12, 1, imx_hdmi_pipe_clks_sels), + + /* resets */ + IMX_BLK_CTL_RESET_MASK(IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET, 0x20, 6, 0x33), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET, 0x20, 12), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET, 0x20, 18), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET, 0x20, 22), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET, 0x20, 20), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET, 0x20, 16), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET, 0x20, 13), + IMX_BLK_CTL_RESET_MASK(IMX8MP_HDMI_BLK_CTL_LCDIF_RESET, 0x20, 4, 0x3), +}; + +static struct imx_blk_ctl_hw imx8mp_media_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_GATE("mipi_dsi_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK, 0x4, 0, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_dsi_clkref", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF, 0x4, 1, "media_mipi_phy1_ref"), + IMX_BLK_CTL_CLK_GATE("mipi_csi_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK, 0x4, 2, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi_aclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK, 0x4, 3, "media_cam1_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL, 0x4, 4, "media_disp1_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB, 0x4, 5, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isi_proc_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC, 0x4, 6, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isi_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB, 0x4, 7, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("bus_blk_clk", IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK, 0x4, 8, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi2_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK, 0x4, 9, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi2_aclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK, 0x4, 10, "media_cam2_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL, 0x4, 11, "media_disp2_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB, 0x4, 12, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR, 0x4, 13, "media_isp_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI, 0x4, 14, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB, 0x4, 15, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR, 0x4, 16, "media_isp_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI, 0x4, 17, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB, 0x4, 18, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR, 0x4, 19, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI, 0x4, 20, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB, 0x4, 21, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_dsi2_clk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2, 0x4, 22, "media_mipi_phy1_ref"), + IMX_BLK_CTL_CLK_GATE("lcdif_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI, 0x4, 23, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI, 0x4, 24, "media_axi_root_clk"), + + /* resets */ + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK, 0, 0), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF, 0, 1), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK, 0, 2), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK, 0, 3), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL, 0, 4), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB, 0, 5), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC, 0, 6), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB, 0, 7), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK, 0, 8), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK, 0, 9), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK, 0, 10), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL, 0, 11), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB, 0, 12), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR, 0, 13), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI, 0, 14), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB, 0, 15), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR, 0, 16), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI, 0, 17), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB, 0, 18), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR, 0, 19), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI, 0, 20), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB, 0, 21), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2, 0, 22), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI, 0, 23), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI, 0, 24) +}; + +static struct imx_blk_ctl_hw imx8mp_audio_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), + IMX_BLK_CTL_CLK_PLL14XX("sai_pll", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL, 0x400, "sai_pll_ref_sel", &imx_blk_ctl_sai_pll), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai_pll_bypass", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS, 0x400, 4, 1, imx_sai_pll_bypass_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_GATE("sai_pll_out", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT, 0x400, 13, "sai_pll_bypass"), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai1_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL, 0x300, 0, 1, imx_sai1_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai1_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL, 0x300, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai2_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL, 0x304, 0, 1, imx_sai2_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai2_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL, 0x304, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai3_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL, 0x308, 0, 1, imx_sai3_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai3_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL, 0x308, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai5_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL, 0x30C, 0, 1, imx_sai5_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai5_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL, 0x30C, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai6_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL, 0x310, 0, 1, imx_sai6_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai6_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL, 0x310, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai7_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL, 0x314, 0, 1, imx_sai7_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai7_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL, 0x314, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_GATE("sai1_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG, 0, 0, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1, 0, 1, "sai1_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2, 0, 2, "sai1_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3, 0, 3, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai2_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG, 0, 4, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1, 0, 5, "sai2_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2, 0, 6, "sai2_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3, 0, 7, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai3_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG, 0, 8, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1, 0, 9, "sai3_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2, 0, 10, "sai3_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3, 0, 11, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai5_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG, 0, 12, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1, 0, 13, "sai5_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2, 0, 14, "sai5_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3, 0, 15, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai6_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG, 0, 16, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1, 0, 17, "sai6_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2, 0, 18, "sai6_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3, 0, 19, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai7_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG, 0, 20, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1, 0, 21, "sai7_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2, 0, 22, "sai7_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3, 0, 23, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("asrc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG, 0, 24, "audio_ahb_root"), + IMX_BLK_CTL_CLK_SHARED_GATE("pdm_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG, 0, 25, "audio_ahb_root", &shared_count_pdm), + IMX_BLK_CTL_CLK_SHARED_GATE("pdm_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT, 0, 25, "pdm_root", &shared_count_pdm), + IMX_BLK_CTL_CLK_GATE("sdma2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SDMA2_ROOT, 0, 26, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sdma3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT, 0, 27, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("spba2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT, 0, 28, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("dsp_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT, 0, 29, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("dsp_dbg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT, 0, 30, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("earc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG, 0, 31, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("ocram_a_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG, 4, 0, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("aud2htx_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG, 4, 1, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("edma_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT, 4, 2, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("aud_pll_clk", IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT, 4, 3, "osc_24m"), + IMX_BLK_CTL_CLK_GATE("mu2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT, 4, 4, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("mu3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT, 4, 5, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("earc_phy_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY, 4, 6, "sai_pll_out"), + IMX_BLK_CTL_CLK_MUX("pdm_sel", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL, 0x318, 1, 4, imx_pdm_sels), + + /* resets */ + IMX_BLK_CTL_RESET(IMX8MP_AUDIO_BLK_CTL_EARC_RESET, 0x200, 0), + IMX_BLK_CTL_RESET(IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET, 0x200, 1), +}; + +const struct imx_blk_ctl_dev_data imx8mp_hdmi_blk_ctl_dev_data __initconst = { + .hws = imx8mp_hdmi_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_hdmi_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_HDMI_BLK_CTL_END, + .resets_max = IMX8MP_HDMI_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 0 +}; + +const struct imx_blk_ctl_dev_data imx8mp_media_blk_ctl_dev_data __initconst = { + .hws = imx8mp_media_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_media_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_MEDIA_BLK_CTL_END, + .resets_max = IMX8MP_MEDIA_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 2, + .pm_runtime_saved_regs = { + IMX_MEDIA_BLK_CTL_SFT_RSTN, + IMX_MEDIA_BLK_CTL_CLK_EN, + }, +}; + +const struct imx_blk_ctl_dev_data imx8mp_audio_blk_ctl_dev_data __initconst = { + .hws = imx8mp_audio_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_AUDIO_BLK_CTL_END, + .resets_max = IMX8MP_AUDIO_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 16, + .pm_runtime_saved_regs = { + IMX_AUDIO_BLK_CTL_CLKEN0, + IMX_AUDIO_BLK_CTL_CLKEN1, + IMX_AUDIO_BLK_CTL_EARC, + IMX_AUDIO_BLK_CTL_SAI1_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI2_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI3_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI5_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI6_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI7_MCLK_SEL, + IMX_AUDIO_BLK_CTL_PDM_CLK, + IMX_AUDIO_BLK_CTL_SAI_PLL_GNRL_CTL, + IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL0, + IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL1, + IMX_AUDIO_BLK_CTL_SAI_PLL_SSCG_CTL, + IMX_AUDIO_BLK_CTL_SAI_PLL_MNIT_CTL, + IMX_AUDIO_BLK_CTL_IPG_LP_CTRL + }, +}; + +static const struct of_device_id imx_blk_ctl_of_match[] = { + { + .compatible = "fsl,imx8mp-audio-blk-ctl", + .data = &imx8mp_audio_blk_ctl_dev_data + }, + { + .compatible = "fsl,imx8mp-media-blk-ctl", + .data = &imx8mp_media_blk_ctl_dev_data + }, + { + .compatible = "fsl,imx8mp-hdmi-blk-ctl", + .data = &imx8mp_hdmi_blk_ctl_dev_data + }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_blk_ctl_of_match); + +static struct platform_driver imx_blk_ctl_driver = { + .probe = imx_blk_ctl_probe, + .driver = { + .name = "imx-blk-ctl", + .of_match_table = of_match_ptr(imx_blk_ctl_of_match), + .pm = &imx_blk_ctl_pm_ops, + }, +}; +module_platform_driver(imx_blk_ctl_driver); From patchwork Tue Sep 8 10:24:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B8EA746 for ; Tue, 8 Sep 2020 10:27:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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(inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B96D01A0339; Tue, 8 Sep 2020 12:26:14 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 065B120327; Tue, 8 Sep 2020 12:26:13 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 12/14] arm64: dts: imx8mp: Add audio_blk_ctl node Date: Tue, 8 Sep 2020 13:24:49 +0300 Message-Id: <1599560691-3763-13-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) 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linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some of the features of the audio_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa Reviewed-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index cad2dd7..3541fd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -736,6 +736,21 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x50c>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, From patchwork Tue Sep 8 10:24:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E6D2112E for ; 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Tue, 8 Sep 2020 12:26:15 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id C812B2036D; Tue, 8 Sep 2020 12:26:14 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 13/14] arm64: dts: imx8mp: Add media_blk_ctl node Date: Tue, 8 Sep 2020 13:24:50 +0300 Message-Id: <1599560691-3763-14-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062620_153390_88C406BD X-CRM114-Status: GOOD ( 11.78 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some of the features of the media_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa Reviewed-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3541fd9..3a5ccef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -736,6 +736,21 @@ }; }; + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + media_blk_ctl: clock-controller@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctl", "syscon"; + reg = <0x32ec0000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + aips5: bus@30c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30c00000 0x400000>; From patchwork Tue Sep 8 10:24:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11763185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5733715E4 for ; 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Tue, 8 Sep 2020 12:26:16 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 940082036D; Tue, 8 Sep 2020 12:26:15 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Jacky Bai , Peng Fan , Dong Aisheng , Fugang Duan , devicetree@vger.kernel.org Subject: [PATCH v3 14/14] arm64: dts: imx8mp: Add hdmi_blk_ctl node Date: Tue, 8 Sep 2020 13:24:51 +0300 Message-Id: <1599560691-3763-15-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> References: <1599560691-3763-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_062620_150967_1264FCE2 X-CRM114-Status: GOOD ( 11.50 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [92.121.34.13 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , linux-clk@vger.kernel.org, NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some of the features of the hdmi_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3a5ccef..0cf4fa1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -749,6 +749,13 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + hdmi_blk_ctl: clock-controller@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctl", "syscon"; + reg = <0x32fc0000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; aips5: bus@30c00000 {