From patchwork Wed Sep 9 08:50:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 11765107 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4391C92C for ; Wed, 9 Sep 2020 08:57:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F56121919 for ; Wed, 9 Sep 2020 08:57:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F56121919 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D01B6EB1E; Wed, 9 Sep 2020 08:57:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9FAE46EB1E for ; Wed, 9 Sep 2020 08:57:13 +0000 (UTC) IronPort-SDR: M9JC4tAELuoLn1sUPjgUJ5vnQ43bShLytOhccnEgUlYxWlpKl8rgMR349dXH8uZlSyTOiqZ75G F6I79wbCgDzQ== X-IronPort-AV: E=McAfee;i="6000,8403,9738"; a="159257110" X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="159257110" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2020 01:57:03 -0700 IronPort-SDR: 8RHSjywk4OfCbG/V/UoWYnOTdZq83Di2CeZe2dpubkLRqIZxgqwscL5eq9zQP8mviOQoMQ9Fvy IEh7SX3DpbqQ== X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="480384761" Received: from vandita-desktop.iind.intel.com ([10.223.74.218]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 09 Sep 2020 01:57:01 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Sep 2020 14:20:44 +0530 Message-Id: <20200909085047.31004-2-vandita.kulkarni@intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a In-Reply-To: <20200909085047.31004-1-vandita.kulkarni@intel.com> References: <20200909085047.31004-1-vandita.kulkarni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [V9 1/4] drm/i915/dsi: Add details about TE in get_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need details about enabling TE on which port before we enable TE through vblank enable path. This is based on the configuration that we receive from the VBT wrt ports, dual_link. Signed-off-by: Vandita Kulkarni Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 30 +++++++++++++++----------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index f4053dd6bde9..ee3c5c085cd3 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1447,6 +1447,18 @@ static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); } +static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, + struct intel_crtc_state *pipe_config) +{ + if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) + pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | + I915_MODE_FLAG_DSI_USE_TE0; + else if (intel_dsi->ports == BIT(PORT_B)) + pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; + else + pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; +} + static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { @@ -1468,6 +1480,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); + /* Get the details on which TE should be enabled */ + if (is_cmd_mode(intel_dsi)) + gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); + if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; } @@ -1562,18 +1578,8 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, * receive TE from the slave if * dual link is enabled */ - if (is_cmd_mode(intel_dsi)) { - if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) - pipe_config->mode_flags |= - I915_MODE_FLAG_DSI_USE_TE1 | - I915_MODE_FLAG_DSI_USE_TE0; - else if (intel_dsi->ports == BIT(PORT_B)) - pipe_config->mode_flags |= - I915_MODE_FLAG_DSI_USE_TE1; - else - pipe_config->mode_flags |= - I915_MODE_FLAG_DSI_USE_TE0; - } + if (is_cmd_mode(intel_dsi)) + gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); return 0; } From patchwork Wed Sep 9 08:50:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 11765113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0A7D746 for ; Wed, 9 Sep 2020 08:57:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2DA721919 for ; Wed, 9 Sep 2020 08:57:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B2DA721919 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD98E6EB42; Wed, 9 Sep 2020 08:57:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 043186EB1E for ; Wed, 9 Sep 2020 08:57:13 +0000 (UTC) IronPort-SDR: AwfPvIA1NxP5sDmyEXn9pGcbfiVUEG7C+iPoF0BOBDj30ZHfyXWYWxYTpVD7NYBpVgLQLqKwOf NPKfTDNn9OkA== X-IronPort-AV: E=McAfee;i="6000,8403,9738"; a="159257114" X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="159257114" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2020 01:57:05 -0700 IronPort-SDR: 2fdH2Z2rBgO4jamofym2OU2ItRAnKu2rcdFNFi83C8wtQLpEVcAEVA3blqZcCGl7DMMjnwVdKw 9HdZ7a5Xh3+w== X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="480384770" Received: from vandita-desktop.iind.intel.com ([10.223.74.218]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 09 Sep 2020 01:57:03 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Sep 2020 14:20:45 +0530 Message-Id: <20200909085047.31004-3-vandita.kulkarni@intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a In-Reply-To: <20200909085047.31004-1-vandita.kulkarni@intel.com> References: <20200909085047.31004-1-vandita.kulkarni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [V9 2/4] i915/dsi: Configure TE interrupt for cmd mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Configure TE interrupt as part of the vblank enable call flow. v2: Hide the private flags check inside configure_te (Jani) v3: Fix the position of masking de_port_masked for DSI_TE. v4: Simplify the caller of configure_te (Jani) v5: Clear IIR, remove the usage of private_flags Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f113fe44572b..de540194ce67 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -40,6 +40,7 @@ #include "display/intel_hotplug.h" #include "display/intel_lpe_audio.h" #include "display/intel_psr.h" +#include "display/intel_dsi.h" #include "gt/intel_breadcrumbs.h" #include "gt/intel_gt.h" @@ -2692,12 +2693,47 @@ int ilk_enable_vblank(struct drm_crtc *crtc) return 0; } +static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, + bool enable) +{ + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + enum port port; + u32 tmp; + + if (!(intel_crtc->mode_flags & + (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) + return false; + + /* for dual link cases we consider TE from slave */ + if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) + port = PORT_B; + else + port = PORT_A; + + tmp = I915_READ(DSI_INTR_MASK_REG(port)); + if (enable) + tmp &= ~DSI_TE_EVENT; + else + tmp |= DSI_TE_EVENT; + + I915_WRITE(DSI_INTR_MASK_REG(port), tmp); + + tmp = I915_READ(DSI_INTR_IDENT_REG(port)); + I915_WRITE(DSI_INTR_IDENT_REG(port), tmp); + + return true; +} + int bdw_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); - enum pipe pipe = to_intel_crtc(crtc)->pipe; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + enum pipe pipe = intel_crtc->pipe; unsigned long irqflags; + if (gen11_dsi_configure_te(intel_crtc, true)) + return 0; + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); @@ -2763,9 +2799,13 @@ void ilk_disable_vblank(struct drm_crtc *crtc) void bdw_disable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); - enum pipe pipe = to_intel_crtc(crtc)->pipe; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + enum pipe pipe = intel_crtc->pipe; unsigned long irqflags; + if (gen11_dsi_configure_te(intel_crtc, false)) + return; + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); @@ -3456,6 +3496,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (IS_GEN9_LP(dev_priv)) de_port_masked |= BXT_DE_PORT_GMBUS; + if (INTEL_GEN(dev_priv) >= 11) { + enum port port; + + if (intel_bios_is_dsi_present(dev_priv, &port)) + de_port_masked |= DSI0_TE | DSI1_TE; + } + de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; From patchwork Wed Sep 9 08:50:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 11765111 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6A3B746 for ; Wed, 9 Sep 2020 08:57:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD8D3218AC for ; Wed, 9 Sep 2020 08:57:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BD8D3218AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 206656EB1F; Wed, 9 Sep 2020 08:57:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4AF5E6EB3A for ; Wed, 9 Sep 2020 08:57:14 +0000 (UTC) IronPort-SDR: fyqy1t1KI/39SybFnBQQvQHu0pO3QG5hlSJoD1ZaSFleezmbmX1CNNASWO/e+j30W7sUjYyqQO lmiFIGGf+QgA== X-IronPort-AV: E=McAfee;i="6000,8403,9738"; a="159257119" X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="159257119" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2020 01:57:07 -0700 IronPort-SDR: x/vbTmwmI7ZR9Q8bVCptUyAYOgrr6MUlkXee9fTysmCtax3QnG52Ii0XQRDtYweZn1dEkf70gT SPA2LB1fACfQ== X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="480384781" Received: from vandita-desktop.iind.intel.com ([10.223.74.218]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 09 Sep 2020 01:57:05 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Sep 2020 14:20:46 +0530 Message-Id: <20200909085047.31004-4-vandita.kulkarni@intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a In-Reply-To: <20200909085047.31004-1-vandita.kulkarni@intel.com> References: <20200909085047.31004-1-vandita.kulkarni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [V9 3/4] drm/i915/dsi: Add TE handler for dsi cmd mode. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. If we are operating in TE_GATE mode, after we do a frame update, the transcoder will send the frame data to the panel, after it receives a TE. Whereas if we are operating in NO_GATE mode then the transcoder will immediately send the frame data to the panel. We are not dealing with the periodic command mode here. v2: Pass only relevant masked bits to the handler (Jani) v3: Fix the check for cmd mode in TE handler function. v4: Use intel_handle_vblank instead of drm_handle_vblank (Jani) Signed-off-by: Vandita Kulkarni Reported-by: kernel test robot Acked-by: Jani Nikula --- drivers/gpu/drm/i915/i915_irq.c | 66 +++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index de540194ce67..f8398c5cbd4a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2299,6 +2299,64 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); } +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, + u32 te_trigger) +{ + enum pipe pipe = INVALID_PIPE; + enum transcoder dsi_trans; + enum port port; + u32 val, tmp; + + /* + * Incase of dual link, TE comes from DSI_1 + * this is to check if dual link is enabled + */ + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); + val &= PORT_SYNC_MODE_ENABLE; + + /* + * if dual link is enabled, then read DSI_0 + * transcoder registers + */ + port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? + PORT_A : PORT_B; + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; + + /* Check if DSI configured in command mode */ + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); + val = val & OP_MODE_MASK; + + if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) { + drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); + return; + } + + /* Get PIPE for handling VBLANK event */ + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); + switch (val & TRANS_DDI_EDP_INPUT_MASK) { + case TRANS_DDI_EDP_INPUT_A_ON: + pipe = PIPE_A; + break; + case TRANS_DDI_EDP_INPUT_B_ONOFF: + pipe = PIPE_B; + break; + case TRANS_DDI_EDP_INPUT_C_ONOFF: + pipe = PIPE_C; + break; + default: + drm_err(&dev_priv->drm, "Invalid PIPE\n"); + return; + } + + intel_handle_vblank(dev_priv, pipe); + + /* clear TE in dsi IIR */ + port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; + tmp = I915_READ(DSI_INTR_IDENT_REG(port)); + I915_WRITE(DSI_INTR_IDENT_REG(port), tmp); + +} + static irqreturn_t gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) { @@ -2363,6 +2421,14 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } + if (INTEL_GEN(dev_priv) >= 11) { + tmp_mask = iir & (DSI0_TE | DSI1_TE); + if (tmp_mask) { + gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask); + found = true; + } + } + if (!found) drm_err(&dev_priv->drm, "Unexpected DE Port interrupt\n"); From patchwork Wed Sep 9 08:50:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 11765109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C33C7138E for ; Wed, 9 Sep 2020 08:57:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9ABEB218AC for ; Wed, 9 Sep 2020 08:57:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9ABEB218AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 999EE6EB3A; Wed, 9 Sep 2020 08:57:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F3BB6EB1E for ; Wed, 9 Sep 2020 08:57:14 +0000 (UTC) IronPort-SDR: Xg6yxUveIzB2dF5dHjBRRoyGes9+Sl/4EVIioiVA1ZByrrSk2KmtIcEQDXqfQ+Hv/lyLVCTCXo qTcEzkLB+pMg== X-IronPort-AV: E=McAfee;i="6000,8403,9738"; a="159257122" X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="159257122" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2020 01:57:09 -0700 IronPort-SDR: rpmUfj8ivLhh8dDcKts6guYi+l3KKm8HwsF45xtuCot48YXoJ53QJ7P2nvJh1Tr/qO4KGLP9OY VgugfTD0q7Ig== X-IronPort-AV: E=Sophos;i="5.76,409,1592895600"; d="scan'208";a="480384792" Received: from vandita-desktop.iind.intel.com ([10.223.74.218]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 09 Sep 2020 01:57:07 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Sep 2020 14:20:47 +0530 Message-Id: <20200909085047.31004-5-vandita.kulkarni@intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a In-Reply-To: <20200909085047.31004-1-vandita.kulkarni@intel.com> References: <20200909085047.31004-1-vandita.kulkarni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [V9 4/4] drm/i915/dsi: Initiate fame request in cmd mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In TE Gate mode or TE NO_GATE mode on every flip we need to set the frame update request bit. After this bit is set transcoder hardware will automatically send the frame data to the panel in case of TE NO_GATE mode, where it sends after it receives the TE event in case of TE_GATE mode. Once the frame data is sent to the panel, we see the frame counter updating. v2: Use intel_de_read/write v3: remove the usage of private_flags Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++ drivers/gpu/drm/i915/display/intel_dsi.h | 3 +++ 3 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ee3c5c085cd3..cdc9d8874945 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -205,6 +205,32 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host, return 0; } +void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 tmp, flags; + enum port port; + + flags = crtc->mode_flags; + + /* + * case 1 also covers dual link + * In case of dual link, frame update should be set on + * DSI_0 + */ + if (flags & I915_MODE_FLAG_DSI_USE_TE0) + port = PORT_A; + else if (flags & I915_MODE_FLAG_DSI_USE_TE1) + port = PORT_B; + else + return; + + tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); + tmp |= DSI_FRAME_UPDATE_REQUEST; + intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); +} + static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ec148a8da2c2..cd852c24d3bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15615,6 +15615,18 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_set_cdclk_post_plane_update(state); } + /* + * Incase of mipi dsi command mode, we need to set frame update + * for every commit + */ + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if ((INTEL_GEN(dev_priv) >= 11) && + (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))) { + if (new_crtc_state->hw.active) + gen11_dsi_frame_update(new_crtc_state); + } + } + /* FIXME: We should call drm_atomic_helper_commit_hw_done() here * already, but still need the state for the delayed optimization. To * fix this: @@ -15626,6 +15638,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) */ drm_atomic_helper_wait_for_flip_done(dev, &state->base); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (new_crtc_state->hw.active && !needs_modeset(new_crtc_state) && diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h index 19f78a4022d3..08f1f586eefb 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.h +++ b/drivers/gpu/drm/i915/display/intel_dsi.h @@ -205,6 +205,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, struct intel_crtc_state *config); void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); +/* icl_dsi.c */ +void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state); + /* intel_dsi_vbt.c */ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id); void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);