From patchwork Wed Oct 24 16:18:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10654789 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6477113A9 for ; Wed, 24 Oct 2018 15:58:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56C9A2AB0C for ; Wed, 24 Oct 2018 15:58:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A8822ABFB; Wed, 24 Oct 2018 15:58:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B0F832AB0C for ; Wed, 24 Oct 2018 15:58:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B3176E262; Wed, 24 Oct 2018 15:58:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 617A16E262 for ; Wed, 24 Oct 2018 15:58:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Oct 2018 08:58:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,420,1534834800"; d="scan'208";a="102934723" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga002.jf.intel.com with ESMTP; 24 Oct 2018 08:58:07 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Wed, 24 Oct 2018 21:48:12 +0530 Message-Id: <1540397893-3301-2-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1540397893-3301-1-git-send-email-uma.shankar@intel.com> References: <1540397893-3301-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v2 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Defined the plane input csc coefficient registers and macros. 6 registers are used to program a total of 9 coefficients, added macros to define each of them for all the planes supporting the feature on pipes. On ICL, bottom 3 planes have this capability. v2: Segregated the register macro definition as separate patch as per Maarten's suggestion. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 217 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 69eb573..6a363a32 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6569,6 +6569,7 @@ enum { #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) +#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* Pre-ICL */ #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) @@ -6585,6 +6586,222 @@ enum { #define _PLANE_NV12_BUF_CFG_1_A 0x70278 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 +/* Input CSC Register Definitions */ +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 +#define _PLANE_INPUT_CSC_RY_GY_3_A 0x703E0 + +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 +#define _PLANE_INPUT_CSC_RY_GY_3_B 0x713E0 + +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ + _PLANE_INPUT_CSC_RY_GY_1_B) +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ + _PLANE_INPUT_CSC_RY_GY_2_B) +#define PLANE_INPUT_CSC_RY_GY(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe), \ + _PLANE_INPUT_CSC_RY_GY_2(pipe)) + +#define _PLANE_INPUT_CSC_BY_1_A 0x701E4 +#define _PLANE_INPUT_CSC_BY_2_A 0x702E4 +#define _PLANE_INPUT_CSC_BY_3_A 0x703E4 + +#define _PLANE_INPUT_CSC_BY_1_B 0x711E4 +#define _PLANE_INPUT_CSC_BY_2_B 0x712E4 +#define _PLANE_INPUT_CSC_BY_3_B 0x713E4 + +#define _PLANE_INPUT_CSC_BY_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_BY_1_A, \ + _PLANE_INPUT_CSC_BY_1_B) +#define _PLANE_INPUT_CSC_BY_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_BY_2_A, \ + _PLANE_INPUT_CSC_BY_2_B) +#define PLANE_INPUT_CSC_BY(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_BY_1(pipe), \ + _PLANE_INPUT_CSC_BY_2(pipe)) + +#define _PLANE_INPUT_CSC_RU_GU_1_A 0x701E8 +#define _PLANE_INPUT_CSC_RU_GU_2_A 0x702E8 +#define _PLANE_INPUT_CSC_RU_GU_3_A 0x703E8 + +#define _PLANE_INPUT_CSC_RU_GU_1_B 0x711E8 +#define _PLANE_INPUT_CSC_RU_GU_2_B 0x712E8 +#define _PLANE_INPUT_CSC_RU_GU_3_B 0x713E8 + +#define _PLANE_INPUT_CSC_RU_GU_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RU_GU_1_A, \ + _PLANE_INPUT_CSC_RU_GU_1_B) +#define _PLANE_INPUT_CSC_RU_GU_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RU_GU_2_A, \ + _PLANE_INPUT_CSC_RU_GU_2_B) +#define PLANE_INPUT_CSC_RU_GU(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RU_GU_1(pipe), \ + _PLANE_INPUT_CSC_RU_GU_2(pipe)) + +#define _PLANE_INPUT_CSC_BU_1_A 0x701EC +#define _PLANE_INPUT_CSC_BU_2_A 0x702EC +#define _PLANE_INPUT_CSC_BU_3_A 0x703EC + +#define _PLANE_INPUT_CSC_BU_1_B 0x711EC +#define _PLANE_INPUT_CSC_BU_2_B 0x712EC +#define _PLANE_INPUT_CSC_BU_3_B 0x713EC + +#define _PLANE_INPUT_CSC_BU_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_BU_1_A, \ + _PLANE_INPUT_CSC_BU_1_B) +#define _PLANE_INPUT_CSC_BU_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_BU_2_A, \ + _PLANE_INPUT_CSC_BU_2_B) +#define PLANE_INPUT_CSC_BU(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_BU_1(pipe), \ + _PLANE_INPUT_CSC_BU_2(pipe)) + +#define _PLANE_INPUT_CSC_RV_GV_1_A 0x701F0 +#define _PLANE_INPUT_CSC_RV_GV_2_A 0x702F0 +#define _PLANE_INPUT_CSC_RV_GV_3_A 0x703F0 + +#define _PLANE_INPUT_CSC_RV_GV_1_B 0x711F0 +#define _PLANE_INPUT_CSC_RV_GV_2_B 0x712F0 +#define _PLANE_INPUT_CSC_RV_GV_3_B 0x713F0 + +#define _PLANE_INPUT_CSC_RV_GV_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RV_GV_1_A, \ + _PLANE_INPUT_CSC_RV_GV_1_B) +#define _PLANE_INPUT_CSC_RV_GV_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RV_GV_2_A, \ + _PLANE_INPUT_CSC_RV_GV_2_B) +#define PLANE_INPUT_CSC_RV_GV(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RV_GV_1(pipe), \ + _PLANE_INPUT_CSC_RV_GV_2(pipe)) + +#define _PLANE_INPUT_CSC_BV_1_A 0x701F4 +#define _PLANE_INPUT_CSC_BV_2_A 0x702F4 +#define _PLANE_INPUT_CSC_BV_3_A 0x703F4 + +#define _PLANE_INPUT_CSC_BV_1_B 0x711F4 +#define _PLANE_INPUT_CSC_BV_2_B 0x712F4 +#define _PLANE_INPUT_CSC_BV_3_B 0x713F4 + +#define _PLANE_INPUT_CSC_BV_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_BV_1_A, \ + _PLANE_INPUT_CSC_BV_1_B) +#define _PLANE_INPUT_CSC_BV_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_BV_2_A, \ + _PLANE_INPUT_CSC_BV_2_B) +#define PLANE_INPUT_CSC_BV(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_BV_1(pipe), \ + _PLANE_INPUT_CSC_BV_2(pipe)) + +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 +#define _PLANE_INPUT_CSC_PREOFF_HI_3_A 0x703F8 + +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 +#define _PLANE_INPUT_CSC_PREOFF_HI_3_B 0x713F8 + +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ + _PLANE_INPUT_CSC_PREOFF_HI_1_B) +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ + _PLANE_INPUT_CSC_PREOFF_HI_2_B) +#define PLANE_INPUT_CSC_PREOFF_HI(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe), \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)) + +#define _PLANE_INPUT_CSC_PREOFF_ME_1_A 0x701FC +#define _PLANE_INPUT_CSC_PREOFF_ME_2_A 0x702FC +#define _PLANE_INPUT_CSC_PREOFF_ME_3_A 0x703FC + +#define _PLANE_INPUT_CSC_PREOFF_ME_1_B 0x711FC +#define _PLANE_INPUT_CSC_PREOFF_ME_2_B 0x712FC +#define _PLANE_INPUT_CSC_PREOFF_ME_3_B 0x713FC + +#define _PLANE_INPUT_CSC_PREOFF_ME_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_ME_1_A, \ + _PLANE_INPUT_CSC_PREOFF_ME_1_B) +#define _PLANE_INPUT_CSC_PREOFF_ME_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_ME_2_A, \ + _PLANE_INPUT_CSC_PREOFF_ME_2_B) +#define PLANE_INPUT_CSC_PREOFF_ME(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_ME_1(pipe), \ + _PLANE_INPUT_CSC_PREOFF_ME_2(pipe)) + +#define _PLANE_INPUT_CSC_PREOFF_LO_1_A 0x70200 +#define _PLANE_INPUT_CSC_PREOFF_LO_2_A 0x70300 +#define _PLANE_INPUT_CSC_PREOFF_LO_3_A 0x70400 + +#define _PLANE_INPUT_CSC_PREOFF_LO_1_B 0x71200 +#define _PLANE_INPUT_CSC_PREOFF_LO_2_B 0x71300 +#define _PLANE_INPUT_CSC_PREOFF_LO_3_B 0x71400 + +#define _PLANE_INPUT_CSC_PREOFF_LO_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_LO_1_A, \ + _PLANE_INPUT_CSC_PREOFF_LO_1_B) +#define _PLANE_INPUT_CSC_PREOFF_LO_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_LO_2_A, \ + _PLANE_INPUT_CSC_PREOFF_LO_2_B) +#define PLANE_INPUT_CSC_PREOFF_LO(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_LO_1(pipe), \ + _PLANE_INPUT_CSC_PREOFF_LO_2(pipe)) + +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 +#define _PLANE_INPUT_CSC_POSTOFF_HI_3_A 0x70404 + +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 +#define _PLANE_INPUT_CSC_POSTOFF_HI_3_B 0x71404 + +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ + _PLANE_INPUT_CSC_POSTOFF_HI_1_B) +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2_B) +#define PLANE_INPUT_CSC_POSTOFF_HI(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe), \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)) + +#define _PLANE_INPUT_CSC_POSTOFF_ME_1_A 0x70208 +#define _PLANE_INPUT_CSC_POSTOFF_ME_2_A 0x70308 +#define _PLANE_INPUT_CSC_POSTOFF_ME_3_A 0x70408 + +#define _PLANE_INPUT_CSC_POSTOFF_ME_1_B 0x71208 +#define _PLANE_INPUT_CSC_POSTOFF_ME_2_B 0x71308 +#define _PLANE_INPUT_CSC_POSTOFF_ME_3_B 0x71408 + +#define _PLANE_INPUT_CSC_POSTOFF_ME_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_ME_1_A, \ + _PLANE_INPUT_CSC_POSTOFF_ME_1_B) +#define _PLANE_INPUT_CSC_POSTOFF_ME_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_ME_2_A, \ + _PLANE_INPUT_CSC_POSTOFF_ME_2_B) +#define PLANE_INPUT_CSC_POSTOFF_ME(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_ME_1(pipe), \ + _PLANE_INPUT_CSC_POSTOFF_ME_2(pipe)) + +#define _PLANE_INPUT_CSC_POSTOFF_LO_1_A 0x7020C +#define _PLANE_INPUT_CSC_POSTOFF_LO_2_A 0x7030C +#define _PLANE_INPUT_CSC_POSTOFF_LO_3_A 0x7040C + +#define _PLANE_INPUT_CSC_POSTOFF_LO_1_B 0x7120C +#define _PLANE_INPUT_CSC_POSTOFF_LO_2_B 0x7130C +#define _PLANE_INPUT_CSC_POSTOFF_LO_3_B 0x7140C + +#define _PLANE_INPUT_CSC_POSTOFF_LO_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_LO_1_A, \ + _PLANE_INPUT_CSC_POSTOFF_LO_1_B) +#define _PLANE_INPUT_CSC_POSTOFF_LO_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_LO_2_A, \ + _PLANE_INPUT_CSC_POSTOFF_LO_2_B) +#define PLANE_INPUT_CSC_POSTOFF_LO(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_LO_1(pipe), \ + _PLANE_INPUT_CSC_POSTOFF_LO_2(pipe)) #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 From patchwork Wed Oct 24 16:18:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10654791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C177613A9 for ; Wed, 24 Oct 2018 15:58:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B37F92AB0C for ; Wed, 24 Oct 2018 15:58:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A3B882ABFB; Wed, 24 Oct 2018 15:58:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 312162AB0C for ; Wed, 24 Oct 2018 15:58:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F6096E26B; Wed, 24 Oct 2018 15:58:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 73DF26E262 for ; Wed, 24 Oct 2018 15:58:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Oct 2018 08:58:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,420,1534834800"; d="scan'208";a="102934733" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga002.jf.intel.com with ESMTP; 24 Oct 2018 08:58:09 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Wed, 24 Oct 2018 21:48:13 +0530 Message-Id: <1540397893-3301-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1540397893-3301-1-git-send-email-uma.shankar@intel.com> References: <1540397893-3301-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v2 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Plane input CSC needs to be enabled to convert frambuffers from YUV to RGB. This is needed for bottom 3 planes on ICL, rest of the planes have hardcoded conversion and taken care by the legacy code. This patch defines the co-efficient values for YUV to RGB conversion in BT709 and BT601 formats. It programs the coefficients and enables the plane input csc unit in hardware. Note: This is currently untested and floated to get an early feedback on the design and implementation for this feature. In parallel, I will test this on actual ICL hardware and confirm with planar formats. v2: Addressed Maarten's and Ville's review comments and added the coefficients in a 2D array instead of independent Macros. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 49 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++----- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 3 files changed, 69 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 5127da2..de733cf 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -57,6 +57,11 @@ #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define CSC_RGB_TO_YUV_BV 0x1e080000 +/* Preoffset values for YUV to RGB Conversion */ +#define PREOFF_YUV_TO_RGB_HI 0x800 +#define PREOFF_YUV_TO_RGB_ME 0xF00 +#define PREOFF_YUV_TO_RGB_LO 0x800 + /* * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point * format). This macro takes the coefficient we want transformed and the @@ -643,6 +648,50 @@ int intel_color_check(struct drm_crtc *crtc, return -EINVAL; } +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *dev_priv = + to_i915(plane_state->base.plane->dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + enum pipe pipe = crtc->pipe; + struct intel_plane *intel_plane = + to_intel_plane(plane_state->base.plane); + enum plane_id plane = intel_plane->id; + + static const u32 input_csc_matrix[][6] = { + /* BT.601 full range YCbCr -> full range RGB */ + [DRM_COLOR_YCBCR_BT601] = { + 0x7AF87800, 0x0, 0x8B287800, + 0x9AC0, 0x7800, 0x7DD8, + }, + /* BT.709 full range YCbCr -> full range RGB */ + [DRM_COLOR_YCBCR_BT709] = { + 0x7C987800, 0x0, 0x9EF87800, + 0xABF8, 0x7800, 0x7ED8, + }, + }; + const u32 *csc = input_csc_matrix[plane_state->base.color_encoding]; + + I915_WRITE(PLANE_INPUT_CSC_RY_GY(pipe, plane), csc[0]); + I915_WRITE(PLANE_INPUT_CSC_BY(pipe, plane), csc[1]); + I915_WRITE(PLANE_INPUT_CSC_RU_GU(pipe, plane), csc[2]); + I915_WRITE(PLANE_INPUT_CSC_BU(pipe, plane), csc[3]); + I915_WRITE(PLANE_INPUT_CSC_RV_GV(pipe, plane), csc[4]); + I915_WRITE(PLANE_INPUT_CSC_BV(pipe, plane), csc[5]); + + I915_WRITE(PLANE_INPUT_CSC_PREOFF_HI(pipe, plane), + PREOFF_YUV_TO_RGB_HI); + I915_WRITE(PLANE_INPUT_CSC_PREOFF_ME(pipe, plane), + PREOFF_YUV_TO_RGB_ME); + I915_WRITE(PLANE_INPUT_CSC_PREOFF_LO(pipe, plane), + PREOFF_YUV_TO_RGB_LO); + + I915_WRITE(PLANE_INPUT_CSC_POSTOFF_HI(pipe, plane), 0x0); + I915_WRITE(PLANE_INPUT_CSC_POSTOFF_ME(pipe, plane), 0x0); + I915_WRITE(PLANE_INPUT_CSC_POSTOFF_LO(pipe, plane), 0x0); +} + void intel_color_init(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fe045ab..be65419 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3666,6 +3666,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); const struct drm_framebuffer *fb = plane_state->base.fb; + struct intel_plane *plane = to_intel_plane(plane_state->base.plane); + u32 plane_color_ctl = 0; if (INTEL_GEN(dev_priv) < 11) { @@ -3676,13 +3678,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); if (fb->format->is_yuv) { - if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; - else - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709; + if (!icl_is_hdr_plane(plane)) { + if (plane_state->base.color_encoding == + DRM_COLOR_YCBCR_BT709) + plane_color_ctl |= + PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; + else + plane_color_ctl |= + PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709; - if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) - plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; + if (plane_state->base.color_range == + DRM_COLOR_YCBCR_FULL_RANGE) + plane_color_ctl |= + PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; + } else { + icl_program_input_csc_coeff(crtc_state, plane_state); + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; + } } return plane_color_ctl; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index db24308..bd9e946 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); void intel_color_set_csc(struct drm_crtc_state *crtc_state); void intel_color_load_luts(struct drm_crtc_state *crtc_state); +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state); /* intel_lspcon.c */ bool lspcon_init(struct intel_digital_port *intel_dig_port);