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[88.207.97.133]) by smtp.googlemail.com with ESMTPSA id hk14sm3461452ejb.88.2020.09.09.12.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 12:48:23 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH 1/4] arm: dts: qcom: ipq4019: add more labels Date: Wed, 9 Sep 2020 21:48:13 +0200 Message-Id: <20200909194816.3125213-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200909194816.3125213-1-robert.marko@sartura.hr> References: <20200909194816.3125213-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Lets add labels to more commonly used nodes for easier modification in board DTS files. Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 3d056aada8d1..7bf1da916f25 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -190,7 +190,7 @@ gcc: clock-controller@1800000 { reg = <0x1800000 0x60000>; }; - rng@22000 { + prng: rng@22000 { compatible = "qcom,prng"; reg = <0x22000 0x140>; clocks = <&gcc GCC_PRNG_AHB_CLK>; @@ -310,7 +310,7 @@ cryptobam: dma@8e04000 { status = "disabled"; }; - crypto@8e3a000 { + crypto: crypto@8e3a000 { compatible = "qcom,crypto-v5.1"; reg = <0x08e3a000 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, @@ -396,7 +396,7 @@ blsp1_uart2: serial@78b0000 { dma-names = "rx", "tx"; }; - watchdog@b017000 { + watchdog: watchdog@b017000 { compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; reg = <0xb017000 0x40>; clocks = <&sleep_clk>; From patchwork Wed Sep 9 19:48:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11766141 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17701746 for ; Wed, 9 Sep 2020 19:49:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E995421D7D for ; Wed, 9 Sep 2020 19:49:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="KSMOBl5t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729663AbgIITtD (ORCPT ); Wed, 9 Sep 2020 15:49:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728207AbgIITs3 (ORCPT ); Wed, 9 Sep 2020 15:48:29 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02B51C061756 for ; Wed, 9 Sep 2020 12:48:27 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id i26so5254342ejb.12 for ; Wed, 09 Sep 2020 12:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a631SFYqGAi4ZEcUvZPpBm0hxLcC/ZMlJ2/z5Bt7trQ=; b=KSMOBl5tjoSiPq1aAb/sxmCKm5v8L6qpKEC4hlYAIz7A6XwGRwbjP8fFj0aW3PEv94 /sAqOoiEINWlGMJVUN6rRDGy6W3bVNbIuL0dt4Sk9P3sndd5mMG3/SelCfO2idzF6hBD KLi0D9hCms6q+h0y1lFJsvVBokE31qS0bk0Wndbh+jq0mBYEgInoiUYP0BexQEXl10YL EjJ0Zs7Weq7lJ7dgBn6e7TwocGt1g8SLRlfD83c3duySlfr7qavTlP3lDtZi0JiFfgRi Tn6Xq2xSno3DN/t0nJgMNcxiVY0g9e3OLCzzVz1gu6eArPmzrUfCph34HFYq+4GP3I8T V1yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a631SFYqGAi4ZEcUvZPpBm0hxLcC/ZMlJ2/z5Bt7trQ=; b=dFZDfnU50Pu1RqrwJycWF6Cd33CGIOGXNd4rEOTbv5+iFcgUA7LU5cpaBcwUCKFftY 2S44mH/m4BocfB5zXFe6bVjh5Smljz9CW2Ik3shX+FQOEQe7gpMDqeVHZqp/Qt7knOO+ T3d4TzBa7RAL1JihzgKYRxq0hRgDiteTmHjPLgFbg2yAN5v2Uy3bdWH2Ck4BEoOsoDra kykE+CiS5xJ1DvZsM8Jr0JCwMC6myhXCIYd1jolgIVnflw1bF1huLhxdRSgwIouuaOt9 JeSy79fa+m+2khmwFj3cX6juGGkjLWIJO5V3XbmybJSkssfwFDoKPf1KfZPfTbqESe86 2Sqg== X-Gm-Message-State: AOAM530Ne1Df3hzKLQzwd6Xc1hJYpmFtK+LA9Z+bW2XNXsa8WLcsqjiz 51lpg1r1bdXgK5lBuJx/8PtDRSM1qn/S0w== X-Google-Smtp-Source: ABdhPJw3OXDp248W+AGX4A/e9CF6exReYH3e8cW08qsenUu252YdZZvge8Bn7kKy+jrVMwziHph4Xw== X-Received: by 2002:a17:906:344e:: with SMTP id d14mr5505849ejb.42.1599680905660; Wed, 09 Sep 2020 12:48:25 -0700 (PDT) Received: from localhost.localdomain (dh207-97-133.xnet.hr. [88.207.97.133]) by smtp.googlemail.com with ESMTPSA id hk14sm3461452ejb.88.2020.09.09.12.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 12:48:25 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH 2/4] arm: dts: add 8devices Jalapeno Date: Wed, 9 Sep 2020 21:48:14 +0200 Message-Id: <20200909194816.3125213-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200909194816.3125213-1-robert.marko@sartura.hr> References: <20200909194816.3125213-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 8devices Jalapeno is a dual-band SoM, based on Qualcomm IPQ4018 + QCA8072 platform. Specification: QCA IPQ4018, Quad core ARM v7 Cortex A7 717MHz 256 MB of DDR3 RAM 8 MB of SPI NOR flash 128 MB of Winbond SPI NAND flash WLAN1: Qualcomm Atheros QCA4018 2.4GHz 802.11bgn 2:2x2 WLAN2: Qualcomm Atheros QCA4018 5GHz 802.11a/n/ac 2:2x2 ETH: Qualcomm Atheros QCA8072 Gigabit Switch (1 x LAN, 1 x WAN) Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts | 215 ++++++++++++++++++++ 2 files changed, 216 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..9b474208057d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -890,6 +890,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ + qcom-ipq4018-jalapeno.dtb \ qcom-ipq4019-ap.dk01.1-c1.dtb \ qcom-ipq4019-ap.dk04.1-c1.dtb \ qcom-ipq4019-ap.dk04.1-c3.dtb \ diff --git a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts new file mode 100644 index 000000000000..3def87e76c48 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +// Copyright (c) 2018, Robert Marko + +#include "qcom-ipq4019.dtsi" +#include +#include +#include + +/ { + model = "8devices Jalapeno"; + compatible = "8dev,jalapeno"; +}; + +&tlmm { + mdio_pins: mdio_pinmux { + pinmux_1 { + pins = "gpio53"; + function = "mdio"; + }; + + pinmux_2 { + pins = "gpio52"; + function = "mdc"; + }; + + pinconf { + pins = "gpio52", "gpio53"; + bias-pull-up; + }; + }; + + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + pin { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + + pin_cs { + function = "gpio"; + pins = "gpio54", "gpio59"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_spi1 { + status = "okay"; + + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>; + + flash@0 { + status = "okay"; + + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x00000000 0x00040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x00040000 0x00020000>; + read-only; + }; + + partition@60000 { + label = "QSEE"; + reg = <0x00060000 0x00060000>; + read-only; + }; + + partition@c0000 { + label = "CDT"; + reg = <0x000c0000 0x00010000>; + read-only; + }; + + partition@d0000 { + label = "DDRPARAMS"; + reg = <0x000d0000 0x00010000>; + read-only; + }; + + partition@e0000 { + label = "u-boot-env"; + reg = <0x000e0000 0x00010000>; + }; + + partition@f0000 { + label = "u-boot"; + reg = <0x000f0000 0x00080000>; + read-only; + }; + + partition@170000 { + label = "ART"; + reg = <0x00170000 0x00010000>; + read-only; + }; + }; + }; + + spi-nand@1 { + status = "okay"; + + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x04000000>; + }; + + partition@4000000 { + label = "ubi2"; + reg = <0x04000000 0x04000000>; + }; + }; + }; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +}; + +&wifi0 { + status = "okay"; + + qcom,ath10k-calibration-variant = "8devices-Jalapeno"; +}; + +&wifi1 { + status = "okay"; + + qcom,ath10k-calibration-variant = "8devices-Jalapeno"; +}; + +&usb3_ss_phy { + status = "okay"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; From patchwork Wed Sep 9 19:48:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11766137 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 85C45112E for ; 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[88.207.97.133]) by smtp.googlemail.com with ESMTPSA id hk14sm3461452ejb.88.2020.09.09.12.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 12:48:26 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH 3/4] arm: dts: add Alfa Network AP120C-AC Date: Wed, 9 Sep 2020 21:48:15 +0200 Message-Id: <20200909194816.3125213-4-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200909194816.3125213-1-robert.marko@sartura.hr> References: <20200909194816.3125213-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org ALFA Network AP120C-AC is a dual-band ceiling AP, based on Qualcomm IPQ4018 + QCA8075 platform. Specification: - Qualcomm IPQ4018 (717 MHz) - 256 MB of RAM (DDR3) - 16 MB (SPI NOR) + 128 or 512 MB (SPI NAND) of flash - 2x Gbps Ethernet, with 802.3af PoE support in one port - 2T2R 2.4/5 GHz (IPQ4018), with ext. FEMs (QFE1952, QFE1922) - 3x U.FL connectors - 1x 1.8 dBi (Bluetooth) and 2x 3/5 dBi dual-band (Wi-Fi) antennas - Atmel/Microchip AT97SC3205T TPM module (I2C bus) - TI CC2540 Bluetooth LE module (USB 2.0 bus) - 1x button (reset) - 1x USB 2.0 - DC jack for main power input (12 V) - UART header available on PCB (2.0 mm pitch) This adds DTS for both the generic and custom Bit edition for Sartura. Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/qcom-ipq4018-ap120c-ac-bit.dts | 28 ++ arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts | 27 ++ arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 255 ++++++++++++++++++ 4 files changed, 312 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts create mode 100644 arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts create mode 100644 arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9b474208057d..246d82fc5fcd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -890,6 +890,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ + qcom-ipq4018-ap120c-ac.dtb \ + qcom-ipq4018-ap120c-ac-bit.dtb \ qcom-ipq4018-jalapeno.dtb \ qcom-ipq4019-ap.dk01.1-c1.dtb \ qcom-ipq4019-ap.dk04.1-c1.dtb \ diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts new file mode 100644 index 000000000000..028ac8e24797 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq4018-ap120c-ac.dtsi" + +/ { + model = "ALFA Network AP120C-AC Bit"; + + leds { + compatible = "gpio-leds"; + + power { + label = "ap120c-ac:green:power"; + gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + wlan { + label = "ap120c-ac:green:wlan"; + gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + }; + + support { + label = "ap120c-ac:green:support"; + gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts new file mode 100644 index 000000000000..b7916fc26d68 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq4018-ap120c-ac.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + status: status { + label = "ap120c-ac:blue:status"; + gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + wlan2g { + label = "ap120c-ac:green:wlan2g"; + gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + wlan5g { + label = "ap120c-ac:red:wlan5g"; + gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi new file mode 100644 index 000000000000..20a0844604ca --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq4019.dtsi" +#include +#include +#include + +/ { + model = "ALFA Network AP120C-AC"; + compatible = "alfa-network,ap120c-ac"; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&tlmm { + i2c0_pins: i2c0_pinmux { + mux_i2c { + function = "blsp_i2c0"; + pins = "gpio58", "gpio59"; + drive-strength = <16>; + bias-disable; + }; + }; + + mdio_pins: mdio_pinmux { + mux_mdio { + pins = "gpio53"; + function = "mdio"; + bias-pull-up; + }; + + mux_mdc { + pins = "gpio52"; + function = "mdc"; + bias-pull-up; + }; + }; + + serial0_pins: serial0_pinmux { + mux_uart { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi0_pins: spi0_pinmux { + mux_spi { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; + }; + + mux_cs { + function = "gpio"; + pins = "gpio54", "gpio4"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + usb-power { + line-name = "USB-power"; + gpios = <1 GPIO_ACTIVE_HIGH>; + gpio-hog; + output-high; + }; +}; + +&watchdog { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_i2c3 { + status = "okay"; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + tpm@29 { + compatible = "atmel,at97sc3204t"; + reg = <0x29>; + }; +}; + +&blsp1_spi1 { + status = "okay"; + + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x00000000 0x00040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x00040000 0x00020000>; + read-only; + }; + + partition@60000 { + label = "QSEE"; + reg = <0x00060000 0x00060000>; + read-only; + }; + + partition@c0000 { + label = "CDT"; + reg = <0x000c0000 0x00010000>; + read-only; + }; + + partition@d0000 { + label = "DDRPARAMS"; + reg = <0x000d0000 0x00010000>; + read-only; + }; + + partition@e0000 { + label = "u-boot-env"; + reg = <0x000e0000 0x00010000>; + }; + + partition@f0000 { + label = "u-boot"; + reg = <0x000f0000 0x00080000>; + read-only; + }; + + partition@170000 { + label = "ART"; + reg = <0x00170000 0x00010000>; + read-only; + }; + + partition@180000 { + label = "priv_data1"; + reg = <0x00180000 0x00010000>; + read-only; + }; + + partition@190000 { + label = "priv_data2"; + reg = <0x00190000 0x00010000>; + read-only; + }; + }; + }; + + nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x04000000>; + }; + + partition@4000000 { + label = "ubi2"; + reg = <0x04000000 0x04000000>; + }; + }; + }; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial0_pins>; + pinctrl-names = "default"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +}; + +&wifi0 { + status = "okay"; +}; + +&wifi1 { + status = "okay"; + qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; + + dwc3@8a00000 { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; + }; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; From patchwork Wed Sep 9 19:48:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11766139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F1A7746 for ; Wed, 9 Sep 2020 19:49:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 003D821D7E for ; Wed, 9 Sep 2020 19:49:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="Cw6hH7ai" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728626AbgIITsv (ORCPT ); Wed, 9 Sep 2020 15:48:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727055AbgIITsf (ORCPT ); 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[88.207.97.133]) by smtp.googlemail.com with ESMTPSA id hk14sm3461452ejb.88.2020.09.09.12.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 12:48:28 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH 4/4] arm: dts: add 8devices Habanero DVK Date: Wed, 9 Sep 2020 21:48:16 +0200 Message-Id: <20200909194816.3125213-5-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200909194816.3125213-1-robert.marko@sartura.hr> References: <20200909194816.3125213-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 8devices Habanero DVK is a dual-band SoM development kit based on Qualcomm IPQ4019 + QCA8075 platform. Specs are: CPU: QCA IPQ4019 RAM: DDR3L 512MB Storage: 32MB SPI-NOR and optional Parallel SLC NAND(Some boards ship with it and some without) WLAN1: 2.4 GHz built into IPQ4019 (802.11n) 2x2 WLAN2: 5 GHz built into IPO4019 (802.11ac Wawe-2) 2x2 Ethernet: 5x Gbit LAN (QCA 8075) USB: 1x USB 2.0 and 1x USB 3.0 (Both built into IPQ4019) MicroSD slot (Uses SD controller built into IPQ4019) SDIO3.0/EMMC slot (Uses the same SD controller) Mini PCI-E Gen 2.0 slot (Built into IPQ4019) 5x LEDs (4 GPIO controllable) 2x Pushbutton (1 is connected to GPIO, other to SoC reset) LCD ZIF socket (Uses the LCD controller built into IPQ4019 which has no driver support) 1x UART 115200 rate on J18 2x breakout development headers 12V DC Jack for power DIP switch for bootstrap configuration Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/qcom-ipq4019-habanero-dvk.dts | 305 ++++++++++++++++++ 2 files changed, 306 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246d82fc5fcd..004262e0d699 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -898,6 +898,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk04.1-c3.dtb \ qcom-ipq4019-ap.dk07.1-c1.dtb \ qcom-ipq4019-ap.dk07.1-c2.dtb \ + qcom-ipq4019-habanero-dvk.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ qcom-msm8660-surf.dtb \ diff --git a/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts b/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts new file mode 100644 index 000000000000..d4236a68fd31 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2019, Robert Marko */ + +#include "qcom-ipq4019.dtsi" +#include +#include +#include + +/ { + model = "8devices Habanero DVK"; + compatible = "8dev,habanero-dvk"; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: status { + label = "habanero-dvk:green:status"; + gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + + led_upgrade: upgrade { + label = "habanero-dvk:green:upgrade"; + gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "habanero-dvk:green:wlan2g"; + gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + wlan5g { + label = "habanero-dvk:green:wlan5g"; + gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + }; +}; + +&vqmmc { + status = "okay"; +}; + +&sdhci { + status = "okay"; + + pinctrl-0 = <&sd_pins>; + pinctrl-names = "default"; + cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vqmmc>; +}; + +&qpic_bam { + status = "okay"; +}; + +&tlmm { + mdio_pins: mdio_pinmux { + mux_1 { + pins = "gpio6"; + function = "mdio"; + bias-pull-up; + }; + + mux_2 { + pins = "gpio7"; + function = "mdc"; + bias-pull-up; + }; + }; + + serial_pins: serial_pinmux { + mux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + drive-strength = <12>; + bias-disable; + }; + + pinmux_cs { + function = "gpio"; + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + nand_pins: nand_pins { + pullups { + pins = "gpio52", "gpio53", "gpio58", "gpio59"; + function = "qpic"; + bias-pull-up; + }; + + pulldowns { + pins = "gpio54", "gpio55", "gpio56", "gpio57", + "gpio60", "gpio62", "gpio63", "gpio64", + "gpio65", "gpio66", "gpio67", "gpio68", + "gpio69"; + function = "qpic"; + bias-pull-down; + }; + }; + + sd_pins: sd_pins { + pinmux { + function = "sdio"; + pins = "gpio23", "gpio24", "gpio25", "gpio26", + "gpio28", "gpio29", "gpio30", "gpio31"; + drive-strength = <10>; + }; + + pinmux_sd_clk { + function = "sdio"; + pins = "gpio27"; + drive-strength = <16>; + }; + + pinmux_sd7 { + function = "sdio"; + pins = "gpio32"; + drive-strength = <10>; + bias-disable; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_spi1 { + status = "okay"; + + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <24000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "MIBIB"; + reg = <0x00040000 0x00020000>; + read-only; + }; + partition@60000 { + label = "QSEE"; + reg = <0x00060000 0x00060000>; + read-only; + }; + partition@c0000 { + label = "CDT"; + reg = <0x000c0000 0x00010000>; + read-only; + }; + partition@d0000 { + label = "DDRPARAMS"; + reg = <0x000d0000 0x00010000>; + read-only; + }; + partition@e0000 { + label = "APPSBLENV"; /* uboot env */ + reg = <0x000e0000 0x00010000>; + read-only; + }; + partition@f0000 { + label = "APPSBL"; /* uboot */ + reg = <0x000f0000 0x00080000>; + read-only; + }; + partition@170000 { + label = "ART"; + reg = <0x00170000 0x00010000>; + read-only; + }; + partition@180000 { + label = "cfg"; + reg = <0x00180000 0x00040000>; + }; + partition@1c0000 { + label = "firmware"; + compatible = "denx,fit"; + reg = <0x001c0000 0x01e40000>; + }; + }; + }; +}; + +/* Some DVK boards ship without NAND */ +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; + + /* Free slot for use */ + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; +}; + +&wifi0 { + status = "okay"; + + qcom,ath10k-calibration-variant = "8devices-Habanero"; +}; + +&wifi1 { + status = "okay"; + + qcom,ath10k-calibration-variant = "8devices-Habanero"; +}; + +&usb3_ss_phy { + status = "okay"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +};