From patchwork Wed Sep 9 22:53:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 11766319 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3341392C for ; Wed, 9 Sep 2020 22:54:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 038BF21D90 for ; Wed, 9 Sep 2020 22:54:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="tSbbd0LY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 038BF21D90 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF30B6F575; Wed, 9 Sep 2020 22:54:38 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-eopbgr750083.outbound.protection.outlook.com [40.107.75.83]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E4D96F56A; Wed, 9 Sep 2020 22:54:37 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ei/kEyBq1efU6aSN/jGPOs5edxSrky408DmqCVss3UY7u0A7kk/jdFlglCQO2e8Y0ADIzi80FZEVDGrDeYZ0ywBOy+69lXlN7MDneBbWzAJJunKuyA9eNU24MSd3xjiOEp8i5ihzznKApm3JKWqZK7ZWWgYzofnf1KCD0D52WVG6HbXQZ6XSJUTHtL76JNY0D617Fk6y7/G8CG9Zm9mz9BC8wcHlsWcSc7yD8ZfIxVkc4JnLI1aXAV3RviV/hLahvLSCxZ4J9YqJdXZjNx0g6f9YN1SXw6mJuopJk0sMibKbbsFITh3eB0lEL2N9En39bvHCwZt5jiefTbv4cvb85g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LsGkSND//QMcm6QNMK9AopcnDe5fv9Dj0RZojN/pOUQ=; b=bKBhiAfCABXXdSk8wPTzN+s78kssWS4R9nCeT/uU6EjvEZicIHUADxpTyxzXzZ/Pj+onVzK5FHvq+jObf6NH1OMNwD+njwrWqz7Rmgm9NbYxHAWH4MQ1jeFb9Tb77U+1+53D5PJDjdIl278M0Rfr7pPxl7W1PHChig1OxNoS71eeLFk2HwVE6DWM1abgbYbQ+yJy0hHzbITpMAtWIZRM9ABpKQDc1Kn5NW1/1irV0tHmliDOgi8uBMozCUemv5Sw6Qefzhe2C7wD5PR8huytKcTF7TAmHnkyOdWi3r9q0HYLoius2ntTIzzabcCKOu5+OU/DyppSkHIfJYC1AP31Jg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LsGkSND//QMcm6QNMK9AopcnDe5fv9Dj0RZojN/pOUQ=; b=tSbbd0LYNHKpsDGps6SqbkO2B0Il00Os71DIixFLhLhiuhKDkDHiE6WYw7/eGHRV21VhwRF/FEGC4xqJVgGzqOKYokQJFtTOh7NElXy9ITibE/Akk1fiEcywP5E5a8nGyd/gJatRcNBe0Mlo6sWOkya6Yd7jO9wsSCzSzAxN6eY= Authentication-Results: lists.freedesktop.org; dkim=none (message not signed) header.d=none; lists.freedesktop.org; dmarc=none action=none header.from=amd.com; Received: from DM6PR12MB4124.namprd12.prod.outlook.com (2603:10b6:5:221::20) by DM6PR12MB2986.namprd12.prod.outlook.com (2603:10b6:5:39::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.18; Wed, 9 Sep 2020 22:54:35 +0000 Received: from DM6PR12MB4124.namprd12.prod.outlook.com ([fe80::25a1:ace4:4ca8:167e]) by DM6PR12MB4124.namprd12.prod.outlook.com ([fe80::25a1:ace4:4ca8:167e%8]) with mapi id 15.20.3370.016; Wed, 9 Sep 2020 22:54:35 +0000 From: Rodrigo Siqueira To: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] drm/amd/display: Rework registers tracepoint Date: Wed, 9 Sep 2020 18:53:50 -0400 Message-Id: <20200909225352.4072030-2-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909225352.4072030-1-Rodrigo.Siqueira@amd.com> References: <20200909225352.4072030-1-Rodrigo.Siqueira@amd.com> X-ClientProxiedBy: YT1PR01CA0143.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:2f::22) To DM6PR12MB4124.namprd12.prod.outlook.com (2603:10b6:5:221::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from atma2.hitronhub.home (2607:fea8:56e0:6d60::10ec) by YT1PR01CA0143.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:2f::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Wed, 9 Sep 2020 22:54:34 +0000 X-Mailer: git-send-email 2.28.0 X-Originating-IP: [2607:fea8:56e0:6d60::10ec] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 74fca6f5-655d-4d6b-cf00-08d85513529f X-MS-TrafficTypeDiagnostic: DM6PR12MB2986: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1303; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sVvX2uDJN0MjymvzlVcDMoQLydpOu+/mTCp51QqKvXiq/XFzTJos30E2pqb63QOi3oKyM2hOMADraQYCoAuPGef/PWcc96dho4Z2ji4IvbbmOZ7DT1DDncd3MzKKECRQyyZyabG05S23QvGOWIxLLqJKnQh23g59uWxEvch1CkEoVmQVyxAhwPWQqNOorTZwTX7Z8tnCJ6VHPP82hSjuf8sdywH5q3AChqZT44ZBQolcijymHwjt7MJqigHTdMmGkGUCDnrFBze3veQReWgA5YFk5Fb++abRHkUxD3fhD4c6I4IrI1frMONbWkJWRlMhTQb13h2+bWSDaZ1cWjCwng== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR12MB4124.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(396003)(136003)(376002)(346002)(39860400002)(2906002)(8936002)(6486002)(6512007)(5660300002)(16526019)(186003)(478600001)(83380400001)(4326008)(8676002)(52116002)(316002)(1076003)(66476007)(6506007)(6666004)(86362001)(2616005)(66556008)(54906003)(36756003)(66946007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: uCMS0QiZrmtwwYiUzHZylOadFnNajiTnNgfdznwwOuptXq9FY2l1P9lgeBS3/6D3jO5t5ljV+Quxr7N6Qtt9s/0jYME18BZyeo/AWQyEF5FyuqVKqdsvJE3LzhXtpmsUrM6ff9AgEhxjfRPuIIJ/c2vXsrhe62VWt6/5Yp/TpNXzrgduO3J6VColidDwNnwoEDQ2QFhZ98XQ20yfbRWGKBTMwvACfpIryX36ddNMtiK4nCrEqiZJK6z3/dKvA4HH+OLeJHqY0hxB2Sc2yri6l43d8tiLSOsWRalEJUKNWOWuHjekwU9wUKztr+MtZx2onUUTS3VSRVXhm6gcMAqlwhwplwquRtCt3YQ+ifa26+Bpt8syVEkO+x72ceOdCmARsqpL/uV36GohFBRAkb2bWJlGKJXRicuY0JuzEyG4LqLXWRWPDFgGB07rHOsnjSXdG9kBfyq2JqP8OX8oN2xFonw1irDysgRe/4UBi4ON95sS4YMGf8tjbkB+lcIsrNWbkwRq7xu0/nCAsDYGivIqCpHH3aYTZuFv9XLVHOBvukWMdkJicTr9nhrQ2QPh2kngSd4HaRsZ74XPACpnenRlhsbXn2XDUwUhSvdq+DR6tU9rga+iDgiIhodG1hD6h4nv/Kf2pf9Lh2CoBYYT9Dm2mRdY/LMP0nOfI6ck4M0Nt00Ub+sJ1+kptTKAXSrZGIYy X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74fca6f5-655d-4d6b-cf00-08d85513529f X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB4124.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2020 22:54:35.3900 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: O4ycvR4NZDNEYtGMVVREsRpgL1i1y26Dotw3yqCyidvk7q+fDGlXI+u0ZRBa0PHybf/GSdP4DWZeDPkyqwWeJA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2986 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , Nicholas Kazlauskas , David Airlie , hersenxs.wu@amd.com, Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" amdgpu_dc_rreg and amdgpu_dc_wreg are very similar, for this reason, this commits abstract these two events by using DECLARE_EVENT_CLASS and create an instance of it for each one of these events. Signed-off-by: Rodrigo Siqueira --- .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 55 ++++++++----------- 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index d898981684d5..dd34e11b1079 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -31,40 +31,33 @@ #include -TRACE_EVENT(amdgpu_dc_rreg, - TP_PROTO(unsigned long *read_count, uint32_t reg, uint32_t value), - TP_ARGS(read_count, reg, value), - TP_STRUCT__entry( - __field(uint32_t, reg) - __field(uint32_t, value) - ), - TP_fast_assign( - __entry->reg = reg; - __entry->value = value; - *read_count = *read_count + 1; - ), - TP_printk("reg=0x%08lx, value=0x%08lx", - (unsigned long)__entry->reg, - (unsigned long)__entry->value) -); +DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, + TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), + TP_ARGS(count, reg, value), -TRACE_EVENT(amdgpu_dc_wreg, - TP_PROTO(unsigned long *write_count, uint32_t reg, uint32_t value), - TP_ARGS(write_count, reg, value), - TP_STRUCT__entry( - __field(uint32_t, reg) - __field(uint32_t, value) - ), - TP_fast_assign( - __entry->reg = reg; - __entry->value = value; - *write_count = *write_count + 1; - ), - TP_printk("reg=0x%08lx, value=0x%08lx", - (unsigned long)__entry->reg, - (unsigned long)__entry->value) + TP_STRUCT__entry( + __field(uint32_t, reg) + __field(uint32_t, value) + ), + + TP_fast_assign( + __entry->reg = reg; + __entry->value = value; + *count = *count + 1; + ), + + TP_printk("reg=0x%08lx, value=0x%08lx", + (unsigned long)__entry->reg, + (unsigned long)__entry->value) ); +DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg, + TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), + TP_ARGS(count, reg, value)); + +DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg, + TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), + TP_ARGS(count, reg, value)); TRACE_EVENT(amdgpu_dc_performance, TP_PROTO(unsigned long read_count, unsigned long write_count, From patchwork Wed Sep 9 22:53:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 11766317 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 338A592C for ; Wed, 9 Sep 2020 22:54:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EE53921D90 for ; Wed, 9 Sep 2020 22:54:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="n+X6iN44" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE53921D90 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 787C46F572; Wed, 9 Sep 2020 22:54:38 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-eopbgr750083.outbound.protection.outlook.com [40.107.75.83]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6091A6ECE2; Wed, 9 Sep 2020 22:54:37 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YPMZVYRk5WMIASLZQMvrj9GX4ILF6tSNl70Gz5acVGbHWNQCvsuM5Rhcn+nU6Wghdrzx7fu8bG3+qgcDlw5Kn1N0/vy1MBRn7SBZkQRlkzppaNDriA7E7XjuTKmhkat9tJarno6I/RsByjxVyUv9i+wGF7EAEEIMnmN186ODEqwzEQKPBTDCM5rE/Id4Z7uH2gX3B4xMUcXXEoMGcoUM1JDLkCLqsmAeY9tm0te0xX2dYCBa76nXR3SYmuxAuquN9afMYjD3T7ZiAdGTDUxEituzQiXngaxKZdSz1TR4mXPK/+Ba0oCc1oaySvRJshuqfcYCmdQu6h46GwSsfrJzIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=weOxQUQB5RUpbq6rgfqy3vqokZqHIdeAziqdnzCsEsA=; b=SS40Xw+QSWlxLGT72A90jyV83Pnk4vHvM3NYS1OrspcDjY/khHGLEo5DJWcXBOhnDYQNZcyAl5WZa1LerW9X8QusjQJSUvYbeEJcRAJTET5Ug2ZuFz0cyGtuGU6efNcvQNgdIVIcwK41OF3tYUq053JfqQDrBgbwMeUpXJGoD6ekszP42OTV1/2VQSEupckrlzm5DfTCR6Jzeq2IFdw0CK9QJYN3ootNFXgZfgThX+AevAHGDkQt+7EEkBE86y7Yrwwa0m2lsshP23rolzj90zCCxUbL3Df7kQVtUh7f8q3VzJMr3gMfW8w6jB3iFct77X8j4HrqOzYgHCUL9y8uuw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=weOxQUQB5RUpbq6rgfqy3vqokZqHIdeAziqdnzCsEsA=; b=n+X6iN44kI8XKILhiY3Ml9e0IaHNuNk98iqTHX4Ivg/mL0a+NWucH/6liTanCcuM1U3ujFfLJz5NmHnJh49/GLkZ3E+TXsrJQkkFNruVBh2xbmBw3Qww3ID5kgx+NLRWdmJW1DeLIawzBBZmhWvmO+o963dtRhLvEJ/5G+YRY50= Authentication-Results: lists.freedesktop.org; dkim=none (message not signed) header.d=none; lists.freedesktop.org; dmarc=none action=none header.from=amd.com; Received: from DM6PR12MB4124.namprd12.prod.outlook.com (2603:10b6:5:221::20) by DM6PR12MB2986.namprd12.prod.outlook.com (2603:10b6:5:39::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.18; Wed, 9 Sep 2020 22:54:36 +0000 Received: from DM6PR12MB4124.namprd12.prod.outlook.com ([fe80::25a1:ace4:4ca8:167e]) by DM6PR12MB4124.namprd12.prod.outlook.com ([fe80::25a1:ace4:4ca8:167e%8]) with mapi id 15.20.3370.016; Wed, 9 Sep 2020 22:54:36 +0000 From: Rodrigo Siqueira To: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] drm/amd/display: Add tracepoint for amdgpu_dm Date: Wed, 9 Sep 2020 18:53:51 -0400 Message-Id: <20200909225352.4072030-3-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909225352.4072030-1-Rodrigo.Siqueira@amd.com> References: <20200909225352.4072030-1-Rodrigo.Siqueira@amd.com> X-ClientProxiedBy: YT1PR01CA0143.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:2f::22) To DM6PR12MB4124.namprd12.prod.outlook.com (2603:10b6:5:221::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from atma2.hitronhub.home (2607:fea8:56e0:6d60::10ec) by YT1PR01CA0143.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:2f::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Wed, 9 Sep 2020 22:54:35 +0000 X-Mailer: git-send-email 2.28.0 X-Originating-IP: [2607:fea8:56e0:6d60::10ec] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d8dcce8b-eddb-4524-2772-08d855135316 X-MS-TrafficTypeDiagnostic: DM6PR12MB2986: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:83; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rCNFw9to8Vpan/qr/VaK3XGSC8vs9IoNfm4tF1XMeFo+0SnbpwifTV1G6WgNxcH2jXozcNvTQ3DO2W6t/093FVaZBJayN0ZSF8M29VDOlOIdmO01KSWIytcj3KFbn+oBlIt7T9HijdJpYFar17HhxRtJO3HYG5Fw/ZTHfIJLCtVBgM4udd5qlcK7e+Oqp+jkI10qUxhF6JdRmYfqn5v/q8OUjnTS8BIExrAVYKYoAnk8cxQPei/yqPXbEbWFT8UIWtb5yDOoV35IB1DBSR5iDSkPtq+NoH2i6POUU9oWRSVTPfrLibFANiihhh6KVFunwUicaPp8MW6PP9ibwAoUvg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR12MB4124.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(396003)(136003)(376002)(346002)(39860400002)(2906002)(8936002)(6486002)(30864003)(6512007)(5660300002)(16526019)(186003)(478600001)(83380400001)(4326008)(8676002)(52116002)(316002)(1076003)(66476007)(6506007)(6666004)(86362001)(2616005)(66556008)(54906003)(36756003)(66946007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: 2sfFgZr0gI2y2aCiKMZQz3WuHBN7IcfJlac9mYUplU79f735a4jAJZSer7XnKFO5bubmk6cBSI35Py27C9mV+21PtVXu/LzOPIsDp4I7jed5nqdwhJH3YtXBnuNR/eCcNFWW84YJ6qUSR+P1W4yFPTB0gW0JgZXiZWtRWI4Hz766cmu2t9W6ejfqhQb1v+jhPOAdunR57wSCkwJlBTWf4DNbzGxtwmoziK5IObctRs0mbieEtIcx861gryRZ8qcEpyrxBmoCffbOssaPH/XZrIfpjW/XbxA32kHWqjye+P1xxo8av5ZDw7pfgxCS4xCCNMjzO53Jd7YxcHY6BvhBgCmpZCGXjJdOE+e4Y0ieNkdmThuCGG4FdR3rm9wAyreSRYWJuKtHBh0gcB1lXruOfs5YGhHeh7TL+YXVf2Zl1iuGb9cNOOZrY9FfZtJ8pcx2YvjRwe2r9JCAxRVK7e299TBUk19xYaMmdGh12+WcAf+ZtyHjAa2nH/pir9PSjcHp8QvdwTxgRC2TP1gKNCPPsQ1iXzHtwUxZXPWAZ7b44eLo2ep+4/56hvxtnB5AROUbOXcU1wXFG1PRLLZUnWSJhfq4+9cRRBHoCCVSGimt4Pu0GO8WWrdF/xlTJGaVF9BoMX4myw1SwYgileZyFfJrFZpXX41EPSgqOGjwSoCfHp5DxmQLTB3XExuPUsKUXLRK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d8dcce8b-eddb-4524-2772-08d855135316 X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB4124.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2020 22:54:36.1437 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: N+Ky+lwguFwaSjF7kKEiSYFfyNCWy4X5x9m2WxEmu//angxmTVTRH8CsDTCa1gRgPcIMdms5zsXScKL8G2Ntxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2986 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , Nicholas Kazlauskas , David Airlie , hersenxs.wu@amd.com, Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Debug amdgpu_dm could be a complicated task, therefore, this commit adds tracepoints in some convenient functions such as plane and connector check inside amdgpu_dm. Co-developed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Kazlauskas Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 ++ .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 287 ++++++++++++++++++ 2 files changed, 304 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cb624ee70545..552ca67c2a71 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5424,6 +5424,8 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, struct drm_crtc_state *new_crtc_state; int ret; + trace_amdgpu_dm_connector_atomic_check(new_con_state); + if (!crtc) return 0; @@ -5542,6 +5544,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); int ret = -EINVAL; + trace_amdgpu_dm_crtc_atomic_check(state); + dm_update_crtc_active_planes(crtc, state); if (unlikely(!dm_crtc_state->stream && @@ -5916,6 +5920,8 @@ static int dm_plane_atomic_check(struct drm_plane *plane, struct drm_crtc_state *new_crtc_state; int ret; + trace_amdgpu_dm_plane_atomic_check(state); + dm_plane_state = to_dm_plane_state(state); if (!dm_plane_state->dc_state) @@ -5956,6 +5962,8 @@ static void dm_plane_atomic_async_update(struct drm_plane *plane, struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(new_state->state, plane); + trace_amdgpu_dm_atomic_update_cursor(new_state); + swap(plane->state->fb, new_state->fb); plane->state->src_x = new_state->src_x; @@ -7546,6 +7554,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) int crtc_disable_count = 0; bool mode_set_reset_required = false; + trace_amdgpu_dm_atomic_commit_tail_begin(state); + drm_atomic_helper_update_legacy_modeset_state(dev, state); dm_state = dm_atomic_get_new_state(state); @@ -8616,6 +8626,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, int ret, i; bool lock_and_validation_needed = false; + trace_amdgpu_dm_atomic_check_begin(state); + ret = drm_atomic_helper_check_modeset(dev, state); if (ret) goto fail; @@ -8912,6 +8924,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, /* Must be success */ WARN_ON(ret); + + trace_amdgpu_dm_atomic_check_finish(state, ret); + return ret; fail: @@ -8922,6 +8937,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, else DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); + trace_amdgpu_dm_atomic_check_finish(state, ret); + return ret; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index dd34e11b1079..5fb4c4a5c349 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -30,6 +30,12 @@ #define _AMDGPU_DM_TRACE_H_ #include +#include +#include +#include +#include +#include +#include DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), @@ -89,6 +95,287 @@ TRACE_EVENT(amdgpu_dc_performance, (unsigned long)__entry->write_delta, (unsigned long)__entry->writes) ); + +TRACE_EVENT(amdgpu_dm_connector_atomic_check, + TP_PROTO(const struct drm_connector_state *state), + TP_ARGS(state), + + TP_STRUCT__entry( + __field(uint32_t, conn_id) + __field(const struct drm_connector_state *, conn_state) + __field(const struct drm_atomic_state *, state) + __field(const struct drm_crtc_commit *, commit) + __field(uint32_t, crtc_id) + __field(uint32_t, best_encoder_id) + __field(enum drm_link_status, link_status) + __field(bool, self_refresh_aware) + __field(enum hdmi_picture_aspect, picture_aspect_ratio) + __field(unsigned int, content_type) + __field(unsigned int, hdcp_content_type) + __field(unsigned int, content_protection) + __field(unsigned int, scaling_mode) + __field(u32, colorspace) + __field(u8, max_requested_bpc) + __field(u8, max_bpc) + ), + + TP_fast_assign( + __entry->conn_id = state->connector->base.id; + __entry->conn_state = state; + __entry->state = state->state; + __entry->commit = state->commit; + __entry->crtc_id = state->crtc ? state->crtc->base.id : 0; + __entry->best_encoder_id = state->best_encoder ? + state->best_encoder->base.id : 0; + __entry->link_status = state->link_status; + __entry->self_refresh_aware = state->self_refresh_aware; + __entry->picture_aspect_ratio = state->picture_aspect_ratio; + __entry->content_type = state->content_type; + __entry->hdcp_content_type = state->hdcp_content_type; + __entry->content_protection = state->content_protection; + __entry->scaling_mode = state->scaling_mode; + __entry->colorspace = state->colorspace; + __entry->max_requested_bpc = state->max_requested_bpc; + __entry->max_bpc = state->max_bpc; + ), + + TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u " + "best_encoder_id=%u link_status=%d self_refresh_aware=%d " + "picture_aspect_ratio=%d content_type=%u " + "hdcp_content_type=%u content_protection=%u scaling_mode=%u " + "colorspace=%u max_requested_bpc=%u max_bpc=%u", + __entry->conn_id, __entry->conn_state, __entry->state, + __entry->commit, __entry->crtc_id, __entry->best_encoder_id, + __entry->link_status, __entry->self_refresh_aware, + __entry->picture_aspect_ratio, __entry->content_type, + __entry->hdcp_content_type, __entry->content_protection, + __entry->scaling_mode, __entry->colorspace, + __entry->max_requested_bpc, __entry->max_bpc) +); + +TRACE_EVENT(amdgpu_dm_crtc_atomic_check, + TP_PROTO(const struct drm_crtc_state *state), + TP_ARGS(state), + + TP_STRUCT__entry( + __field(const struct drm_atomic_state *, state) + __field(const struct drm_crtc_state *, crtc_state) + __field(const struct drm_crtc_commit *, commit) + __field(uint32_t, crtc_id) + __field(bool, enable) + __field(bool, active) + __field(bool, planes_changed) + __field(bool, mode_changed) + __field(bool, active_changed) + __field(bool, connectors_changed) + __field(bool, zpos_changed) + __field(bool, color_mgmt_changed) + __field(bool, no_vblank) + __field(bool, async_flip) + __field(bool, vrr_enabled) + __field(bool, self_refresh_active) + __field(u32, plane_mask) + __field(u32, connector_mask) + __field(u32, encoder_mask) + ), + + TP_fast_assign( + __entry->state = state->state; + __entry->crtc_state = state; + __entry->crtc_id = state->crtc->base.id; + __entry->commit = state->commit; + __entry->enable = state->enable; + __entry->active = state->active; + __entry->planes_changed = state->planes_changed; + __entry->mode_changed = state->mode_changed; + __entry->active_changed = state->active_changed; + __entry->connectors_changed = state->connectors_changed; + __entry->zpos_changed = state->zpos_changed; + __entry->color_mgmt_changed = state->color_mgmt_changed; + __entry->no_vblank = state->no_vblank; + __entry->async_flip = state->async_flip; + __entry->vrr_enabled = state->vrr_enabled; + __entry->self_refresh_active = state->self_refresh_active; + __entry->plane_mask = state->plane_mask; + __entry->connector_mask = state->connector_mask; + __entry->encoder_mask = state->encoder_mask; + ), + + TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed(" + "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) " + "state(enable=%d active=%d async_flip=%d vrr_enabled=%d " + "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x " + "enc=%x)", + __entry->crtc_id, __entry->crtc_state, __entry->state, + __entry->commit, __entry->planes_changed, + __entry->mode_changed, __entry->active_changed, + __entry->connectors_changed, __entry->zpos_changed, + __entry->color_mgmt_changed, __entry->enable, __entry->active, + __entry->async_flip, __entry->vrr_enabled, + __entry->self_refresh_active, __entry->no_vblank, + __entry->plane_mask, __entry->connector_mask, + __entry->encoder_mask) +); + +DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template, + TP_PROTO(const struct drm_plane_state *state), + TP_ARGS(state), + TP_STRUCT__entry( + __field(uint32_t, plane_id) + __field(enum drm_plane_type, plane_type) + __field(const struct drm_plane_state *, plane_state) + __field(const struct drm_atomic_state *, state) + __field(uint32_t, crtc_id) + __field(uint32_t, fb_id) + __field(uint32_t, fb_format) + __field(uint8_t, fb_planes) + __field(uint64_t, fb_modifier) + __field(const struct dma_fence *, fence) + __field(int32_t, crtc_x) + __field(int32_t, crtc_y) + __field(uint32_t, crtc_w) + __field(uint32_t, crtc_h) + __field(uint32_t, src_x) + __field(uint32_t, src_y) + __field(uint32_t, src_w) + __field(uint32_t, src_h) + __field(u32, alpha) + __field(uint32_t, pixel_blend_mode) + __field(unsigned int, rotation) + __field(unsigned int, zpos) + __field(unsigned int, normalized_zpos) + __field(enum drm_color_encoding, color_encoding) + __field(enum drm_color_range, color_range) + __field(bool, visible) + ), + + TP_fast_assign( + __entry->plane_id = state->plane->base.id; + __entry->plane_type = state->plane->type; + __entry->plane_state = state; + __entry->state = state->state; + __entry->crtc_id = state->crtc ? state->crtc->base.id : 0; + __entry->fb_id = state->fb ? state->fb->base.id : 0; + __entry->fb_format = state->fb ? state->fb->format->format : 0; + __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0; + __entry->fb_modifier = state->fb ? state->fb->modifier : 0; + __entry->fence = state->fence; + __entry->crtc_x = state->crtc_x; + __entry->crtc_y = state->crtc_y; + __entry->crtc_w = state->crtc_w; + __entry->crtc_h = state->crtc_h; + __entry->src_x = state->src_x >> 16; + __entry->src_y = state->src_y >> 16; + __entry->src_w = state->src_w >> 16; + __entry->src_h = state->src_h >> 16; + __entry->alpha = state->alpha; + __entry->pixel_blend_mode = state->pixel_blend_mode; + __entry->rotation = state->rotation; + __entry->zpos = state->zpos; + __entry->normalized_zpos = state->normalized_zpos; + __entry->color_encoding = state->color_encoding; + __entry->color_range = state->color_range; + __entry->visible = state->visible; + ), + + TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p " + "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) " + "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u " + "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u " + "pixel_blend_mode=%u rotation=%u zpos=%u " + "normalized_zpos=%u color_encoding=%d color_range=%d " + "visible=%d", + __entry->plane_id, __entry->plane_type, __entry->plane_state, + __entry->state, __entry->crtc_id, __entry->fb_id, + (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N', + ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O', + ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N', + ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E', + __entry->fb_planes, + __entry->fb_modifier, __entry->fence, __entry->crtc_x, + __entry->crtc_y, __entry->crtc_w, __entry->crtc_h, + __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h, + __entry->alpha, __entry->pixel_blend_mode, __entry->rotation, + __entry->zpos, __entry->normalized_zpos, + __entry->color_encoding, __entry->color_range, + __entry->visible) +); + +DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check, + TP_PROTO(const struct drm_plane_state *state), + TP_ARGS(state)); + +DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor, + TP_PROTO(const struct drm_plane_state *state), + TP_ARGS(state)); + +TRACE_EVENT(amdgpu_dm_atomic_state_template, + TP_PROTO(const struct drm_atomic_state *state), + TP_ARGS(state), + + TP_STRUCT__entry( + __field(const struct drm_atomic_state *, state) + __field(bool, allow_modeset) + __field(bool, legacy_cursor_update) + __field(bool, async_update) + __field(bool, duplicated) + __field(int, num_connector) + __field(int, num_private_objs) + ), + + TP_fast_assign( + __entry->state = state; + __entry->allow_modeset = state->allow_modeset; + __entry->legacy_cursor_update = state->legacy_cursor_update; + __entry->async_update = state->async_update; + __entry->duplicated = state->duplicated; + __entry->num_connector = state->num_connector; + __entry->num_private_objs = state->num_private_objs; + ), + + TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d " + "async_update=%d duplicated=%d num_connector=%d " + "num_private_objs=%d", + __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update, + __entry->async_update, __entry->duplicated, __entry->num_connector, + __entry->num_private_objs) +); + +DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin, + TP_PROTO(const struct drm_atomic_state *state), + TP_ARGS(state)); + +DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish, + TP_PROTO(const struct drm_atomic_state *state), + TP_ARGS(state)); + +DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin, + TP_PROTO(const struct drm_atomic_state *state), + TP_ARGS(state)); + +TRACE_EVENT(amdgpu_dm_atomic_check_finish, + TP_PROTO(const struct drm_atomic_state *state, int res), + TP_ARGS(state, res), + + TP_STRUCT__entry( + __field(const struct drm_atomic_state *, state) + __field(int, res) + __field(bool, async_update) + __field(bool, allow_modeset) + ), + + TP_fast_assign( + __entry->state = state; + __entry->res = res; + __entry->async_update = state->async_update; + __entry->allow_modeset = state->allow_modeset; + ), + + TP_printk("state=%p res=%d async_update=%d allow_modeset=%d", + __entry->state, __entry->res, + __entry->async_update, __entry->allow_modeset) +); + #endif /* _AMDGPU_DM_TRACE_H_ */ #undef TRACE_INCLUDE_PATH From patchwork Wed Sep 9 22:53:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Siqueira Jordao X-Patchwork-Id: 11766323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8050C59D for ; Wed, 9 Sep 2020 22:54:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4AD3421D90 for ; Wed, 9 Sep 2020 22:54:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="d14jEUS7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4AD3421D90 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8011A6F577; Wed, 9 Sep 2020 22:54:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-eopbgr750054.outbound.protection.outlook.com [40.107.75.54]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5081D6F56A; Wed, 9 Sep 2020 22:54:38 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Um93tfzKjex0nn05zKtdMMBldQKaN/Gt4JmvLuF2/7eoeTI5ITD7rC8vaRTezstXoBtW27jFontLOapnHfIl01BQ77hopZFPUnyFZeZb+twfWEGZWa6uON9DNKofyPQKoMPVsZyXTuQ0V+h5mtbepIW5V4EA9oFipIbnAG552qmr6q2m+yc60rxap4trRkqHRFUDS7vD2pDDm8wyCuTmANsyqBPTON3AFHTgpwnffgxPnIpUMmH+08UDLCPWfUVs6wYsrTLxzDyiO3c52/5VSky18OzNMgOH4C11lz3Tg4aSzuTvSCpD/0y1l44a1GusOn7PmB3+HdAkq8J018UF3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9dODFAEWpJwE7o6RftnyaGtifeCeyXmRhnXRtvEwanU=; b=Ql4QSDGJvlIswgedB7fVE7fW3gGPv0oVtkUWYgPiH3L4MauMBGPKQd1NcANOYei03E5k8QAQwYEkffW0AxRgtH10/DYOlUmrzpaWp7CKZnSJLDbiJMZzkZgNFJm90SmNtHrmfirzxHwuWtxSUIMgnC9fcaZIpiD1cO3Ijr2pqeLlCoZzfAWOqdwq/dpxbFj5AZ8nnQbkfNR98zLyZcVyR3HGBohdWDdylRepm2ZkbBu07lttEV6/obwTHWmTuWAKiMKsOXtjWTKWU4vXZWJHcxrXrCPvO4Jb8+ufGgJMxaT5Fq30K5Tfr4WAtrPHQ4YOS+Mt5BeCZT/VD7HuD5fw8A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9dODFAEWpJwE7o6RftnyaGtifeCeyXmRhnXRtvEwanU=; b=d14jEUS7naU7bReArMR7Zg6W13MsTh4hfmVuqcuKtN3ujUTZjNCvdZO1e3gIvadsFnyUgyG4d0Raz/GV8GhmSQ1b/C9bwdbnG+VTgxrYIn/6etVFhMAY0kuq7bwPnFKaeSBoMDc0Jn+HgWJaCHa6KM5tLPybp7Up0XjAnfsdv6k= Authentication-Results: lists.freedesktop.org; dkim=none (message not signed) header.d=none; lists.freedesktop.org; dmarc=none action=none header.from=amd.com; Received: from DM6PR12MB4124.namprd12.prod.outlook.com (2603:10b6:5:221::20) by DM6PR12MB2986.namprd12.prod.outlook.com (2603:10b6:5:39::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.18; Wed, 9 Sep 2020 22:54:37 +0000 Received: from DM6PR12MB4124.namprd12.prod.outlook.com ([fe80::25a1:ace4:4ca8:167e]) by DM6PR12MB4124.namprd12.prod.outlook.com ([fe80::25a1:ace4:4ca8:167e%8]) with mapi id 15.20.3370.016; Wed, 9 Sep 2020 22:54:36 +0000 From: Rodrigo Siqueira To: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] drm/amd/display: Add pipe_state tracepoint Date: Wed, 9 Sep 2020 18:53:52 -0400 Message-Id: <20200909225352.4072030-4-Rodrigo.Siqueira@amd.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909225352.4072030-1-Rodrigo.Siqueira@amd.com> References: <20200909225352.4072030-1-Rodrigo.Siqueira@amd.com> X-ClientProxiedBy: YT1PR01CA0143.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:2f::22) To DM6PR12MB4124.namprd12.prod.outlook.com (2603:10b6:5:221::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from atma2.hitronhub.home (2607:fea8:56e0:6d60::10ec) by YT1PR01CA0143.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:2f::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Wed, 9 Sep 2020 22:54:36 +0000 X-Mailer: git-send-email 2.28.0 X-Originating-IP: [2607:fea8:56e0:6d60::10ec] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 149ec436-921e-414a-1502-08d85513538f X-MS-TrafficTypeDiagnostic: DM6PR12MB2986: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:586; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NheUKLb5WuPWuhCeBeSmhVUB3x/y1Zb90Vm8es5GGRFqBPKQg2u+10QDLY64tKSoYB/omzQiFzp1JAh9Uxao8TjsAL1eJRvyGGvVT+ADKC0NcmeuUcIl7JmFoGbzZtzwUNXhkOcijcl0Eqk69vw+5h4NikhFRYVtnYvObrIsummaUi/ttQwvDCA+Dsd0IGr3Sj1OkialNM62HUwsrVEg9qpzN/fvAYSk9otWxsetGRWVMPFrsS66c0gYFKcoTmqLgYoI2qQhR7joQ6m3nFuE4VNte8sw/Akg8a0IoL3NR8HM/OhV8VVaQ8RVMXm02aYI9pMx2pJh1q5iKRjAluMjpA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR12MB4124.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(396003)(136003)(376002)(346002)(39860400002)(2906002)(8936002)(6486002)(6512007)(5660300002)(16526019)(186003)(478600001)(83380400001)(4326008)(8676002)(52116002)(316002)(1076003)(66476007)(6506007)(6666004)(86362001)(2616005)(66556008)(54906003)(36756003)(66946007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: WZyn81Xpr9Dg4uTqmIw54IeeQJa1KoSaxifg/4sdIOiQllf69Mfv5N5qfaHYIvAq+smjwAUrTGpZsy3APPFBoyh7vcZJI8Pgwvtemugc8ne83D5WYHD1Ja4EAGL20nKiGaOIxpe55pJTm9nhLonKP2oaH41qHYsrDhtXSrS9oBnCJbkNbsxXnXfUsMBu0kfrLFpN7hKQ+4P7i0LF8ZUHPcQbyDQHlP0CLYgLwMg/DRnWyCo6NlejfUyyuXjN0hdRKRMaIaHwEC59Cck+kS1/ggs6o8CgSjrT14bF6ov3mJpSnfd0xCIIrwAD9EOJBwGFHQg7Po8ai4xAyT08qwTRfVGhjAR68raFKW348mmArWSjsHwe9Zj2ZVGVH7fAy3BvzUMI4FC2V5MGKcM1tm70oW2r0QnxpXhgI2zqRqKdEoVeoIjCjP8BRatRJrA4gf81Gx8ig1u0RBuVbycXVPHLkfhr2qBDScdSiujTy0587zomGQ6YM9HbbqEmQdD+DhQoZSIKqYlgRjoBozPHQA7CM12N12RJusJ/fovIaC8TpZ3X1vpE2p2CdZE1eam0e/uFOpkroowjOws0ot+LUHI/DmVatN9if6vDwMY0pENbQKXE5sQr01F+gKx4QjD6LJ4R1LRrLwVr2l5tl+PWTDdRxgYoIvUIlyNpE0L1A2yyvIs= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 149ec436-921e-414a-1502-08d85513538f X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB4124.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2020 22:54:36.9243 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kSKNBQgFs3EpKdbyLtI3o9h28guAqLgnKmSKJDDF0lDFWbr6mYDqy/agyEAjMV9D7sODsCrpnhkgAzSaMABNUw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2986 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , Nicholas Kazlauskas , David Airlie , hersenxs.wu@amd.com, Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This commit introduces a trace mechanism for struct pipe_ctx by adding a middle layer struct in the amdgpu_dm_trace.h for capturing the most important data from struct pipe_ctx and showing its data via tracepoint. This tracepoint was added to dc.c and dcn10_hw_sequencer, however, it can be added to other DCN architecture. Co-developed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Kazlauskas Signed-off-by: Rodrigo Siqueira --- .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 172 ++++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 +- 3 files changed, 195 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index 5fb4c4a5c349..53f62506e17c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -376,6 +376,178 @@ TRACE_EVENT(amdgpu_dm_atomic_check_finish, __entry->async_update, __entry->allow_modeset) ); +#ifndef _AMDGPU_DM_TRACE_STRUCTS_DEFINED_ +#define _AMDGPU_DM_TRACE_STRUCTS_DEFINED_ + +struct amdgpu_dm_trace_pipe_state { + int pipe_idx; + const void *stream; + int stream_w; + int stream_h; + int dst_x; + int dst_y; + int dst_w; + int dst_h; + int src_x; + int src_y; + int src_w; + int src_h; + int clip_x; + int clip_y; + int clip_w; + int clip_h; + int recout_x; + int recout_y; + int recout_w; + int recout_h; + int viewport_x; + int viewport_y; + int viewport_w; + int viewport_h; + int flip_immediate; + int surface_pitch; + int format; + int swizzle; + unsigned int update_flags; +}; + +#define fill_out_trace_pipe_state(trace_pipe_state, pipe_ctx) \ + do { \ + trace_pipe_state.pipe_idx = (pipe_ctx)->pipe_idx; \ + trace_pipe_state.stream = (pipe_ctx)->stream; \ + trace_pipe_state.stream_w = (pipe_ctx)->stream->timing.h_addressable; \ + trace_pipe_state.stream_h = (pipe_ctx)->stream->timing.v_addressable; \ + trace_pipe_state.dst_x = (pipe_ctx)->plane_state->dst_rect.x; \ + trace_pipe_state.dst_y = (pipe_ctx)->plane_state->dst_rect.y; \ + trace_pipe_state.dst_w = (pipe_ctx)->plane_state->dst_rect.width; \ + trace_pipe_state.dst_h = (pipe_ctx)->plane_state->dst_rect.height; \ + trace_pipe_state.src_x = (pipe_ctx)->plane_state->src_rect.x; \ + trace_pipe_state.src_y = (pipe_ctx)->plane_state->src_rect.y; \ + trace_pipe_state.src_w = (pipe_ctx)->plane_state->src_rect.width; \ + trace_pipe_state.src_h = (pipe_ctx)->plane_state->src_rect.height; \ + trace_pipe_state.clip_x = (pipe_ctx)->plane_state->clip_rect.x; \ + trace_pipe_state.clip_y = (pipe_ctx)->plane_state->clip_rect.y; \ + trace_pipe_state.clip_w = (pipe_ctx)->plane_state->clip_rect.width; \ + trace_pipe_state.clip_h = (pipe_ctx)->plane_state->clip_rect.height; \ + trace_pipe_state.recout_x = (pipe_ctx)->plane_res.scl_data.recout.x; \ + trace_pipe_state.recout_y = (pipe_ctx)->plane_res.scl_data.recout.y; \ + trace_pipe_state.recout_w = (pipe_ctx)->plane_res.scl_data.recout.width; \ + trace_pipe_state.recout_h = (pipe_ctx)->plane_res.scl_data.recout.height; \ + trace_pipe_state.viewport_x = (pipe_ctx)->plane_res.scl_data.viewport.x; \ + trace_pipe_state.viewport_y = (pipe_ctx)->plane_res.scl_data.viewport.y; \ + trace_pipe_state.viewport_w = (pipe_ctx)->plane_res.scl_data.viewport.width; \ + trace_pipe_state.viewport_h = (pipe_ctx)->plane_res.scl_data.viewport.height; \ + trace_pipe_state.flip_immediate = (pipe_ctx)->plane_state->flip_immediate; \ + trace_pipe_state.surface_pitch = (pipe_ctx)->plane_state->plane_size.surface_pitch; \ + trace_pipe_state.format = (pipe_ctx)->plane_state->format; \ + trace_pipe_state.swizzle = (pipe_ctx)->plane_state->tiling_info.gfx9.swizzle; \ + trace_pipe_state.update_flags = (pipe_ctx)->update_flags.raw; \ + } while (0) + +#endif /* _AMDGPU_DM_TRACE_STRUCTS_DEFINED_ */ + +TRACE_EVENT(amdgpu_dm_dc_pipe_state, + TP_PROTO(const struct amdgpu_dm_trace_pipe_state *pipe_state), + TP_ARGS(pipe_state), + TP_STRUCT__entry( + __field(int, pipe_idx) + __field(const void *, stream) + __field(int, stream_w) + __field(int, stream_h) + __field(int, dst_x) + __field(int, dst_y) + __field(int, dst_w) + __field(int, dst_h) + __field(int, src_x) + __field(int, src_y) + __field(int, src_w) + __field(int, src_h) + __field(int, clip_x) + __field(int, clip_y) + __field(int, clip_w) + __field(int, clip_h) + __field(int, recout_x) + __field(int, recout_y) + __field(int, recout_w) + __field(int, recout_h) + __field(int, viewport_x) + __field(int, viewport_y) + __field(int, viewport_w) + __field(int, viewport_h) + __field(int, flip_immediate) + __field(int, surface_pitch) + __field(int, format) + __field(int, swizzle) + __field(unsigned int, update_flags) + ), + + TP_fast_assign( + __entry->pipe_idx = pipe_state->pipe_idx; + __entry->stream = pipe_state->stream; + __entry->stream_w = pipe_state->stream_w; + __entry->stream_h = pipe_state->stream_h; + __entry->dst_x = pipe_state->dst_x; + __entry->dst_y = pipe_state->dst_y; + __entry->dst_w = pipe_state->dst_w; + __entry->dst_h = pipe_state->dst_h; + __entry->src_x = pipe_state->src_x; + __entry->src_y = pipe_state->src_y; + __entry->src_w = pipe_state->src_w; + __entry->src_h = pipe_state->src_h; + __entry->clip_x = pipe_state->clip_x; + __entry->clip_y = pipe_state->clip_y; + __entry->clip_w = pipe_state->clip_w; + __entry->clip_h = pipe_state->clip_h; + __entry->recout_x = pipe_state->recout_x; + __entry->recout_y = pipe_state->recout_y; + __entry->recout_w = pipe_state->recout_w; + __entry->recout_h = pipe_state->recout_h; + __entry->viewport_x = pipe_state->viewport_x; + __entry->viewport_y = pipe_state->viewport_y; + __entry->viewport_w = pipe_state->viewport_w; + __entry->viewport_h = pipe_state->viewport_h; + __entry->flip_immediate = pipe_state->flip_immediate; + __entry->surface_pitch = pipe_state->surface_pitch; + __entry->format = pipe_state->format; + __entry->swizzle = pipe_state->swizzle; + __entry->update_flags = pipe_state->update_flags; + ), + TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) " + "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) " + "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d " + "format=%d swizzle=%d update_flags=%x", + __entry->pipe_idx, + __entry->stream, + __entry->stream_w, + __entry->stream_h, + __entry->dst_x, + __entry->dst_y, + __entry->dst_w, + __entry->dst_h, + __entry->src_x, + __entry->src_y, + __entry->src_w, + __entry->src_h, + __entry->clip_x, + __entry->clip_y, + __entry->clip_w, + __entry->clip_h, + __entry->recout_x, + __entry->recout_y, + __entry->recout_w, + __entry->recout_h, + __entry->viewport_x, + __entry->viewport_y, + __entry->viewport_w, + __entry->viewport_h, + __entry->flip_immediate, + __entry->surface_pitch, + __entry->format, + __entry->swizzle, + __entry->update_flags + ) +); + #endif /* _AMDGPU_DM_TRACE_H_ */ #undef TRACE_INCLUDE_PATH diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index dc463d99ef50..0c9f177e5827 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2644,6 +2644,17 @@ void dc_commit_updates_for_stream(struct dc *dc, } } + for (i = 0; i < MAX_PIPES; ++i) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->plane_state) { + struct amdgpu_dm_trace_pipe_state pipe_state_trace; + + fill_out_trace_pipe_state(pipe_state_trace, pipe_ctx); + trace_amdgpu_dm_dc_pipe_state(&pipe_state_trace); + } + } + commit_planes_for_stream( dc, srf_updates, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 8ca94f506195..464d0ad093b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1020,15 +1020,22 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc) } - void dcn10_verify_allow_pstate_change_high(struct dc *dc) { - static bool should_log_hw_state; /* prevent hw state log by default */ - if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { - if (should_log_hw_state) { - dcn10_log_hw_state(dc, NULL); + int i; + + for (i = 0; i < MAX_PIPES; ++i) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->plane_state) { + struct amdgpu_dm_trace_pipe_state pipe_state_trace; + + fill_out_trace_pipe_state(pipe_state_trace, pipe_ctx); + trace_amdgpu_dm_dc_pipe_state(&pipe_state_trace); + } } + BREAK_TO_DEBUGGER(); if (dcn10_hw_wa_force_recovery(dc)) { /*check again*/