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Signed-off-by: Peng Fan --- arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index b7ea37ad4e55..b02dc4c97fb8 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -286,6 +286,11 @@ pcc2: clock-controller@403f0000 { assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; + pmc1: pmc1@40400000 { + compatible = "fsl,imx7ulp-pmc1"; + reg = <0x40400000 0x1000>; + }; + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; @@ -447,6 +452,11 @@ m4aips1: bus@41080000 { reg = <0x41080000 0x80000>; ranges; + pmc0: pmc0@410a1000 { + compatible = "fsl,imx7ulp-pmc0"; + reg = <0x410a1000 0x1000>; + }; + sim: sim@410a3000 { compatible = "fsl,imx7ulp-sim", "syscon"; reg = <0x410a3000 0x1000>; From patchwork Wed Sep 16 02:48:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 11778755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40E1D746 for ; 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In LDO-enabled mode, HSRUN mode is not allowed, so add a check before configure PMPROT. Signed-off-by: Peng Fan --- arch/arm/mach-imx/pm-imx7ulp.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c index 2e756d8191fa..393faf1e8382 100644 --- a/arch/arm/mach-imx/pm-imx7ulp.c +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -11,6 +11,10 @@ #include "common.h" +#define PMC0_CTRL 0x28 +#define BM_CTRL_LDOEN BIT(31) + +#define SMC_PMPROT 0x8 #define SMC_PMCTRL 0x10 #define BP_PMCTRL_PSTOPO 16 #define PSTOPO_PSTOP3 0x3 @@ -25,7 +29,10 @@ #define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM) #define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM) +#define BM_PMPROT_AHSRUN BIT(7) + static void __iomem *smc1_base; +static void __iomem *pmc0_base; int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) { @@ -65,5 +72,13 @@ void __init imx7ulp_pm_init(void) of_node_put(np); WARN_ON(!smc1_base); + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0"); + pmc0_base = of_iomap(np, 0); + WARN_ON(!pmc0_base); + of_node_put(np); + + if (!(readl_relaxed(pmc0_base + PMC0_CTRL) & BM_CTRL_LDOEN)) + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT); + imx7ulp_set_lpm(ULP_PM_RUN); } From patchwork Wed Sep 16 02:48:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 11778757 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B944714F6 for ; Wed, 16 Sep 2020 02:56:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 872F620708 for ; Wed, 16 Sep 2020 02:56:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="KKj8cqq2"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="aXvx/mVN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 872F620708 Authentication-Results: mail.kernel.org; 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So add imx7ulp_get_mode to get thr cpu run mode, and use WAIT mode instead, when cpu in HSRUN mode. Signed-off-by: Peng Fan Reviewed-by: Dong Aisheng --- arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpuidle-imx7ulp.c | 14 +++++++++++--- arch/arm/mach-imx/pm-imx7ulp.c | 10 ++++++++++ 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 72c3fcc32910..707ac650f1c2 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -103,6 +103,7 @@ void imx6_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); int imx_mmdc_get_ddr_type(void); int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode); +u32 imx7ulp_get_mode(void); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c b/arch/arm/mach-imx/cpuidle-imx7ulp.c index ca86c967d19e..e7009d10b331 100644 --- a/arch/arm/mach-imx/cpuidle-imx7ulp.c +++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c @@ -15,10 +15,18 @@ static int imx7ulp_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - if (index == 1) + u32 mode; + + if (index == 1) { imx7ulp_set_lpm(ULP_PM_WAIT); - else - imx7ulp_set_lpm(ULP_PM_STOP); + } else { + mode = imx7ulp_get_mode(); + + if (mode == 3) + imx7ulp_set_lpm(ULP_PM_WAIT); + else + imx7ulp_set_lpm(ULP_PM_STOP); + } cpu_do_idle(); diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c index 393faf1e8382..1410ccfc71bd 100644 --- a/arch/arm/mach-imx/pm-imx7ulp.c +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -63,6 +63,16 @@ int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) return 0; } +u32 imx7ulp_get_mode(void) +{ + u32 mode; + + mode = readl_relaxed(smc1_base + SMC_PMCTRL) & BM_PMCTRL_RUNM; + mode >>= BP_PMCTRL_RUNM; + + return mode; +} + void __init imx7ulp_pm_init(void) { struct device_node *np;