From patchwork Wed Sep 16 20:44:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11780885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ECC0392C for ; Wed, 16 Sep 2020 20:44:24 +0000 (UTC) Received: by mail.kernel.org (Postfix) id E3C5C221EE; Wed, 16 Sep 2020 20:44:24 +0000 (UTC) Delivered-To: soc@kernel.org Received: from localhost.localdomain (cpe-70-114-140-30.austin.res.rr.com [70.114.140.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1AFD721D24; Wed, 16 Sep 2020 20:44:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600289064; bh=RoIfzpWJ5l8bw0efDP2SNEA4UD+gWu91IStSkmG4Xy4=; h=From:List-Id:To:Cc:Subject:Date:From; b=O6aBRG7YhOzKpU6KFznrvswUVgRy5aQ40CSa//dNTxaJ2XfZN+wRf5wm5wK4g2V0b AGEh73X84ABF98QL8934tWZ22eQqM7dvoIy+RFP8hWdO4BnnBM7ZSuBgsDU0dcWllX 2m1eWhtdxty4MI1ccauF3XAGjlOKqrghfJLw4FSM= From: Dinh Nguyen List-Id: To: arm@kernel.org, soc@kernel.org Cc: dinguyen@kernel.org Subject: [GIT PULL] SoCFPGA DTS updates for v5.10 Date: Wed, 16 Sep 2020 15:44:22 -0500 Message-Id: <20200916204422.30897-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.17.1 Hi Arnd, Kevin, and Olof: Please pull in these SoCFPGA DTS updates for v5.10. Thanks, Dinh The following changes since commit 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5: Linux 5.9-rc1 (2020-08-16 13:04:57 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_dts_update_for_v5.10 for you to fetch changes up to 6e043c658e7917200e6251d1fa67b64c332f0531: arm64: dts: stratix10/agilex: add the ptp_ref clock (2020-08-31 12:56:55 -0500) ---------------------------------------------------------------- SoCFPGA DTS updates for v5.10 - Increase shared-dma-pool size to 32MB - Add ptp_ref clock properties to the ethernet nodes on Stratix10 and Agilex ---------------------------------------------------------------- Dinh Nguyen (1): arm64: dts: stratix10/agilex: add the ptp_ref clock Richard Gong (1): arm64: dts: agilex: increase shared memory size to 32Mb arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++------ arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 14 +++++++------- 2 files changed, 13 insertions(+), 13 deletions(-)