From patchwork Fri Sep 18 00:28:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 11783759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCA236CB for ; Fri, 18 Sep 2020 00:28:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 968F1207FB for ; Fri, 18 Sep 2020 00:28:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=poorly.run header.i=@poorly.run header.b="Te490BDm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 968F1207FB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=poorly.run Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA18F6E429; Fri, 18 Sep 2020 00:28:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qk1-x741.google.com (mail-qk1-x741.google.com [IPv6:2607:f8b0:4864:20::741]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0ADC36E429 for ; Fri, 18 Sep 2020 00:28:51 +0000 (UTC) Received: by mail-qk1-x741.google.com with SMTP id w12so4332768qki.6 for ; Thu, 17 Sep 2020 17:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=poorly.run; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/gmncA8kxGKcPa7SK+dFjAMfzQZTgarB/yb9R4FsDX0=; b=Te490BDmgnfcl57DFNtHMwkerMN0P3TGX+cfZoHfwaStAe1+9o+kADXbkMJjzF4l4M eh4UGNEqsoH/xjcfY+I9UZWgDZTJUYZjJInheqlAK2x8ip5Ty9Qsb/Qz3Uuk+THBSX0f ep4PUY+uka7iZEC7bxuE33TXB4MuKVNe1B1chXayyHTxhm+eUqiDyCvwbC/HRpwCWJ3T h5Jr+ZmJ3MDLcBVl/G34FfU4E/lZEao9NhTnp+htqcIgdLzrdnJl/4ZTCIiHdp154cfn 8fOjdkSDN2nPtC9kA/zhXk9t3gUJXxRxTK9bypLi4NYf7GYmZtMrLwTzWGzuwmmLYRsE BYNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/gmncA8kxGKcPa7SK+dFjAMfzQZTgarB/yb9R4FsDX0=; b=i7Chp6306xiU9FUdlmYOnb1ct4rYM2CnGxheuhdECHPsnGxpon6U90RVjSkL0wqbZw 43fL22Z/AaAcdUj/p/t5sM9I0VWDvyJNQK/IYtQfAiAhx6pfwM/EVRxR8Bo/CvsH9L7Q OAd4PUc5U3Aqqk4kLSu/PKQD/+h2DXMCAmdzk1lU/DZ4WHPwMSCx2hquMo6fzLAmxMdy KeEUSNwAzyFT15GYgjoLUJZEMinEPUCa7XzDQfw/9KDzKzLK2o0x2Nped/VwOcyAqIoh gvp6n9hmtXrKWOZjL3FCuIppdJCL9NGVA3BTZ2Ad4eIfC1z/s8s1e6s4dHifoNhk54/f LuMw== X-Gm-Message-State: AOAM532Wbk7PsFwi52/Lr/dSLuBNOfrdnu4N+MI+gIGpPEvJuhB11SK0 EQhWaSpmSU/A/TMUaGnaiJevIg== X-Google-Smtp-Source: ABdhPJyOi699V89FVWQZnO2X7JruK4pyUVX+UfMsR4kcpC1beac5Jy/L3/asVJVZcYaWeV5dDPR3ng== X-Received: by 2002:a37:9d88:: with SMTP id g130mr30762675qke.185.1600388931091; Thu, 17 Sep 2020 17:28:51 -0700 (PDT) Received: from localhost ([166.137.97.114]) by smtp.gmail.com with ESMTPSA id r78sm979842qka.95.2020.09.17.17.28.50 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Sep 2020 17:28:50 -0700 (PDT) From: Sean Paul To: dri-devel@lists.freedesktop.org Date: Thu, 17 Sep 2020 20:28:42 -0400 Message-Id: <20200918002845.32766-1-sean@poorly.run> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Tweak initial dpcd backlight.enabled value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Chowski , Jani Nikula , intel-gfx@lists.freedesktop.org, David Airlie , Sean Paul Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Sean Paul In commit 79946723092b ("drm/i915: Assume 100% brightness when not in DPCD control mode"), we fixed the brightness level when DPCD control was not active to max brightness. This is as good as we can guess since most backlights go on full when uncontrolled. However in doing so we changed the semantics of the initial 'backlight.enabled' value. At least on Pixelbooks, they were relying on the brightness level in DP_EDP_BACKLIGHT_BRIGHTNESS_MSB to be 0 on boot such that enabled would be false. This causes the device to be enabled when the brightness is set. Without this, brightness control doesn't work. So by changing brightness to max, we also flipped enabled to be true on boot. To fix this, make enabled a function of brightness and backlight control mechanism. Fixes: 79946723092b ("drm/i915: Assume 100% brightness when not in DPCD control mode") Cc: Lyude Paul Cc: Jani Nikula Cc: Juha-Pekka Heikkila Cc: "Ville Syrjälä" Cc: Rodrigo Vivi Cc: Kevin Chowski > Signed-off-by: Sean Paul Reviewed-by: Lyude Paul --- .../drm/i915/display/intel_dp_aux_backlight.c | 31 ++++++++++++------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index acbd7eb66cbe..036f504ac7db 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -52,17 +52,11 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable) } } -/* - * Read the current backlight value from DPCD register(s) based - * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported - */ -static u32 intel_dp_aux_get_backlight(struct intel_connector *connector) +static bool intel_dp_aux_backlight_dpcd_mode(struct intel_connector *connector) { struct intel_dp *intel_dp = intel_attached_dp(connector); struct drm_i915_private *i915 = dp_to_i915(intel_dp); - u8 read_val[2] = { 0x0 }; u8 mode_reg; - u16 level = 0; if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, @@ -70,15 +64,29 @@ static u32 intel_dp_aux_get_backlight(struct intel_connector *connector) drm_dbg_kms(&i915->drm, "Failed to read the DPCD register 0x%x\n", DP_EDP_BACKLIGHT_MODE_SET_REGISTER); - return 0; + return false; } + return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) == + DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; +} + +/* + * Read the current backlight value from DPCD register(s) based + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported + */ +static u32 intel_dp_aux_get_backlight(struct intel_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(connector); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u8 read_val[2] = { 0x0 }; + u16 level = 0; + /* * If we're not in DPCD control mode yet, the programmed brightness * value is meaningless and we should assume max brightness */ - if ((mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != - DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) + if (!intel_dp_aux_backlight_dpcd_mode(connector)) return connector->panel.backlight.max; if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, @@ -319,7 +327,8 @@ static int intel_dp_aux_setup_backlight(struct intel_connector *connector, panel->backlight.min = 0; panel->backlight.level = intel_dp_aux_get_backlight(connector); - panel->backlight.enabled = panel->backlight.level != 0; + panel->backlight.enabled = intel_dp_aux_backlight_dpcd_mode(connector) && + panel->backlight.level != 0; return 0; }