From patchwork Wed Sep 23 23:15:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795807 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 219B76CA for ; Thu, 24 Sep 2020 00:14:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 05D5321734 for ; Thu, 24 Sep 2020 00:14:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XhX2ZhKO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726638AbgIXAOv (ORCPT ); Wed, 23 Sep 2020 20:14:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAOv (ORCPT ); Wed, 23 Sep 2020 20:14:51 -0400 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B615C0613CE for ; Wed, 23 Sep 2020 17:14:51 -0700 (PDT) Received: by mail-ed1-x544.google.com with SMTP id k14so1605294edo.1 for ; Wed, 23 Sep 2020 17:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7kHwfcAazeBg+h2uEVovJwlfIIrEWzUTpgb6sW8h8RI=; b=XhX2ZhKOexKs7QyhyEZso/Cywth1bItGzMPp0erbG0jVgRgR/Z7byFWwRy5QIusmUt w4IAkdAqOJgAvap6BA3IxCpeBhBaQK75Thxl7jTBwq75dsyEoWh13Hnn1T/QzMFPexDA nW2P8Vy3svJiYA5FYG26tk4SImu7Ev3i+pT+pDaBHYlIpgrm9xeSY/FtzIPu4lcdAyUI EkeNyS3qTmfT62uMLluF9HK6fiOAKOUDnD1Pzuxvw1307C70cAq41oD61VBcJv3HtfeR KXyfDi0OEV4Qlclz5VmQjiOHbmAF1jS56EslnJSYpUNETzuXq3QmstUc6TFT7saejmaf hZxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7kHwfcAazeBg+h2uEVovJwlfIIrEWzUTpgb6sW8h8RI=; b=AVo5d0TsC1yysfxWYEEMIsnbUDRSdNmxK8gPwldyf/rCok/6JMSl+x06sanhUjhqFU M5fOTeEIvbkKHjYzAlrggqj3HqYiH3E333dp7JvFiSLlMJ0VZXYYP1V10hPeUuu8lnTZ VBOAxtrRJey2+wuI+w42o++CWz3gRwyCUZDxXjhgrkEALlF//MEVvBPcJVN7hQlBAUrI XFyinApQSqn2cyO3vR4sRYVMJ69h4fnVXrwLfdIZC6m15mDdk0xZuHLO7iPkIVJSuS4P oP/pGrq4SWrHgKpl73XRApNST5YMsjR8uMpnxgjTL+tugOwpjcnzjJLpgdxzRJS4N2kj xp5w== X-Gm-Message-State: AOAM533KQoD8BYYlZbH7ueH5RS/dhjekUw30ei6or42TTBIhtENXaFkM nmX/ib8iFeIM3XcFBmrxuVxCWVOmt4KnbQ== X-Google-Smtp-Source: ABdhPJyFgW+fCsejGi9f0ZVVLvoMyaE4iTmgFDgjiXEXexRQVuKO8wLgEbCqRtjKwV1uyLzkeMoUEQ== X-Received: by 2002:a05:6402:cb4:: with SMTP id cn20mr1884326edb.369.1600906489644; Wed, 23 Sep 2020 17:14:49 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:49 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 1/8] PCI/ASPM: Cache device's ASPM link capability in struct pci_dev Date: Thu, 24 Sep 2020 01:15:10 +0200 Message-Id: <20200923231517.221310-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pcie_get_aspm_reg() reads LNKCAP to learn whether the device supports ASPM L0s and/or L1 and L1 substates. If we cache the entire LNKCAP word early enough, we may be able to use it in other places that read LNKCAP, e.g. pcie_get_speed_cap(), pcie_get_width_cap(), pcie_init(), etc. - Add struct pci_dev.lnkcap (u32) - Read PCI_EXP_LNKCAP in set_pcie_port_type() and save it in pci_dev.lnkcap - Use pdev->lnkcap instead of reading PCI_EXP_LNKCAP Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 7 ++----- drivers/pci/probe.c | 1 + include/linux/pci.h | 1 + 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 253c30cc1967..d7e69b3595a0 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -177,15 +177,13 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable) static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) { int capable = 1, enabled = 1; - u32 reg32; u16 reg16; struct pci_dev *child; struct pci_bus *linkbus = link->pdev->subordinate; /* All functions should have the same cap and state, take the worst */ list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); - if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { + if (!(child->lnkcap & PCI_EXP_LNKCAP_CLKPM)) { capable = 0; enabled = 0; break; @@ -397,9 +395,8 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { u16 reg16; - u32 reg32; + u32 reg32 = pdev->lnkcap; - pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 03d37128a24f..2d5898f05f89 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1486,6 +1486,7 @@ void set_pcie_port_type(struct pci_dev *pdev) pdev->pcie_flags_reg = reg16; pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &pdev->lnkcap); parent = pci_upstream_bridge(pdev); if (!parent) diff --git a/include/linux/pci.h b/include/linux/pci.h index 835530605c0d..5b305cfeb1dc 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -375,6 +375,7 @@ struct pci_dev { bit manually */ unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ + u32 lnkcap; /* Link Capabilities */ #ifdef CONFIG_PCIEASPM struct pcie_link_state *link_state; /* ASPM link state */ From patchwork Wed Sep 23 23:15:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795809 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D5C16CA for ; Thu, 24 Sep 2020 00:14:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8395F23119 for ; Thu, 24 Sep 2020 00:14:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bViPTjYG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726643AbgIXAOx (ORCPT ); Wed, 23 Sep 2020 20:14:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAOw (ORCPT ); Wed, 23 Sep 2020 20:14:52 -0400 Received: from mail-ed1-x541.google.com (mail-ed1-x541.google.com [IPv6:2a00:1450:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85799C0613CE for ; Wed, 23 Sep 2020 17:14:52 -0700 (PDT) Received: by mail-ed1-x541.google.com with SMTP id g4so1615104edk.0 for ; Wed, 23 Sep 2020 17:14:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=avYflrEIwbhH8rFwntiZPPaA0Uaq3GfuFh1DgQVMGyA=; b=bViPTjYGohP3TkXs0XHXvYKjAbzGCgNpFCb9T2+UqfqV125TP2o8NzpbFNkgJNfVzR KP26tlLOK4MqzbU40ct5Dt/hqzrIBInjpIBPWyaAtnejRuUxxXK2ZzV6kSxEZdYyjB2R dhbZsY1wz3d74AG3V9uu00C5u0ZZ1/LMZUNx7Z6ExN3PdZMqHwUra1rc7dI8L0u/MBYi 7yh/WqzFThF4ozOr4FGf4fW7niqLIwMnJGYToDJ3M55QfudFw3FC/HxKErEpOGvNzmyd hLZi9GeI7uzw2OA3UqYlcVf5gwwpCeYKjWRi6Uh6YurehBDW2x6i+hxQeuKr+tU367+9 /pUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=avYflrEIwbhH8rFwntiZPPaA0Uaq3GfuFh1DgQVMGyA=; b=MTSshsPdv7pNn6yHqLIT5uIt55k/bh2wbt5N0N6AeB7Wz/oRgkfjrzzb8FQtFfSDxF txdsFJIUbDJ7gN0c2Ulbld9t++Tk8VSCRT5vW1S4TyLRjt3Rz6M5+y60Y9OGkloUS9Ns I1yuy2yKG9gqtueJFLoM9nkHCen+7CdeTHVJea19kjuBSzWE0km87GQQeSNjRCEzzRs8 TBmcF/3ycwOzn6Birs7eXo54Ej4wZUuR01T780vnwwN2HG5Ea+MLJkaa+Y0srWMwXH76 vi0Tx9NsynQh9R31b5a7PrSbx0n5/o+E+KewXONf0B8nDTmWMYrv3nDkcJDZbfWu4SMV LdwA== X-Gm-Message-State: AOAM530OtMjopHevab9Fz0L6xMoes3vJ80HbGJnCeJdQVewxO9lIIQk8 VojJzVdpWDHqrdNkRrdJeQA= X-Google-Smtp-Source: ABdhPJyuU611U2J2wVPyfP4BwFcuCSceoZ0GRUlVHyqhYV2EmXtfaelObsGZOpZUqCsku0di9uH4wQ== X-Received: by 2002:a05:6402:10c9:: with SMTP id p9mr1983528edu.156.1600906491248; Wed, 23 Sep 2020 17:14:51 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:50 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 2/8] PCI/ASPM: Rework calc_l*_latency() to take a struct pci_dev Date: Thu, 24 Sep 2020 01:15:11 +0200 Message-Id: <20200923231517.221310-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Change the argument of calc_l0s_latency() to pci_dev *, - Compute latency_encoding_l0s encoding inside calc_l0s_latency() - Compute latency_encoding_l1 encoding inside calc_l1_latency() - Make calc_l*_latency() take only pci_dev *, - Make callers to calc_l0s_latency() and calc_l1_latency() pass in struct pci_dev - In pcie_get_aspm_reg() remove assignments to the latency encodings - Remove aspm_register_info.latency_encoding_l1 - Remove aspm_register_info.latency_encoding_l0s Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index d7e69b3595a0..5f7cf47b6a40 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -306,8 +306,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) } /* Convert L0s latency encoding to ns */ -static u32 calc_l0s_latency(u32 encoding) +static u32 calc_l0s_latency(struct pci_dev *pdev) { + u32 encoding = (pdev->lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + if (encoding == 0x7) return (5 * 1000); /* > 4us */ return (64 << encoding); @@ -322,8 +324,10 @@ static u32 calc_l0s_acceptable(u32 encoding) } /* Convert L1 latency encoding to ns */ -static u32 calc_l1_latency(u32 encoding) +static u32 calc_l1_latency(struct pci_dev *pdev) { + u32 encoding = (pdev->lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + if (encoding == 0x7) return (65 * 1000); /* > 64us */ return (1000 << encoding); @@ -381,8 +385,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) struct aspm_register_info { u32 support:2; u32 enabled:2; - u32 latency_encoding_l0s; - u32 latency_encoding_l1; /* L1 substates */ u32 l1ss_cap_ptr; @@ -398,8 +400,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, u32 reg32 = pdev->lnkcap; info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; - info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; - info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; @@ -587,16 +587,16 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (upreg.enabled & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; - link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); - link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); + link->latency_up.l0s = calc_l0s_latency(parent); + link->latency_dw.l0s = calc_l0s_latency(child); /* Setup L1 state */ if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) link->aspm_support |= ASPM_STATE_L1; if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; - link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); - link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); + link->latency_up.l1 = calc_l1_latency(parent); + link->latency_dw.l1 = calc_l1_latency(child); /* Setup L1 substate */ if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) From patchwork Wed Sep 23 23:15:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795811 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB6AF112E for ; Thu, 24 Sep 2020 00:14:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B00FC21D91 for ; Thu, 24 Sep 2020 00:14:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qwMu1d9c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726650AbgIXAOy (ORCPT ); Wed, 23 Sep 2020 20:14:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAOy (ORCPT ); Wed, 23 Sep 2020 20:14:54 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB6DCC0613CE for ; Wed, 23 Sep 2020 17:14:53 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id k14so1605374edo.1 for ; Wed, 23 Sep 2020 17:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gqOo9sRKsu8OklEdZbxfDsKXZHiV2LQufDSEO7PGLPM=; b=qwMu1d9cN2u3F4Vq1BCz/BrY+tG0KkT+iBJwkq5tkHnOjeFVSQ4YiYTHdQ295mgFBw l66p8OOPjrDA+YWosty+8eGZjlVCfAE2PiL8ZO7HoGZ5ejgQ6b6kOZAZwP7Xm1YebOy5 e8WYDVoXPweMqskM3s0XwNjL7Pq+MZyKn38iOL93Y/1knUX2AiJ8m0dM9oB4CBgSYXF5 n4L3fDCis6UGKkh6k1g59LaMSRqSftCmHlYNHVR5pzRdus5cdhs7ZIos+N+3lKhsKsaq uTr2vJd3PoShty0naEFEKV3Tj9RZR7fv5GF9ikIPcbkWUCyZr8uhNMNqQv4jLSUy0BKa LpNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gqOo9sRKsu8OklEdZbxfDsKXZHiV2LQufDSEO7PGLPM=; b=RPjCfYsxgnXSW/W1SXj/4IEQF52AfT46dL48QYoOaCEL+8Vavouvktf3CTYCDOvrYn zceoGqFAjKBdt7viogyVD8n/Wc8RY8u+KUuvfIRlIvo18mclWihqkfPDRxEZWFfb66vP pjkW/vmLTKB/VM6D0t3hwULpa2ddRghuSviHIccoV2dSnaj0nrqdk/wG0bIB2breEGcF yir9As3MzSpKNvTuNJeENR3uu/+w4myFsKiaK4XJ7njnA5tsPHCgnDw7FEPlSnjN34kq l3s6SLJd8m3pIusatxfjo8sA4bkK4Q1ItxnM7tBUifRQNFnnUi9JU438SJ3LLwkG1ed5 wAfQ== X-Gm-Message-State: AOAM532IXLIqLYz6wy/MDm3JQxhB0SJnMNjzPMMgnqEA188k7GrahWs6 jKK0q295uQu1io4CcLJDhTw= X-Google-Smtp-Source: ABdhPJzrtfxhKIlDd4w8QsFQYW1taNVNZGl6pcPKDb+S5nGtYmd3ea3tJRhOXc4SluOrIRNUC0za7w== X-Received: by 2002:aa7:db02:: with SMTP id t2mr1866598eds.95.1600906492342; Wed, 23 Sep 2020 17:14:52 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:51 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 3/8] PCI/ASPM: Compute the value of aspm_register_info.support directly Date: Thu, 24 Sep 2020 01:15:12 +0200 Message-Id: <20200923231517.221310-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Calculate aspm_register_info.support inside aspm_support() - Replace references to aspm_register_info.support with aspm_support(). - In pcie_get_aspm_reg() remove assignment to aspm_register_info.support - Remove aspm_register_info.support Signed-off-by: Saheed O. Bolarinwa Reported-by: kernel test robot --- drivers/pci/pcie/aspm.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 5f7cf47b6a40..321b328347c1 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -383,7 +383,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } struct aspm_register_info { - u32 support:2; u32 enabled:2; /* L1 substates */ @@ -396,12 +395,10 @@ struct aspm_register_info { static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { - u16 reg16; - u32 reg32 = pdev->lnkcap; + u16 ctl; - info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); - info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; + pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); + info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; /* Read L1 PM substate capabilities */ info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; @@ -540,6 +537,11 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } +static void aspm_support(struct pci_dev *pdev) +{ + return (pdev->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10; +} + static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; @@ -561,7 +563,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) * If ASPM not supported, don't mess with the clocks and link, * bail out now. */ - if (!(upreg.support & dwreg.support)) + if (!(aspm_support(parent) & aspm_support(child))) return; /* Configure common clock before checking latencies */ @@ -581,8 +583,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) * given link unless components on both sides of the link each * support L0s. */ - if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) + if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L0S) link->aspm_support |= ASPM_STATE_L0S; + if (dwreg.enabled & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (upreg.enabled & PCIE_LINK_STATE_L0S) @@ -591,8 +594,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_dw.l0s = calc_l0s_latency(child); /* Setup L1 state */ - if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) + if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L1) link->aspm_support |= ASPM_STATE_L1; + if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; link->latency_up.l1 = calc_l1_latency(parent); From patchwork Wed Sep 23 23:15:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795813 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20707112E for ; Thu, 24 Sep 2020 00:14:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0656921D91 for ; Thu, 24 Sep 2020 00:14:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sJz4BUfB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726662AbgIXAOz (ORCPT ); Wed, 23 Sep 2020 20:14:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAOz (ORCPT ); Wed, 23 Sep 2020 20:14:55 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3854C0613CE for ; Wed, 23 Sep 2020 17:14:54 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id e23so2049299eja.3 for ; Wed, 23 Sep 2020 17:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K97YsgNj5X1wCsM2C3sfK5CfB6Twz8gI9Kolu+4q0zg=; b=sJz4BUfB8kNZ+sHNb/0q3JsZHAwIKZr90x9hjHwvv0A6J5iOWuIMzNp3CKgtxx6jSG lgg3FZOVTOvxAxI+gtJavCpg1pkHWIYHv/vCNifBIrUqFREwROXYh1MYIQMJV2XIW0hP bjN/om3Awe+H+R5BKQ1SHp9g01KehqPLM0LecW7u09Ef3WwvVoxYXYC8fSuWGJglXAxF WRqgPoBhOV9yLEWE0Osz8FcwsyRjwGAMynMUxitGllml+fUiNpHC1J9ViU7UKvPEyhcu aMjepQD2wFcHqldf5rwZXHgKyufdqml2Qv3hH+hFteQvL5cPg5s0Rw6ZiRLntZCL4YEQ Nn2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K97YsgNj5X1wCsM2C3sfK5CfB6Twz8gI9Kolu+4q0zg=; b=LzxfrWsNivoDuleH9lJYJR442v58lL+Ega4aWC8wmyVuqhvfbG2HIEqlDlMYXH+pzB GY6OJ3g8ETBacs/ObkKtpZBqThxRsfmm6mNtOv6C4ODZ0IleIqYCd6qKPHWIL5JfRu7F 61PX7kvDPMuJ0QPHMLomjNu1ysN/VqSQozhknQoXHFNjdg42hRFXnPBzfHqgtTf9GtZZ 5a/r6gIcoPit0mci/IiYXuYdqvjB6e2AEnZfASt5bkypqkpa3D6urmUvpO1sKnlPY1Q8 hwvecKWtjSHX8eL3nCZKlzLG6q1vr0PbqqcVOzIODlczxDaYSQ5d3xQZ72ygxHg2LafX CfgQ== X-Gm-Message-State: AOAM532RGfANHuqK3luOzIaaPRxwXSkweipRQFMh36qbER9duxFWLu5y yrgpu3JPPDIliVyKvjSPzw8= X-Google-Smtp-Source: ABdhPJwA2hnUIb7VfQAfW7n7EKAOypS0bDTfiWSRoX/ahhS8t6zJBF6+DoBlE3n9Qbfs/yJoMsuUfg== X-Received: by 2002:a17:906:249b:: with SMTP id e27mr2041936ejb.105.1600906493608; Wed, 23 Sep 2020 17:14:53 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:53 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 4/8] PCI/ASPM: Replace aspm_register_info.l1ss_cap* with pci_dev.l1ss_cap* Date: Thu, 24 Sep 2020 01:15:13 +0200 Message-Id: <20200923231517.221310-5-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Add l1ss_cap and l1ss_cap_ptr to struct pci_dev - In pci_configure_ltr(), compute the value of pci_dev.l1ss_cap and pci_dev.l1ss_cap_ptr - Replace all references to aspm_register_info.(l1ss_cap && l1ss_cap_ptr) with pci_dev.(l1ss_cap && l1ss_cap_ptr) - In pcie_get_aspm_reg() remove reference to aspm_register_info.l1ss_cap* - In pcie_get_aspm_reg() remove reading of l1ss_cap_ptr and l1ss_cap - Remove aspm_register_info.(l1ss_cap && l1ss_cap_ptr) Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 56 +++++++++++++---------------------------- drivers/pci/probe.c | 6 +++++ include/linux/pci.h | 2 ++ 3 files changed, 26 insertions(+), 38 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 321b328347c1..d3ad31a230b5 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -386,8 +386,6 @@ struct aspm_register_info { u32 enabled:2; /* L1 substates */ - u32 l1ss_cap_ptr; - u32 l1ss_cap; u32 l1ss_ctl1; u32 l1ss_ctl2; }; @@ -400,26 +398,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; - /* Read L1 PM substate capabilities */ - info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; - info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!info->l1ss_cap_ptr) - return; - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP, - &info->l1ss_cap); - if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { - info->l1ss_cap = 0; - return; - } - - /* - * If we don't have LTR for the entire path from the Root Complex - * to this device, we can't use ASPM L1.2 because it relies on the - * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. - */ - if (!pdev->ltr_path) - info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, &info->l1ss_ctl1); pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, @@ -494,32 +472,34 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, { u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; + struct pci_dev *dw_pdev = link->downstream; + struct pci_dev *up_pdev = link->pdev; - link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; - link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; + link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr; + link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr; link->l1ss.ctl1 = link->l1ss.ctl2 = 0; if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; /* Choose the greater of the two Port Common_Mode_Restore_Times */ - val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; - val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; + val1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; + val2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; t_common_mode = max(val1, val2); /* Choose the greater of the two Port T_POWER_ON times */ - val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; - scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; - scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; + val1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; + scale1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; + val2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; + scale2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - if (calc_l1ss_pwron(link->pdev, scale1, val1) > - calc_l1ss_pwron(link->downstream, scale2, val2)) { + if (calc_l1ss_pwron(up_pdev, scale1, val1) > + calc_l1ss_pwron(dw_pdev, scale2, val2)) { link->l1ss.ctl2 |= scale1 | (val1 << 3); - t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); + t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1); } else { link->l1ss.ctl2 |= scale2 | (val2 << 3); - t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); + t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2); } /* @@ -603,13 +583,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_dw.l1 = calc_l1_latency(child); /* Setup L1 substate */ - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1_PCIPM; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2_PCIPM; if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2d5898f05f89..71a714065e14 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2107,6 +2107,12 @@ static void pci_configure_ltr(struct pci_dev *dev) if (!pci_is_pcie(dev)) return; + /* Read L1 PM substate capabilities */ + dev->l1ss_cap_ptr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); + if (dev->l1ss_cap_ptr) + pci_read_config_dword(dev, dev->l1ss_cap_ptr + PCI_L1SS_CAP, + &dev->l1ss_cap); + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_LTR)) return; diff --git a/include/linux/pci.h b/include/linux/pci.h index 5b305cfeb1dc..60b82e255738 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -381,6 +381,8 @@ struct pci_dev { struct pcie_link_state *link_state; /* ASPM link state */ unsigned int ltr_path:1; /* Latency Tolerance Reporting supported from root to here */ + int l1ss_cap_ptr; /* L1SS cap ptr, 0 if not supported */ + u32 l1ss_cap; /* L1 PM substate Capabilities */ #endif unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ From patchwork Wed Sep 23 23:15:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795815 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 467516CA for ; Thu, 24 Sep 2020 00:14:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 293F3208B8 for ; Thu, 24 Sep 2020 00:14:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YkeTw4l2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726665AbgIXAO4 (ORCPT ); Wed, 23 Sep 2020 20:14:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAO4 (ORCPT ); Wed, 23 Sep 2020 20:14:56 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FCD9C0613CE for ; Wed, 23 Sep 2020 17:14:56 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id c8so1573385edv.5 for ; Wed, 23 Sep 2020 17:14:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O+0gCUfQpKBUTZFJZ24lqInCxl7vB/u2IOYQOf88Jsc=; b=YkeTw4l2Jzj7Y+mdMx3atKr87ltA0i3jawk+/mzTnbNO4Y/+4ByxH/qOGx4qqTXHt4 Mf2qy6Jp8obd6pjmGUV9DW/QZvR8r8imVXV+vvIoFqYHH0VdfEDY02tug1kZ+NS0Dwxd 0ysD27FBC86BXf76LQ3B6rVRsFy+9bRMGtJc8bIUC+sSsSL+Z5LYfGxDKK1zFsV2pTas NIelwBS4RE4QA6NU5nZfbuKN2hg43eEN7szEJCnQqdkTIYfP82ysG/g4ZxxNiZRYtRR9 vHREFdLaIliYRiotfh39GlMPMu1qQGv3DsVvNb3z397ckZHabQgBc0FxW/fxoqdZ33wv 1W1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O+0gCUfQpKBUTZFJZ24lqInCxl7vB/u2IOYQOf88Jsc=; b=Xag0y7pzmbsXzHnmxcsBUTDgEuv3c1aaQc2RRaqJvKrgmgiy31RJquMS7FnILEFqSV zgDoT1B13UQDFS07TCx9zXOTxVlzH1Y4/Tu5DpC9+CjG+xy4r8u+YvpU6NjGCkMvSiao uOX3L9WsmUFwdEqzfybJ+ioScFC6j+Mx3ZctEQVl+IPW6OraE6IOh3tkCxScVfAUmUIP 2SRYe6LawGeL9E4p0/VDvZDdcfrPJSWdXAfubif8DIDkgS5U7PN1onbJpojrTkVES6TH +B5C638Q+cORvr3uqg7+FBN9bP7+1uFSTzMZ9j312DEEpLz4NyJsT+ZwzDJxX0ypNKEp UN7Q== X-Gm-Message-State: AOAM531U6vQ1D28F2GobKOpp6VWTfs3zhmFuEu5lihIJoSvSvEfDGtu5 6dKoxQ0VM3XV7M+BEtRSC/c= X-Google-Smtp-Source: ABdhPJybcPeoGa/wiD3AQmA9+zk9TM9JHF4dPs0DOhEn3WOZpcAhoDJ8NXySsSssOifcQ33UIExwXw== X-Received: by 2002:a05:6402:a51:: with SMTP id bt17mr1975328edb.186.1600906494843; Wed, 23 Sep 2020 17:14:54 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:54 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 5/8] PCI/ASPM: Remove aspm_register_info.l1ss_ctl* Date: Thu, 24 Sep 2020 01:15:14 +0200 Message-Id: <20200923231517.221310-6-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Read the value of PCI_L1SS_CTL1 directly and cache in local variables. - Replace references to aspm_register_info.l1ss_ctl1 with the variables. - In pcie_get_aspm_reg() remove reference to aspm_register_info.l1ss_ctl* - In pcie_get_aspm_reg() remove reading PCI_L1SS_CTL1 and PCI_L1SS_CTL2 - Remove aspm_register_info.(l1ss_ctl1 && l1ss_ctl2) Note that aspm_register_info.l1ss_ctl2 is eliminated totally since it is not used. Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index d3ad31a230b5..f89d3b2be1c7 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -384,10 +384,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) struct aspm_register_info { u32 enabled:2; - - /* L1 substates */ - u32 l1ss_ctl1; - u32 l1ss_ctl2; }; static void pcie_get_aspm_reg(struct pci_dev *pdev, @@ -397,11 +393,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; - - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, - &info->l1ss_ctl1); - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, - &info->l1ss_ctl2); } static void pcie_aspm_check_latency(struct pci_dev *endpoint) @@ -527,6 +518,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) struct pci_dev *child = link->downstream, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; struct aspm_register_info upreg, dwreg; + u32 up_l1ss_ctl1, dw_l1ss_ctl1; if (blacklist) { /* Set enabled/disable so that we will disable ASPM later */ @@ -549,6 +541,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Configure common clock before checking latencies */ pcie_aspm_configure_common_clock(link); + pci_read_config_dword(parent, parent->l1ss_cap_ptr + PCI_L1SS_CTL1, + &up_l1ss_ctl1); + pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1, + &dw_l1ss_ctl1); + /* * Re-read upstream/downstream components' register state * after clock configuration @@ -592,13 +589,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2_PCIPM; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) link->aspm_enabled |= ASPM_STATE_L1_1; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) From patchwork Wed Sep 23 23:15:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795817 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84649112E for ; Thu, 24 Sep 2020 00:14:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6992321734 for ; Thu, 24 Sep 2020 00:14:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BygXBvxB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726681AbgIXAO6 (ORCPT ); Wed, 23 Sep 2020 20:14:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAO5 (ORCPT ); Wed, 23 Sep 2020 20:14:57 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B042C0613CE for ; Wed, 23 Sep 2020 17:14:57 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id i1so1604309edv.2 for ; Wed, 23 Sep 2020 17:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3opejunV380zsaSYNb96dESI67v7H1F5KotXWkdJHno=; b=BygXBvxBdqtluFCX5vT1AobkCw7BE0fvzPA3CAwfW8odSDEyEsCwGj9LRB++8C0yyt jocGJHRXJ2PZ6aqYXyp248SiGF4HWsRaJ3vDyAXOcFv18BOkR2NWjIO+96RJy7aJnsV9 0XVPZaGVl7naE2vTa8qMBiT6XDB2kLmpBiSHZxgqpTY808d3238VAl7VHrhv2O9jignO QS4MFMiQD+JuUz7fEH5zFBFp+Atk8kk9+5Iuk+kUW0HTXVAJnWI/WvemIdtP5C19VJ/S QgUw3+7nzy7I8+hWmypOXMOPh/Kr9707UkuHrItdGZvXFFQ2JNmiiqTSU2zq1486o2Gh rDtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3opejunV380zsaSYNb96dESI67v7H1F5KotXWkdJHno=; b=cGkmqeNEHx+9hSRX5B8ekBgLiz4mgk+jUg1Box9fkMJ/4+Lck9eKPMPYyYXT4Np8aQ C+BimvUSotyym492Ftj1a7RX4GBk2M/ncSDwsJGdUr4Yut0w7eo++VtK8HDHZFV2neqh HaOkniTnVk2a/hF8pexeCSooLtam2zCa0Lx1iKeERMN7bcxWlwGM7ntKOUPTYcvypUKd a7XmAgpdnE2QAXMGLuAZ9IriQk+u0pVwS2wwiYIr4E+TOyu5yTb7BxHFZJxk4+UJrrgy Ub7nBjXE+/cfKYkQ13wZ+EAjpYfhAJjBwcv+BxUO7jgJ2JZDCqwGS4WBmsldsTGSrEAb RIMA== X-Gm-Message-State: AOAM5328mxHbqVFeA6/rf/lhfJ/7ZjvLgGQKAD8ySx0xd2VTFKfTaZm5 FSa/BYNNC1lIA/0kR+6Gzkg= X-Google-Smtp-Source: ABdhPJwRpF49GdIaC8djfceQhTgQIfO88FOJMdRbouW8JaAQdbizsK6dSh86KCWkpVCeodrPuIflfA== X-Received: by 2002:aa7:d991:: with SMTP id u17mr1934719eds.11.1600906496155; Wed, 23 Sep 2020 17:14:56 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:55 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 6/8] PCI/ASPM: Remove aspm_register_info.enable Date: Thu, 24 Sep 2020 01:15:15 +0200 Message-Id: <20200923231517.221310-7-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Create get_aspm_enable() to compute aspm_register_info.enable directly - Replace all aspm_register_info.enable references with get_aspm_enable() - In pcie_get_aspm_reg() remove reference to aspm_register_info.l1ss_cap* - Remove aspm_register_info.enabled - In pcie_aspm_cap_init() remove all calls to pcie_get_aspm_reg(), since it now does nothing. All the values are calculated elsewhere. Signed-off-by: Saheed O. Bolarinwa --- NOTE: To avoid messing up this patch, the struct aspm_register_info is removed in the next patch. I am not sure if it is better to merge them. drivers/pci/pcie/aspm.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index f89d3b2be1c7..e43fdf0cd08c 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -383,7 +383,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } struct aspm_register_info { - u32 enabled:2; }; static void pcie_get_aspm_reg(struct pci_dev *pdev, @@ -392,7 +391,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, u16 ctl; pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); - info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; } static void pcie_aspm_check_latency(struct pci_dev *endpoint) @@ -513,6 +511,14 @@ static void aspm_support(struct pci_dev *pdev) return (pdev->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10; } +static u32 get_aspm_enable(struct pci_dev *pdev) +{ + u16 ctl; + + pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); + return (ctl & PCI_EXP_LNKCTL_ASPMC); +} + static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; @@ -527,10 +533,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) return; } - /* Get upstream/downstream components' register state */ - pcie_get_aspm_reg(parent, &upreg); - pcie_get_aspm_reg(child, &dwreg); - /* * If ASPM not supported, don't mess with the clocks and link, * bail out now. @@ -546,13 +548,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1, &dw_l1ss_ctl1); - /* - * Re-read upstream/downstream components' register state - * after clock configuration - */ - pcie_get_aspm_reg(parent, &upreg); - pcie_get_aspm_reg(child, &dwreg); - /* * Setup L0s state * @@ -563,9 +558,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L0S) link->aspm_support |= ASPM_STATE_L0S; - if (dwreg.enabled & PCIE_LINK_STATE_L0S) + if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_UP; - if (upreg.enabled & PCIE_LINK_STATE_L0S) + if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; link->latency_up.l0s = calc_l0s_latency(parent); link->latency_dw.l0s = calc_l0s_latency(child); @@ -574,7 +569,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L1) link->aspm_support |= ASPM_STATE_L1; - if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) + if (get_aspm_enable(parent) & get_aspm_enable(child) + & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; link->latency_up.l1 = calc_l1_latency(parent); link->latency_dw.l1 = calc_l1_latency(child); From patchwork Wed Sep 23 23:15:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795819 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F06CE112E for ; Thu, 24 Sep 2020 00:14:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D530820936 for ; Thu, 24 Sep 2020 00:14:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dGN6lnH+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726684AbgIXAO7 (ORCPT ); Wed, 23 Sep 2020 20:14:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAO6 (ORCPT ); Wed, 23 Sep 2020 20:14:58 -0400 Received: from mail-ej1-x641.google.com (mail-ej1-x641.google.com [IPv6:2a00:1450:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77FA0C0613CE for ; Wed, 23 Sep 2020 17:14:58 -0700 (PDT) Received: by mail-ej1-x641.google.com with SMTP id gr14so2069175ejb.1 for ; Wed, 23 Sep 2020 17:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4Z+X4UnmNs9kD39hWhQQ29DlHXSDN88jSqF5HIVTFMw=; b=dGN6lnH+GDPI1sZ2NM5G+LxhJZcvfo+tBNtz9CDTNy53UPEffCa3lBgx6uwHeDIX0c Lvj+gGx1xzgZOJkrC2KHz485kUosvFF/f5SgUwkxNRB5MHcfSPThyfxpNCgZ4D5Uc44G NLaJLaIRLhWVKwg1E+OZL18Wo5rRmXTEAmVhxFSrKvuPBoMOuUKiZzXkjdVDRkDI1kIZ ZbkcBzoXD0UOKw29doACQ+GqSMUoLp2rkZCYwsywzBkgUG9K7InmdJ33VRpjgtmQ2BYC h2RdmFjXcOuzi5SO0O0Dn5NntHrwhu2gD7CB2XaIG0thesKkBlDZGHJNDEBjiK4Qvyhw +owg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4Z+X4UnmNs9kD39hWhQQ29DlHXSDN88jSqF5HIVTFMw=; b=gb9xr1NxN8DAxDB1gK9HtrMTPzchABD3HZ/kksQAlsv81Ft5uG5izg7SbkipoL5KbG 9+qJhCr7KUG/rg74TZO7bZqgXBr3kzJ+dDAQorIL7CcY+TXmxvaaQOB1UmYmQfKnBpaP apMHMfzlqJ1hzxbIta+l4bEYN0bPJXCj8FML0YbqovQmao2cC2BzQp+TlU8tztcB7Sab GvPHAAXB2w3Sv7uEsZcwtaVHuEtg3q+5GApnu8sEJCo85tOB6iVBTA8YzW6mrxIBRPgl 0XTxcpUkCmiDt/9+qkc4LlpDMOVNDheSbh7PHG0yLI02FoPahxebCLxm6GKQvbrMhowQ ES7Q== X-Gm-Message-State: AOAM5336606BPHoQSlhlJhRD4AUTl+PSKCor9L92rjLa/Vhb9TukEPKQ nqepFeevCVQ74f756Xwk0k8= X-Google-Smtp-Source: ABdhPJwlEEipqvI0Ik7ygmIg2WsYBFmyVEweArROoYHWBpY02XQZOJdDs4TuUfcLhBn2AmlfncirXA== X-Received: by 2002:a17:906:82c1:: with SMTP id a1mr2043821ejy.270.1600906497220; Wed, 23 Sep 2020 17:14:57 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:56 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 7/8] PCI/ASPM: Remove pcie_get_aspm_reg() and struct aspm_register_info Date: Thu, 24 Sep 2020 01:15:16 +0200 Message-Id: <20200923231517.221310-8-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Two of aspm_calc_l1ss_info()'s arguments are now redundant. All members of struct aspm_register_info are now calculated directly, so both the struct and pcie_get_aspm_reg() are now useless. - Remove redundant arguments in aspm_calc_l1ss_info(). - Refactor callers to also remove redundant parameters - Remove any remaining call to pcie_get_aspm_reg() - Remove pcie_get_aspm_reg() - Remove remaining reference to struct aspm_register_info. - Remove struct aspm_register_info Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index e43fdf0cd08c..f4fc2d65240c 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -382,17 +382,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } } -struct aspm_register_info { -}; - -static void pcie_get_aspm_reg(struct pci_dev *pdev, - struct aspm_register_info *info) -{ - u16 ctl; - - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); -} - static void pcie_aspm_check_latency(struct pci_dev *endpoint) { u32 latency, l1_switch_latency = 0; @@ -455,9 +444,7 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) } /* Calculate L1.2 PM substate timing parameters */ -static void aspm_calc_l1ss_info(struct pcie_link_state *link, - struct aspm_register_info *upreg, - struct aspm_register_info *dwreg) +static void aspm_calc_l1ss_info(struct pcie_link_state *link) { u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; @@ -523,7 +510,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; - struct aspm_register_info upreg, dwreg; u32 up_l1ss_ctl1, dw_l1ss_ctl1; if (blacklist) { @@ -595,7 +581,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) - aspm_calc_l1ss_info(link, &upreg, &dwreg); + aspm_calc_l1ss_info(link); /* Save default state */ link->aspm_default = link->aspm_enabled; From patchwork Wed Sep 23 23:15:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11795821 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCD056CA for ; Thu, 24 Sep 2020 00:15:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B340E21D91 for ; Thu, 24 Sep 2020 00:15:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="itAKrwDR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726687AbgIXAPA (ORCPT ); Wed, 23 Sep 2020 20:15:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726419AbgIXAPA (ORCPT ); Wed, 23 Sep 2020 20:15:00 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0968C0613CE for ; Wed, 23 Sep 2020 17:14:59 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id gr14so2069225ejb.1 for ; Wed, 23 Sep 2020 17:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xMJO2Jcr81Kz6dNqWOWrAXyKpzQnQDDmiKEkvmDCFHs=; b=itAKrwDR7THUW5vb1fATAqPjIcciWQgvUdDbLWtiMxugPCGaqoklMz4l5vL5iAkJS8 TAm6XOAvfXme6OwnipDWtroxYetRmJByQlBtYMlNaAf99pCO2Vq31WdORfsn+QO/Rwym tBfvpgbbNZ/I8QgTWxnrjH4GjKENr9B5tjm5bl4u/TlA4yWVEKGyq3/IY1QvifNM6khk b+N8GuRTnmFpILNRR1d/QD0xP3Rm9srxVQDtGdxNZXLK2GvdH4toWwAtVRo5mIEIao9x 3K7zAatoM9kx1qA36EcEQ2vQjN++Xnzk94zmQ7JYqZway3QCZ2B4vqnwAnMfOZOClsoG 7xoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xMJO2Jcr81Kz6dNqWOWrAXyKpzQnQDDmiKEkvmDCFHs=; b=gTbAyrFOE0/iURkHbYSG88eAxzHw43G5nGNN8D8t9yGFALQRfJaoqGG+4timDv8UNP AW7ZOzzS//YbwCTpv3vXhM9VhDTHizDEdul0ztXxyF176FCiJA5m8nbVxCwQ6cYigOjM fa0rtzsXk4VLWVC/MpcccBo7ULzW/gbABAuK7x4wNHDw7hmD99AO+Rmcstl+v2UxCHjF C7vix19gC1AluxiagM6sfwIQoMqOSGuwtDl/ff5U+rtjzEy6UlRn/eluhP5WGXqfzoyL kSeui324z5jhBykeuIFkjAa0IzAJmUZZ3lMAnmxDzbIS5+QZraV7NcF54iffC+eku5VQ sI4g== X-Gm-Message-State: AOAM531dtND7uq0majrYtDFObbzFoqFNHOc7LLOEw8XB21hGB1izZiMm wWZIcplthiLwf5L/TG603iA= X-Google-Smtp-Source: ABdhPJyL5fy5D0ORVZQiYxifw7L5iZjWhHi9DLAuojzfSwn2CIZ6UTP1Bh2/AiQU76IDgHpMqLCKUA== X-Received: by 2002:a17:906:24d6:: with SMTP id f22mr2017448ejb.85.1600906498290; Wed, 23 Sep 2020 17:14:58 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id r9sm1026559ejc.102.2020.09.23.17.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 17:14:57 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH 8/8] PCI/ASPM: Remove struct pcie_link_state.l1ss Date: Thu, 24 Sep 2020 01:15:17 +0200 Message-Id: <20200923231517.221310-9-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200923231517.221310-1-refactormyself@gmail.com> References: <20200923231517.221310-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pcie_link_state.l1ss.{up_cap_ptr, dw_cap_ptr} are used to cache the value of l1ss_cap_ptr for upstream and downstream respectively. This value can now be obtained directly from struct pci_dev, it is no longer useful to cache it. So, aspm_calc_l1ss_info() will only be computing the values for ctl1 and ctl2. The addresses of these can also be passed in. Then if aspm_calc_l1ss_info() calculates pcie_link_state.l1ss.{ctl1, ctl2} which are only used inside pcie_config_aspm_l1ss(). Calling the function where it is needed will remove the need to cache the values in the struct. - Move call to aspm_calc_l1ss_info() from pcie_aspm_cap_init() to pcie_config_aspm_l1ss(). - Rename aspm_calc_l1ss_info() to aspm_calc_l1ss_ctl_values(). - Rework the function to take a pci_dev and pointers to ctl1 and ctl2. - Change calls to aspm_calc_l1ss_info() into new function. - Replace l1ss.{up,dw}_cap_ptr with pci_dev->l1ss_cap_ptr - Replace pcie_link_state.l1ss.{ctl1, ctl2} with local variables. - No more reference to struct pcie_link_state.l1ss, so remove it. - Remove pcie_link_state.l1ss Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 45 ++++++++++++++--------------------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index f4fc2d65240c..b9bacdef8c80 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -74,14 +74,6 @@ struct pcie_link_state { * has one slot under it, so at most there are 8 functions. */ struct aspm_latency acceptable[8]; - - /* L1 PM Substate info */ - struct { - u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */ - u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */ - u32 ctl1; /* value to be programmed in ctl1 */ - u32 ctl2; /* value to be programmed in ctl2 */ - } l1ss; }; static int aspm_disabled, aspm_force; @@ -444,17 +436,15 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) } /* Calculate L1.2 PM substate timing parameters */ -static void aspm_calc_l1ss_info(struct pcie_link_state *link) +static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev, + u32 *ctl1, u32 *ctl2) { + struct pcie_link_state *link = pdev->link_state; u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; struct pci_dev *dw_pdev = link->downstream; struct pci_dev *up_pdev = link->pdev; - link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr; - link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr; - link->l1ss.ctl1 = link->l1ss.ctl2 = 0; - if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; @@ -471,10 +461,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link) if (calc_l1ss_pwron(up_pdev, scale1, val1) > calc_l1ss_pwron(dw_pdev, scale2, val2)) { - link->l1ss.ctl2 |= scale1 | (val1 << 3); + *ctl2 |= scale1 | (val1 << 3); t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1); } else { - link->l1ss.ctl2 |= scale2 | (val2 << 3); + *ctl2 |= scale2 | (val2 << 3); t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2); } @@ -490,7 +480,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link) */ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; encode_l12_threshold(l1_2_threshold, &scale, &value); - link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; + *ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } static void aspm_support(struct pci_dev *pdev) @@ -580,9 +570,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; - if (link->aspm_support & ASPM_STATE_L1SS) - aspm_calc_l1ss_info(link); - /* Save default state */ link->aspm_default = link->aspm_enabled; @@ -625,12 +612,13 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, /* Configure the ASPM L1 substates */ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) { - u32 val, enable_req; + u32 val, enable_req, ctl1, ctl2; struct pci_dev *child = link->downstream, *parent = link->pdev; - u32 up_cap_ptr = link->l1ss.up_cap_ptr; - u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; + int up_cap_ptr = parent->l1ss_cap_ptr; + int dw_cap_ptr = child->l1ss_cap_ptr; enable_req = (link->aspm_enabled ^ state) & state; + aspm_calc_l1ss_ctl_values(parent, &ctl1, &ctl2); /* * Here are the rules specified in the PCIe spec for enabling L1SS: @@ -665,24 +653,21 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) /* Program T_POWER_ON times in both ports */ pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, - link->l1ss.ctl2); + ctl2); pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, - link->l1ss.ctl2); + ctl2); /* Program Common_Mode_Restore_Time in upstream device */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CTL1_CM_RESTORE_TIME, - link->l1ss.ctl1); + PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1); /* Program LTR_L1.2_THRESHOLD time in both ports */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); } val = 0;