From patchwork Thu Sep 24 14:24:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11797695 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CE6F6CB for ; Thu, 24 Sep 2020 15:24:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 821D5238A1 for ; Thu, 24 Sep 2020 15:24:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cKO1/dw7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728432AbgIXPYP (ORCPT ); Thu, 24 Sep 2020 11:24:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbgIXPYO (ORCPT ); Thu, 24 Sep 2020 11:24:14 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DC64C0613CE for ; Thu, 24 Sep 2020 08:24:14 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id z23so4982545ejr.13 for ; Thu, 24 Sep 2020 08:24:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7kHwfcAazeBg+h2uEVovJwlfIIrEWzUTpgb6sW8h8RI=; b=cKO1/dw7vR3pvZAtvJzVVZU3A0UrzI7YmHvx0MDAmeRXVV0jWVmum7kzwPL5gjOE1b 01wD06CN9lIYPnCn8yfjGd8a0EefOejZOeRx1mSt+avP5Vmi+8ym5P031TdYf4SJUcvH XaeRkMXU8aeocsep0hN7697QCbYZPj7MLARWlZzB848mO8ZZ8XmEzKoikkAnS3QbeSTh d/2vhEWZOzR0IXi1dZQDv8/sgHwDR5La97NTI7a5M2IFsS39CJkPp0vTrE6ozrmIQp/+ HOr8iuQc2GbAhsr+NwN51lf1RdZnXiql1i+BjeRLCpyRkckXZ7izmrBnqDdsyQfgRLvo iRqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7kHwfcAazeBg+h2uEVovJwlfIIrEWzUTpgb6sW8h8RI=; b=Z9adWHPDeOdIOfk9Vl/wmxzt62YM1kQgrXIa2FWcY9xVWV1WyLokoVORZoqhSUF5aa aAgYmK4VyXZvHBrq2jeYDiDESt+Q4i3f1v6HEQ2KZ1p9pW2gvGGL/HUSAnepHLMOEI3f wPggaWwVmqz73wUwQYUWxNxf9n1dcOlN9oSGBC0HNfM/CHR9CXY4DU3LBNfNZw2EDqg6 VCyd28ox5jYNw249mURkdUSV2zQ/XjEqrwav5JwYvnKMzFzbjhc0qkwUDDnwIyVIyEQg wWEtg2elYHgnwinN3je2Zq+psQFo7HkKObvo8tS5WbEwoH8LN9KDnveM6XO9O0qaQn1y 4FeQ== X-Gm-Message-State: AOAM533qaHkPeKCgHsWqyL2KpEeQ053z7bKkCixQ1RbsHcoVSs3lzCgD BhfOtkSxxmbSZq+ilUp+oRI= X-Google-Smtp-Source: ABdhPJycTMt0iBMbMs1r0za9D8QSz2i9l1CXXdE5NuEwInEv+Xpo+JY/udUHiXtYG9OI+L2bzXmyNw== X-Received: by 2002:a17:906:f1d5:: with SMTP id gx21mr384571ejb.165.1600961053192; Thu, 24 Sep 2020 08:24:13 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:12 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 1/7] PCI/ASPM: Cache device's ASPM link capability in struct pci_dev Date: Thu, 24 Sep 2020 16:24:37 +0200 Message-Id: <20200924142443.260861-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pcie_get_aspm_reg() reads LNKCAP to learn whether the device supports ASPM L0s and/or L1 and L1 substates. If we cache the entire LNKCAP word early enough, we may be able to use it in other places that read LNKCAP, e.g. pcie_get_speed_cap(), pcie_get_width_cap(), pcie_init(), etc. - Add struct pci_dev.lnkcap (u32) - Read PCI_EXP_LNKCAP in set_pcie_port_type() and save it in pci_dev.lnkcap - Use pdev->lnkcap instead of reading PCI_EXP_LNKCAP Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 7 ++----- drivers/pci/probe.c | 1 + include/linux/pci.h | 1 + 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 253c30cc1967..d7e69b3595a0 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -177,15 +177,13 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable) static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) { int capable = 1, enabled = 1; - u32 reg32; u16 reg16; struct pci_dev *child; struct pci_bus *linkbus = link->pdev->subordinate; /* All functions should have the same cap and state, take the worst */ list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); - if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { + if (!(child->lnkcap & PCI_EXP_LNKCAP_CLKPM)) { capable = 0; enabled = 0; break; @@ -397,9 +395,8 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { u16 reg16; - u32 reg32; + u32 reg32 = pdev->lnkcap; - pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 03d37128a24f..2d5898f05f89 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1486,6 +1486,7 @@ void set_pcie_port_type(struct pci_dev *pdev) pdev->pcie_flags_reg = reg16; pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &pdev->lnkcap); parent = pci_upstream_bridge(pdev); if (!parent) diff --git a/include/linux/pci.h b/include/linux/pci.h index 835530605c0d..5b305cfeb1dc 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -375,6 +375,7 @@ struct pci_dev { bit manually */ unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ + u32 lnkcap; /* Link Capabilities */ #ifdef CONFIG_PCIEASPM struct pcie_link_state *link_state; /* ASPM link state */ From patchwork Thu Sep 24 14:24:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11797697 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C69606CA for ; Thu, 24 Sep 2020 15:24:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A8663238A1 for ; Thu, 24 Sep 2020 15:24:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XIvFWIgZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728434AbgIXPYQ (ORCPT ); Thu, 24 Sep 2020 11:24:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbgIXPYQ (ORCPT ); Thu, 24 Sep 2020 11:24:16 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3A46C0613CE for ; Thu, 24 Sep 2020 08:24:15 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id q13so5013741ejo.9 for ; Thu, 24 Sep 2020 08:24:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=avYflrEIwbhH8rFwntiZPPaA0Uaq3GfuFh1DgQVMGyA=; b=XIvFWIgZBWyNZUkBfc2w/RllzBf6qyCAhpJJ+GV0SOqJwljpEP755cERzLLkV88jc4 jLPeSRpxL08ldJVwiaQuc5METfOcB0sd84kS1e9VPBX1B9bqMd+Gi+1rm3Xd1QzrioQm gaUjs2xaoL0I51k7QcmLnMcxCNcubQ5fszwmU8DJNtssUBtt5WGqsND/FUUQDjMVAX8e hhh30k7Q9Vzl/2veiiTqgp7go7GknGRsXRXIvFDzBQpk8VpeE3bSy0aB7pFTqar+zGIq GtcS/5vRLjkDVhhJ7rXF3GRB8f9FsDEmUWfnQrvloiLBXwJjD623gt/BPXURQsFEjCQj 9zCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=avYflrEIwbhH8rFwntiZPPaA0Uaq3GfuFh1DgQVMGyA=; b=iqxSywImfNott6mmKy/UAWY5JpYDG0x9gTySTKqUEPs+s0e7MT0Ll1ZdGPZvlZWKwU O7AR5TcusJXnus1nJEaVBAxTM6k63E06/K7EJTBMwMjL4/UUoAnItt3LdF7iTh2nBqHp Xw8sl99Ujs78yRn3bTkXtw4FwCkrclYyqJy0nXjny+6uQ4bs8/ezTHEdP5QnfqeltGoq 5dDSGpW3tPQxuEN/xvECLC2/CivA8GJmspqZ0Idws4yIwhHBsUioqPLVYT5aNyJ7AH3V 8VJWTC52aXZ5dJ0O7wrlWgtOdzN4xC0Hi6Gy7UyqedrShF7B9CijphT3EWfhtfAke7vu bifQ== X-Gm-Message-State: AOAM533adDsYiNCWFEjl0DeVm8Be2jPiKoTMnAsRcqQaPOOJ732Sah8e R+3XEf+71lJZn3B9dEOOFEgMPd90UBX7hg== X-Google-Smtp-Source: ABdhPJxNO0zSRK57nZRgxmDoeCO3EdntHuEtrUNmcHzEbiM0RV369GE8ehUpcFwQ0I3ukJkcaCAWxQ== X-Received: by 2002:a17:906:841a:: with SMTP id n26mr401568ejx.213.1600961054450; Thu, 24 Sep 2020 08:24:14 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:13 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 2/7] PCI/ASPM: Rework calc_l*_latency() to take a struct pci_dev Date: Thu, 24 Sep 2020 16:24:38 +0200 Message-Id: <20200924142443.260861-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Change the argument of calc_l0s_latency() to pci_dev *, - Compute latency_encoding_l0s encoding inside calc_l0s_latency() - Compute latency_encoding_l1 encoding inside calc_l1_latency() - Make calc_l*_latency() take only pci_dev *, - Make callers to calc_l0s_latency() and calc_l1_latency() pass in struct pci_dev - In pcie_get_aspm_reg() remove assignments to the latency encodings - Remove aspm_register_info.latency_encoding_l1 - Remove aspm_register_info.latency_encoding_l0s Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index d7e69b3595a0..5f7cf47b6a40 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -306,8 +306,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) } /* Convert L0s latency encoding to ns */ -static u32 calc_l0s_latency(u32 encoding) +static u32 calc_l0s_latency(struct pci_dev *pdev) { + u32 encoding = (pdev->lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + if (encoding == 0x7) return (5 * 1000); /* > 4us */ return (64 << encoding); @@ -322,8 +324,10 @@ static u32 calc_l0s_acceptable(u32 encoding) } /* Convert L1 latency encoding to ns */ -static u32 calc_l1_latency(u32 encoding) +static u32 calc_l1_latency(struct pci_dev *pdev) { + u32 encoding = (pdev->lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + if (encoding == 0x7) return (65 * 1000); /* > 64us */ return (1000 << encoding); @@ -381,8 +385,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) struct aspm_register_info { u32 support:2; u32 enabled:2; - u32 latency_encoding_l0s; - u32 latency_encoding_l1; /* L1 substates */ u32 l1ss_cap_ptr; @@ -398,8 +400,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, u32 reg32 = pdev->lnkcap; info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; - info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; - info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; @@ -587,16 +587,16 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (upreg.enabled & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; - link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); - link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); + link->latency_up.l0s = calc_l0s_latency(parent); + link->latency_dw.l0s = calc_l0s_latency(child); /* Setup L1 state */ if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) link->aspm_support |= ASPM_STATE_L1; if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; - link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); - link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); + link->latency_up.l1 = calc_l1_latency(parent); + link->latency_dw.l1 = calc_l1_latency(child); /* Setup L1 substate */ if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) From patchwork Thu Sep 24 14:24:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11797699 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F4816CA for ; Thu, 24 Sep 2020 15:24:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1320D2388A for ; Thu, 24 Sep 2020 15:24:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZLbKpduj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728465AbgIXPYR (ORCPT ); Thu, 24 Sep 2020 11:24:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbgIXPYR (ORCPT ); Thu, 24 Sep 2020 11:24:17 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03B24C0613CE for ; Thu, 24 Sep 2020 08:24:17 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id z22so5041268ejl.7 for ; Thu, 24 Sep 2020 08:24:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gqOo9sRKsu8OklEdZbxfDsKXZHiV2LQufDSEO7PGLPM=; b=ZLbKpdujpsyuwlg3VvHrMe5dseLSbvSLOuFoF+mPsRr7sm59RyPtI2arMz7XfihkEL KzACRGtJNUuWwUCQX3ejN/qe4Qq5vPq6QaOYKrgSrsBDw/xSRUfxwuprhPmIgeOcjeUV pbYyeXitK1Fk934gvybAw5vK8KARG1MdBKoOKjeOPhFVqKkRErfIS8+rX3QI7dMK7yyb PuirOvqjzrr4FHnCsZPKP41nXD3k6r69BeioENXZRBpJ9AgUHJBmbOFDVZtjRS1kk+Yy kmfrnNYCxW9ZuIAyvCR4iimLe6zLI9VHldWjLtuCI1bp71enx/nTIAxOAlNQTfMs8Cx/ WRFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gqOo9sRKsu8OklEdZbxfDsKXZHiV2LQufDSEO7PGLPM=; b=RscjomifTa1IXalXMPf4NnX3E8srRtrVpGJsIm+pOzTry/Y0UxyWDQEPl2GY42g0nE IvSx3YeVbsadvzsku0unkqmX8s9qO+FKIDpXmM956Jz5NXBIOwcEimDM/xvnhwi06Ut6 i/J9rXRh6KHsuYJCAB2SKG5dr3qYX1pA+UqyCVGIIgkaip6iXPW/sofvikhEyyrQJe8G HlsghE4+krl55SaB5oiBehSDgyP8eL0EqKRPPAzjdmn944/LUs+2hpvejM+VMtakUVPI LklkrNUy4I1mQNopF3g9VTO7EheoO+s2DEJrblBLYZm+FnRnyd/tUT0223lKbIPlSzwN hwfQ== X-Gm-Message-State: AOAM5329+bZn4FtfDErIoXzki7NmLTGISnA+cYFHRDUlxaW/tQDdbU/R fl8KqYLNaJArG2c8Ton7Tfc= X-Google-Smtp-Source: ABdhPJxYZ4U5br55orZCpnApMVEk0NxOgpjlpNQk+4fYXYhcnsUiE6L1KaDgakj1tQWN84GzELx+9Q== X-Received: by 2002:a17:906:17c6:: with SMTP id u6mr418428eje.95.1600961055606; Thu, 24 Sep 2020 08:24:15 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:15 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 3/7] PCI/ASPM: Compute the value of aspm_register_info.support directly Date: Thu, 24 Sep 2020 16:24:39 +0200 Message-Id: <20200924142443.260861-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Calculate aspm_register_info.support inside aspm_support() - Replace references to aspm_register_info.support with aspm_support(). - In pcie_get_aspm_reg() remove assignment to aspm_register_info.support - Remove aspm_register_info.support Signed-off-by: Saheed O. Bolarinwa Reported-by: kernel test robot --- drivers/pci/pcie/aspm.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 5f7cf47b6a40..321b328347c1 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -383,7 +383,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } struct aspm_register_info { - u32 support:2; u32 enabled:2; /* L1 substates */ @@ -396,12 +395,10 @@ struct aspm_register_info { static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { - u16 reg16; - u32 reg32 = pdev->lnkcap; + u16 ctl; - info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); - info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; + pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); + info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; /* Read L1 PM substate capabilities */ info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; @@ -540,6 +537,11 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } +static void aspm_support(struct pci_dev *pdev) +{ + return (pdev->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10; +} + static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; @@ -561,7 +563,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) * If ASPM not supported, don't mess with the clocks and link, * bail out now. */ - if (!(upreg.support & dwreg.support)) + if (!(aspm_support(parent) & aspm_support(child))) return; /* Configure common clock before checking latencies */ @@ -581,8 +583,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) * given link unless components on both sides of the link each * support L0s. */ - if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) + if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L0S) link->aspm_support |= ASPM_STATE_L0S; + if (dwreg.enabled & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (upreg.enabled & PCIE_LINK_STATE_L0S) @@ -591,8 +594,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_dw.l0s = calc_l0s_latency(child); /* Setup L1 state */ - if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) + if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L1) link->aspm_support |= ASPM_STATE_L1; + if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; link->latency_up.l1 = calc_l1_latency(parent); From patchwork Thu Sep 24 14:24:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11797701 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 442266CB for ; Thu, 24 Sep 2020 15:24:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 223982388A for ; Thu, 24 Sep 2020 15:24:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="t04CsfL6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728472AbgIXPYS (ORCPT ); Thu, 24 Sep 2020 11:24:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbgIXPYS (ORCPT ); Thu, 24 Sep 2020 11:24:18 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CC28C0613CE for ; Thu, 24 Sep 2020 08:24:18 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id i1so3813243edv.2 for ; Thu, 24 Sep 2020 08:24:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jnTqkMfg+pF303Rlza2fs/WGjR363sRc72ZJW6h8OKQ=; b=t04CsfL6CqOV0vgChqvejovaW8e0Cn9+EYyl5tGe+2bUJAP063LIYx4s7nf6TbW7Mk 9pJLF50FDkkPFYel2Y26ue50IvbVvYDtO+sZm1wWPPWFIAc1VkwJ5pL+7pj+hiZGAilD PWx4vZPS/6YzMrdDl/mm4qzlbRcNUNdVSpcGkid1xK5seWeQphPBd6wHW2aTWyt4Vuz0 vazBfw7OUFHADm/XcniKMxQui+gsPKGRd+yH/QAWNb/w/kBrA8WpW9vYwB1sGq7NVz7U il1XotF5O+r5wGTFPcbl7LgVhhbgJ2gu0HSoLHw0yzAz56VbujHy0BEG7PxwqA1L2Y/d yH2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jnTqkMfg+pF303Rlza2fs/WGjR363sRc72ZJW6h8OKQ=; b=Uf8kxMYKAu8kPYdRwKava1/7QlPsX99L6eqoA78PcIWd5B+vIntc0x4azL6/SIstbj u0D9BYQ8LJ1lzdXgt5HOTVrBu8qg2hEUuxJXfKNJdLNeB63uir29oIYmSdOovl/xjGST Cy/qFI3HzQjGLMpEGBOLN25VO16haFcMx0chW15AnBkTNsvPCxQ5APjA9Fw8xS5jiB4w 7SEzWVsYOlR7ns1dSTechYgFNP9C4pbAHZKoZQnOEp0B16wU3X+OLS39WJ2cJgZQIim2 7jNjS7z/+ZllXXFgAJvlMgPUq4lJRQuCcD9GviIkTySSme/GROf4uP9T1EOpDL4P9d4J /gHg== X-Gm-Message-State: AOAM530VXBgYHdeXMhleUMzqHXSmrbpV89QwOUe2KTRtW8zN8mbbrAh9 5FOnFN0Slc3PWtVYygaYSaE= X-Google-Smtp-Source: ABdhPJzUGOHX6ijc5vd0lkVgvTrvx8RNXvD1Jkf5oX28zV/PrUulWQg5XfGQvYL81Krn+tPossyqSQ== X-Received: by 2002:a50:9355:: with SMTP id n21mr401286eda.237.1600961056809; Thu, 24 Sep 2020 08:24:16 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:16 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 4/7] PCI/ASPM: Replace aspm_register_info.l1ss_cap* Date: Thu, 24 Sep 2020 16:24:40 +0200 Message-Id: <20200924142443.260861-5-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Add l1ss_cap and l1ss_cap_ptr to struct pci_dev - In pci_configure_ltr(), compute the value of pci_dev.l1ss_cap and pci_dev.l1ss_cap_ptr - Replace all references to aspm_register_info.(l1ss_cap && l1ss_cap_ptr) with pci_dev.(l1ss_cap && l1ss_cap_ptr) - Remove the now redundant parameters of aspm_calc_l1ss_info() - Change callers of aspm_calc_l1ss_info() to use the new signature - In pcie_get_aspm_reg() remove reference to aspm_register_info.l1ss_cap* - In pcie_get_aspm_reg() remove reading of l1ss_cap_ptr and l1ss_cap - Remove aspm_register_info.(l1ss_cap && l1ss_cap_ptr) Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 62 +++++++++++++---------------------------- drivers/pci/probe.c | 6 ++++ include/linux/pci.h | 2 ++ 3 files changed, 28 insertions(+), 42 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 321b328347c1..e7bb7d069361 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -386,8 +386,6 @@ struct aspm_register_info { u32 enabled:2; /* L1 substates */ - u32 l1ss_cap_ptr; - u32 l1ss_cap; u32 l1ss_ctl1; u32 l1ss_ctl2; }; @@ -400,26 +398,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; - /* Read L1 PM substate capabilities */ - info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; - info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!info->l1ss_cap_ptr) - return; - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP, - &info->l1ss_cap); - if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { - info->l1ss_cap = 0; - return; - } - - /* - * If we don't have LTR for the entire path from the Root Complex - * to this device, we can't use ASPM L1.2 because it relies on the - * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. - */ - if (!pdev->ltr_path) - info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, &info->l1ss_ctl1); pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, @@ -488,38 +466,38 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) } /* Calculate L1.2 PM substate timing parameters */ -static void aspm_calc_l1ss_info(struct pcie_link_state *link, - struct aspm_register_info *upreg, - struct aspm_register_info *dwreg) +static void aspm_calc_l1ss_info(struct pcie_link_state *link) { u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; + struct pci_dev *dw_pdev = link->downstream; + struct pci_dev *up_pdev = link->pdev; - link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; - link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; + link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr; + link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr; link->l1ss.ctl1 = link->l1ss.ctl2 = 0; if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; /* Choose the greater of the two Port Common_Mode_Restore_Times */ - val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; - val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; + val1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; + val2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; t_common_mode = max(val1, val2); /* Choose the greater of the two Port T_POWER_ON times */ - val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; - scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; - scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; + val1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; + scale1 = (up_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; + val2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; + scale2 = (dw_pdev->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - if (calc_l1ss_pwron(link->pdev, scale1, val1) > - calc_l1ss_pwron(link->downstream, scale2, val2)) { + if (calc_l1ss_pwron(up_pdev, scale1, val1) > + calc_l1ss_pwron(dw_pdev, scale2, val2)) { link->l1ss.ctl2 |= scale1 | (val1 << 3); - t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); + t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1); } else { link->l1ss.ctl2 |= scale2 | (val2 << 3); - t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); + t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2); } /* @@ -603,13 +581,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_dw.l1 = calc_l1_latency(child); /* Setup L1 substate */ - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1_PCIPM; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) + if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2_PCIPM; if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) @@ -622,7 +600,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) - aspm_calc_l1ss_info(link, &upreg, &dwreg); + aspm_calc_l1ss_info(link); /* Save default state */ link->aspm_default = link->aspm_enabled; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2d5898f05f89..71a714065e14 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2107,6 +2107,12 @@ static void pci_configure_ltr(struct pci_dev *dev) if (!pci_is_pcie(dev)) return; + /* Read L1 PM substate capabilities */ + dev->l1ss_cap_ptr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); + if (dev->l1ss_cap_ptr) + pci_read_config_dword(dev, dev->l1ss_cap_ptr + PCI_L1SS_CAP, + &dev->l1ss_cap); + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_LTR)) return; diff --git a/include/linux/pci.h b/include/linux/pci.h index 5b305cfeb1dc..60b82e255738 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -381,6 +381,8 @@ struct pci_dev { struct pcie_link_state *link_state; /* ASPM link state */ unsigned int ltr_path:1; /* Latency Tolerance Reporting supported from root to here */ + int l1ss_cap_ptr; /* L1SS cap ptr, 0 if not supported */ + u32 l1ss_cap; /* L1 PM substate Capabilities */ #endif unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ From patchwork Thu Sep 24 14:24:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11797703 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 758536CB for ; Thu, 24 Sep 2020 15:24:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 563A62388A for ; Thu, 24 Sep 2020 15:24:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="a8a9zxl6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728474AbgIXPYT (ORCPT ); Thu, 24 Sep 2020 11:24:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbgIXPYT (ORCPT ); Thu, 24 Sep 2020 11:24:19 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46682C0613CE for ; Thu, 24 Sep 2020 08:24:19 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id z22so5041450ejl.7 for ; Thu, 24 Sep 2020 08:24:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vcc0BYnocUTKGJbOFWpRFtp+y0ZbkIBTKk3LLhU83hU=; b=a8a9zxl6ALelKDlciaXgXi0krqYPQ6uS1ixXsydbgTyRARo8dATmjkouXuksyKz5cm 4M3KyTkLbodaYaYPS99zNgSrxm+bfHCBHnYdpBTTrU+HB5pAESkj/AhOzm7ST3pwtqcJ 8IUAjpheSjeyeF4eMszoqGdmCbfDwuvWnVqvTJnQOUfc8h/5KNuFmGcRzcHKAxREoGuM 8RUhqP03xeNC5NmdDAlhfBpqrSzrBlxruDlzkjqiWTrKr9vP55iKkegercICcQjieXjh PLRObKeNaCDu7uygRuMpDJLNZDXO8mpOr48c6aBIWtPD/KhiUnFUeEWqbRNl51kfGYe/ mWLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vcc0BYnocUTKGJbOFWpRFtp+y0ZbkIBTKk3LLhU83hU=; b=BESoVMAX8l/9IZUFAzjXYGTYrvyTXIDj2lQmsKUb4v6p5uKXRV6VuAlOCTfPgzbJcj 1IocqldmyKlpjkQ63OIsbpy+iqVpiczXrXjCXYPRnFf9O9GXP06EytPRSVfPzj/lmWKa pDOmfR/ZLhuXQagpxVRJEX30BuL2WXv+UbPRTAd+AqwrlijgUxHpGzzem7MvGkU9m0WZ 5WpAnKzgjQQdtkPlyMLawlIFg8mWsyzg3H7imQK2E9WWwYumeLbOJAhV9fxl0PltxT8x imMyBg0UxCcbCcZDVGDGrquhvr8INeVGEr7rde5STsI72IlmJSo+7YhJM2Imv/qBL+g1 SFyw== X-Gm-Message-State: AOAM5313QuMUlt2mtlFNGCrr4TUAHSCe3bIlEAPXlgNLx8g6BqvOoxl0 H3ZDOrjycmMEBf28QF0UtMU= X-Google-Smtp-Source: ABdhPJypogfPGDUFMLIIH6QK+erQGezPk6nReuceQ+TnADEc3hBET57fzS9Wt5XkIQrszQpbUBcvXQ== X-Received: by 2002:a17:906:1909:: with SMTP id a9mr402218eje.127.1600961058004; Thu, 24 Sep 2020 08:24:18 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:17 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 5/7] PCI/ASPM: Remove aspm_register_info.l1ss_ctl* Date: Thu, 24 Sep 2020 16:24:41 +0200 Message-Id: <20200924142443.260861-6-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Read the value of PCI_L1SS_CTL1 directly and cache in local variables. - Replace references to aspm_register_info.l1ss_ctl1 with the variables. - In pcie_get_aspm_reg() remove reference to aspm_register_info.l1ss_ctl* - In pcie_get_aspm_reg() remove reading PCI_L1SS_CTL1 and PCI_L1SS_CTL2 - Remove aspm_register_info.(l1ss_ctl1 && l1ss_ctl2) Note that aspm_register_info.l1ss_ctl2 is eliminated totally since it is not used. Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index e7bb7d069361..cec8acad6363 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -384,10 +384,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) struct aspm_register_info { u32 enabled:2; - - /* L1 substates */ - u32 l1ss_ctl1; - u32 l1ss_ctl2; }; static void pcie_get_aspm_reg(struct pci_dev *pdev, @@ -397,11 +393,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; - - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, - &info->l1ss_ctl1); - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, - &info->l1ss_ctl2); } static void pcie_aspm_check_latency(struct pci_dev *endpoint) @@ -525,6 +516,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) struct pci_dev *child = link->downstream, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; struct aspm_register_info upreg, dwreg; + u32 up_l1ss_ctl1, dw_l1ss_ctl1; if (blacklist) { /* Set enabled/disable so that we will disable ASPM later */ @@ -547,6 +539,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) /* Configure common clock before checking latencies */ pcie_aspm_configure_common_clock(link); + pci_read_config_dword(parent, parent->l1ss_cap_ptr + PCI_L1SS_CTL1, + &up_l1ss_ctl1); + pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1, + &dw_l1ss_ctl1); + /* * Re-read upstream/downstream components' register state * after clock configuration @@ -590,13 +587,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2_PCIPM; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) link->aspm_enabled |= ASPM_STATE_L1_1; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) + if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) From patchwork Thu Sep 24 14:24:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11797705 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B20126CA for ; Thu, 24 Sep 2020 15:24:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8FFF9238A1 for ; Thu, 24 Sep 2020 15:24:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ncu8qcj7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728476AbgIXPYV (ORCPT ); Thu, 24 Sep 2020 11:24:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728285AbgIXPYU (ORCPT ); Thu, 24 Sep 2020 11:24:20 -0400 Received: from mail-ed1-x541.google.com (mail-ed1-x541.google.com [IPv6:2a00:1450:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77049C0613CE for ; Thu, 24 Sep 2020 08:24:20 -0700 (PDT) Received: by mail-ed1-x541.google.com with SMTP id n13so3741990edo.10 for ; Thu, 24 Sep 2020 08:24:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CxVW/OWl4rMkNznVqITBMJOJXHc5RmUmH3vwqAEU0DQ=; b=ncu8qcj7DhmsrWBGM835amPn69Jtz8xy5/AVqlrbz/f8VqtykGkGQk3dt1ePfMkS16 vp98Ke8jse+gelLvzSTkVGgchExsJbhWH/J6ZZJeSK5rH+vIdJGiH5BtUcvZfEdA6hLq KJodMN30l64ciHdTZ08q1wQt6ts88Sc/vYs+/o+C+WeZT2s8Db3BtO6DB7p2F8jGWQPB pORPnoIYfOazcyL8JjvdqoV776zJHjFRoWweh4XjisfUpQTmbTw9gOrSvnqupn5nYW7/ CXPTIPZfvheWAQyqMCnH1ltZsgVXY/q2EhpsxG4ls2A16LRN1qXVGSPlMH/JWq9E7YRu CS/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CxVW/OWl4rMkNznVqITBMJOJXHc5RmUmH3vwqAEU0DQ=; b=SEVxKtpuVW026DWiiMp719oEydcfreg4L0a6axTei6zzNBQ+2UdZOTEus5+Ju0Z4Ie k0ER8FLoMUaLh4Yl89KjbVVtWnNF5FSduT/idIl6k4xB1W7l8nNGjH/iW9tABb2VNSo9 4z6rQ/PYw+OakoEwo5TWFEbGBzT4vM0hwxWkIU6ZydvtrLurzUoWfa2X9ZxXqM/Fobek gY7pLApgYqZ+usfkyISjz6e8gBJQbj4aBK65ao4lyqsIp/CzdUQ3muSwraGPKIUBaoTi 5JfLuK62gACDhUZ0TpxXLcvkariy+fH2IHjTiSuSdt4gK358BFJW08b9KNwriu77OiQV tRJg== X-Gm-Message-State: AOAM5323RL3VxFihx/3neqFg5xIR08Bd77wua1hAVH0uUDpxJdrfJE29 WdLV6AaV2ESa3la9tEGZhqkB62qND2g7ew== X-Google-Smtp-Source: ABdhPJz+E3+k23UgUoB72jvcjx9LSIqrhy1VdKY3oyc8cJ4WHRNxBc/lf+E+DWYl+qvLBFMr1nN2lw== X-Received: by 2002:aa7:db02:: with SMTP id t2mr420466eds.95.1600961059103; Thu, 24 Sep 2020 08:24:19 -0700 (PDT) Received: from net.saheed (5402C65D.dsl.pool.telekom.hu. [84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:18 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 6/7] PCI/ASPM: Remove struct aspm_register_info and pcie_get_aspm_reg() Date: Thu, 24 Sep 2020 16:24:42 +0200 Message-Id: <20200924142443.260861-7-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org - Create get_aspm_enable() to compute aspm_register_info.enable directly - Replace all aspm_register_info.enable references with get_aspm_enable() - Remove pcie_get_aspm_reg() and all calls to it. All the values are now calculated elsewhere. - Remove struct aspm_register_info and its references Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 40 ++++++++++++---------------------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index cec8acad6363..f4fc2d65240c 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -382,19 +382,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } } -struct aspm_register_info { - u32 enabled:2; -}; - -static void pcie_get_aspm_reg(struct pci_dev *pdev, - struct aspm_register_info *info) -{ - u16 ctl; - - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); - info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC; -} - static void pcie_aspm_check_latency(struct pci_dev *endpoint) { u32 latency, l1_switch_latency = 0; @@ -511,11 +498,18 @@ static void aspm_support(struct pci_dev *pdev) return (pdev->lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10; } +static u32 get_aspm_enable(struct pci_dev *pdev) +{ + u16 ctl; + + pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl); + return (ctl & PCI_EXP_LNKCTL_ASPMC); +} + static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; - struct aspm_register_info upreg, dwreg; u32 up_l1ss_ctl1, dw_l1ss_ctl1; if (blacklist) { @@ -525,10 +519,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) return; } - /* Get upstream/downstream components' register state */ - pcie_get_aspm_reg(parent, &upreg); - pcie_get_aspm_reg(child, &dwreg); - /* * If ASPM not supported, don't mess with the clocks and link, * bail out now. @@ -544,13 +534,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1, &dw_l1ss_ctl1); - /* - * Re-read upstream/downstream components' register state - * after clock configuration - */ - pcie_get_aspm_reg(parent, &upreg); - pcie_get_aspm_reg(child, &dwreg); - /* * Setup L0s state * @@ -561,9 +544,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L0S) link->aspm_support |= ASPM_STATE_L0S; - if (dwreg.enabled & PCIE_LINK_STATE_L0S) + if (get_aspm_enable(child) & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_UP; - if (upreg.enabled & PCIE_LINK_STATE_L0S) + if (get_aspm_enable(parent) & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; link->latency_up.l0s = calc_l0s_latency(parent); link->latency_dw.l0s = calc_l0s_latency(child); @@ -572,7 +555,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (aspm_support(parent) & aspm_support(child) & PCIE_LINK_STATE_L1) link->aspm_support |= ASPM_STATE_L1; - if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) + if (get_aspm_enable(parent) & get_aspm_enable(child) + & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; link->latency_up.l1 = calc_l1_latency(parent); link->latency_dw.l1 = calc_l1_latency(child); From patchwork Thu Sep 24 14:24:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. 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[84.2.198.93]) by smtp.gmail.com with ESMTPSA id i7sm2641735ejo.22.2020.09.24.08.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2020 08:24:19 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , linux-pci@vger.kernel.org Subject: [PATCH v2 7/7] PCI/ASPM: Remove struct pcie_link_state.l1ss Date: Thu, 24 Sep 2020 16:24:43 +0200 Message-Id: <20200924142443.260861-8-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200924142443.260861-1-refactormyself@gmail.com> References: <20200924142443.260861-1-refactormyself@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pcie_link_state.l1ss.{up_cap_ptr, dw_cap_ptr} are used to cache the value of l1ss_cap_ptr for upstream and downstream respectively. This value can now be obtained directly from struct pci_dev, it is no longer useful to cache it. So, aspm_calc_l1ss_info() will only be computing the values for ctl1 and ctl2. The addresses of these can also be passed in. Then if aspm_calc_l1ss_info() calculates pcie_link_state.l1ss.{ctl1, ctl2} which are only used inside pcie_config_aspm_l1ss(). Calling the function where it is needed will remove the need to cache the values in the struct. - Move call to aspm_calc_l1ss_info() from pcie_aspm_cap_init() to pcie_config_aspm_l1ss(). - Rename aspm_calc_l1ss_info() to aspm_calc_l1ss_ctl_values(). - Rework the function to take a pci_dev and pointers to ctl1 and ctl2. - Change calls to aspm_calc_l1ss_info() into new function. - Replace l1ss.{up,dw}_cap_ptr with pci_dev->l1ss_cap_ptr - Replace pcie_link_state.l1ss.{ctl1, ctl2} with local variables. - No more reference to struct pcie_link_state.l1ss, so remove it. - Remove pcie_link_state.l1ss Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 45 ++++++++++++++--------------------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index f4fc2d65240c..b9bacdef8c80 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -74,14 +74,6 @@ struct pcie_link_state { * has one slot under it, so at most there are 8 functions. */ struct aspm_latency acceptable[8]; - - /* L1 PM Substate info */ - struct { - u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */ - u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */ - u32 ctl1; /* value to be programmed in ctl1 */ - u32 ctl2; /* value to be programmed in ctl2 */ - } l1ss; }; static int aspm_disabled, aspm_force; @@ -444,17 +436,15 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) } /* Calculate L1.2 PM substate timing parameters */ -static void aspm_calc_l1ss_info(struct pcie_link_state *link) +static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev, + u32 *ctl1, u32 *ctl2) { + struct pcie_link_state *link = pdev->link_state; u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; struct pci_dev *dw_pdev = link->downstream; struct pci_dev *up_pdev = link->pdev; - link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr; - link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr; - link->l1ss.ctl1 = link->l1ss.ctl2 = 0; - if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; @@ -471,10 +461,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link) if (calc_l1ss_pwron(up_pdev, scale1, val1) > calc_l1ss_pwron(dw_pdev, scale2, val2)) { - link->l1ss.ctl2 |= scale1 | (val1 << 3); + *ctl2 |= scale1 | (val1 << 3); t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1); } else { - link->l1ss.ctl2 |= scale2 | (val2 << 3); + *ctl2 |= scale2 | (val2 << 3); t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2); } @@ -490,7 +480,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link) */ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; encode_l12_threshold(l1_2_threshold, &scale, &value); - link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; + *ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } static void aspm_support(struct pci_dev *pdev) @@ -580,9 +570,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; - if (link->aspm_support & ASPM_STATE_L1SS) - aspm_calc_l1ss_info(link); - /* Save default state */ link->aspm_default = link->aspm_enabled; @@ -625,12 +612,13 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, /* Configure the ASPM L1 substates */ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) { - u32 val, enable_req; + u32 val, enable_req, ctl1, ctl2; struct pci_dev *child = link->downstream, *parent = link->pdev; - u32 up_cap_ptr = link->l1ss.up_cap_ptr; - u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; + int up_cap_ptr = parent->l1ss_cap_ptr; + int dw_cap_ptr = child->l1ss_cap_ptr; enable_req = (link->aspm_enabled ^ state) & state; + aspm_calc_l1ss_ctl_values(parent, &ctl1, &ctl2); /* * Here are the rules specified in the PCIe spec for enabling L1SS: @@ -665,24 +653,21 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) /* Program T_POWER_ON times in both ports */ pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, - link->l1ss.ctl2); + ctl2); pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, - link->l1ss.ctl2); + ctl2); /* Program Common_Mode_Restore_Time in upstream device */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CTL1_CM_RESTORE_TIME, - link->l1ss.ctl1); + PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1); /* Program LTR_L1.2_THRESHOLD time in both ports */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); } val = 0;