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Fri, 25 Sep 2020 08:39:39 +0000 Date: Fri, 25 Sep 2020 16:37:49 +0800 From: Jisheng Zhang To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Ard Biesheuvel Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled Message-ID: <20200925163749.4a45b8fa@xhacker.debian> In-Reply-To: <20200925163435.680b8e08@xhacker.debian> References: <20200925163435.680b8e08@xhacker.debian> X-Mailer: Claws Mail 3.17.6 (GTK+ 2.24.32; x86_64-pc-linux-gnu) X-ClientProxiedBy: TY2PR0101CA0019.apcprd01.prod.exchangelabs.com (2603:1096:404:92::31) To DM6PR03MB4555.namprd03.prod.outlook.com (2603:10b6:5:102::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from xhacker.debian (124.74.246.114) by TY2PR0101CA0019.apcprd01.prod.exchangelabs.com (2603:1096:404:92::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3412.22 via Frontend Transport; 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Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domainshierarchical API") Signed-off-by: Jisheng Zhang Acked-by: Gustavo Pimentel Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9dafecba347f..f08f4d97f321 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -632,7 +632,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - if (!pp->ops->msi_host_init) { + if (pci_msi_enabled() && !pp->ops->msi_host_init) { num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; /* Initialize IRQ Status array */ From patchwork Fri Sep 25 08:38:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 11799355 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1DCBC1580 for ; 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X-MS-Exchange-AntiSpam-MessageData: 8yGvGSXP82zl+b9EMjESAOnREhzKkiGekF+8g18A1WwRrTjIJnR2mU8c2FZzgcJVuTGx943l2pVLU4oqD1J90vl6aCn0OF1OmDgXoLXXCs5G0ipA7hRQWA4HaEuCh/pxu4VWTvLL2KLdDCh9EqtkSWtQz+6aH4yCx7m8Jub8Ykq364BwKfOSXiibwZRHs1ytPdrZMVnsCbuJloiH+49PPWA732RiIZ68dZ+FULz6B0dDfrQ5/QkXK5tt3Usqk8a/7SqRzXxcRBPMKxA7RaQ7yzofKe+VEMsbQCcVJCb9FDWvX79LrD5LHTwRZdEyMOR54b4sMkZTGaMZITcZhL5VZUFJOZKGHLQW46jKS96OJKVZ7CFYbrfXv7eWWhB7u7p+zIj+pmDV2w0UYyCRUo+aYo4KHVFM9eS9C9jGjtSwdVQnvuEIR1RrKID+i5Kb97Q9UtjZvAvOI9hwpPV+OUfb9+TRuoq1iYXTbf0IDrGodpWqgemHCpHy4AumIzcNg00IiSK0o8sqnE4drt/hlG/CzmRZu1fWQ0hnnwlNvjgSrZji4y3k8X6QqsGnDa5qbWCNVzfReRT63oDR8H8g5BEcvODatFEpgrwLgY7P2LVeWICjd2w8c7XqOECnoePYsLlm37cERvDba17MlxHyKoaQTA== X-OriginatorOrg: synaptics.com X-MS-Exchange-CrossTenant-Network-Message-Id: d899aaac-10ea-471f-760f-08d8612e8d57 X-MS-Exchange-CrossTenant-AuthSource: DM6PR03MB4555.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2020 08:39:44.2173 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335d1fbc-2124-4173-9863-17e7051a2a0e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LQUVVk7EhNSbkhnejhnAmEU4O8ZimAvv0UjGszjl2JeidZlWglviMBnnElK54rZ38cIltvIIWd8CZAVBfBJSCA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB4697 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There's no need to allocate a page for the MSI address, we could use an address in the driver data. One side effect of this patch is fixing the MSI page leakage during suspend/resume. Take the pcie-tegra194.c for example, it calls dw_pcie_msi_init() in resume path, thus the previous MSI page is leaked. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Suggested-by: Rob Herring Signed-off-by: Jisheng Zhang Reviewed-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 22 ++----------------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 2 files changed, 2 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f08f4d97f321..bf25d783b5c5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -126,9 +126,7 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - u64 msi_target; - - msi_target = (u64)pp->msi_data; + u64 msi_target = virt_to_phys(&pp->msi_data); msg->address_lo = lower_32_bits(msi_target); msg->address_hi = upper_32_bits(msi_target); @@ -287,27 +285,11 @@ void dw_pcie_free_msi(struct pcie_port *pp) irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); - - if (pp->msi_page) - __free_page(pp->msi_page); } void dw_pcie_msi_init(struct pcie_port *pp) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct device *dev = pci->dev; - u64 msi_target; - - pp->msi_page = alloc_page(GFP_KERNEL); - pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE, - DMA_FROM_DEVICE); - if (dma_mapping_error(dev, pp->msi_data)) { - dev_err(dev, "Failed to map MSI data\n"); - __free_page(pp->msi_page); - pp->msi_page = NULL; - return; - } - msi_target = (u64)pp->msi_data; + u64 msi_target = virt_to_phys(&pp->msi_data); /* Program the msi_data */ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index f911760dcc69..a88e15a09745 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -195,7 +195,6 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; - struct page *msi_page; struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS];