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Wed, 30 Sep 2020 20:21:09 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Wed, 30 Sep 2020 20:21:08 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 08UIL8q4009881; Wed, 30 Sep 2020 20:21:08 +0200 Received: (from nadeem@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 08UIL7NJ009880; Wed, 30 Sep 2020 20:21:07 +0200 From: Nadeem Athani To: , , , , , , CC: , , Subject: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 training defect. Date: Wed, 30 Sep 2020 20:21:05 +0200 Message-ID: <20200930182105.9752-1-nadeem@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2c017722-0edf-4d57-483c-08d8656d9cab X-MS-TrafficTypeDiagnostic: MWHPR07MB3581: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2449; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oBGPfcWRlqPltegnFweTLSWmv5eQl+F662dH7taIEiaD4vS19v8TFrM5/eMtSHlZXcQKYsfMbJw+/oqsdD1PHeoKg33NHDsdCWRH+JloiEbdQ470C+js/Cl2pm5mxVLShFPlDCEj6aKsR5W3R92k0utMqefNjgn4KA+f3yu7Xg0x0D5WVXwvMjECGDH9uQTp2Z7xdfs6PnOmJJ9NLbfsgTPf9af264hmo5deTWXjtIKs+2REAYMTejlNwMdCTNB5bFG1pByRN0JbBboEU/KFE6UgyItCFaCtauiSQEo4KPxjqjbQh8TpSy8hGYK/WPQU2Z6g7/JA+Wh9Gb2t7yhzwUnMgp1a2lI3wpW+vxGkODrK1ZK2cUVdwL+5IoC1Z2VjoYg0853k5Ihfj4fAXj3VEO80eSPeYZ6K6wEqkcRZw815HKP8HTSQ8NVUXSOgGd7tAMKrVLG13b1DjGHLaLrdHC5rideq16yoO9eE4IRsAts= X-Forefront-Antispam-Report: CIP:199.43.4.23;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:rmmaillnx1.cadence.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(39860400002)(396003)(136003)(346002)(376002)(36092001)(46966005)(8936002)(2906002)(6636002)(336012)(107886003)(47076004)(82740400003)(81166007)(356005)(478600001)(1076003)(186003)(26005)(2616005)(83380400001)(426003)(82310400003)(36756003)(5660300002)(86362001)(4326008)(316002)(42186006)(8676002)(70206006)(54906003)(110136005)(70586007)(36906005);DIR:OUT;SFP:1101; X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2020 18:21:12.5007 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c017722-0edf-4d57-483c-08d8656d9cab X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9;Ip=[199.43.4.23];Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM12FT052.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR07MB3581 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-30_09:2020-09-30,2020-09-30 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 bulkscore=0 adultscore=0 priorityscore=1501 clxscore=1015 spamscore=0 phishscore=0 malwarescore=0 mlxscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009300146 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Signed-off-by: Nadeem Athani --- Changes in v3: - To set retrain link bit,checking device capability & link status. - 32bit read in place of 8bit. - Minor correction in patch comment. - Change in variable & macro name. Changes in v2: - 16bit read in place of 8bit. drivers/pci/controller/cadence/pcie-cadence-host.c | 31 ++++++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 9 ++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 4550e0d469ca..2b2ae4e18032 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = { .write = pci_generic_config_write, }; +static void cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + + if (!cdns_pcie_link_up(pcie)) + return; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) + return; + + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl = cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |= PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + if (!cdns_pcie_link_up(pcie)) + return; + } +} static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { @@ -115,6 +145,7 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + cdns_pcie_retrain(pcie); return 0; } diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index feed1e3038f4..5f1cf032ae15 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -119,7 +119,7 @@ * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE 0x00200000 - +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 /* * Address Translation Registers @@ -413,6 +413,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, cdns_pcie_write_sz(addr, 0x2, value); } +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value)