From patchwork Mon Oct 12 23:29:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C167139F for ; Tue, 13 Oct 2020 00:59:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 359A6218AC for ; Tue, 13 Oct 2020 00:59:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 359A6218AC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=getutm.app Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:60162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kS8ej-0004Kn-9j for patchwork-qemu-devel@patchwork.kernel.org; Mon, 12 Oct 2020 20:59:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kS7Gd-0001mc-Bx; Mon, 12 Oct 2020 19:30:11 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:35038) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kS7GB-00060t-WA; Mon, 12 Oct 2020 19:30:11 -0400 Received: by mail-pg1-f194.google.com with SMTP id g29so16026524pgl.2; Mon, 12 Oct 2020 16:29:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8NpxZ4sG3TMSoSeEr8UVCiKc9XMWaUFFs7rNquz3/8U=; b=UnQmZ5t2FyYKZRckwNTMS47ZB2dOC5ABZoqM/mECeozVOePqf2TlzZpLieUZMPCpGH R2+TMdEpkD2eKojLMsw8wcVNOSP+mfjaoG5LXXrCCebPWv82KtDBTYG0quVv+QMf0xzP v99NuyJYj38tHebGbRTl+BVSS/sgrNuW3UfbmaFS88gVg5q/aKYrel8o7sWwResymTvX 2x+PZBJhfsBo5HdT1pBvSVMUciSLJvsIcdiqeDw0ZgDLCn1kn+ia8adn0G4Lx7eBFWgP xIUQtkt8/lsIcbiW2MMS08/N0+gPd0fnVaJuZTRx9wK1RgguHa2rAbAjAdgX3ruK0qmo ySoA== X-Gm-Message-State: AOAM533s5kqOCEyne5XrKqhJNaqBHfQ5vIyr1Ewjd4yIH7TaQtoRQhbg pw6+dNPZRCz+zaxsGkiUMbRNxxunxsE= X-Google-Smtp-Source: ABdhPJz2ImXbIL67Up/8Ki1mhu+FKxK2zseyNUdIb15khotMyPuO89jTXcQiSFeFyibcu6KB1vBcOA== X-Received: by 2002:a63:370f:: with SMTP id e15mr13713559pga.124.1602545382283; Mon, 12 Oct 2020 16:29:42 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.41 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:41 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 01/10] configure: option to disable host block devices Date: Mon, 12 Oct 2020 16:29:30 -0700 Message-Id: <20201012232939.48481-2-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.194; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f194.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Joelle van Dyne , "open list:raw" , Max Reitz Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy Some hosts (iOS) have a sandboxed filesystem and do not provide low-level APIs for interfacing with host block devices. Signed-off-by: Joelle van Dyne --- block/file-posix.c | 8 +++++++- configure | 4 ++++ meson.build | 1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/block/file-posix.c b/block/file-posix.c index c63926d592..52f7c20525 100644 --- a/block/file-posix.c +++ b/block/file-posix.c @@ -41,7 +41,7 @@ #include "scsi/pr-manager.h" #include "scsi/constants.h" -#if defined(__APPLE__) && (__MACH__) +#if defined(CONFIG_HOST_BLOCK_DEVICE) && defined(__APPLE__) && (__MACH__) #include #include #include @@ -3247,6 +3247,8 @@ BlockDriver bdrv_file = { /***********************************************/ /* host device */ +#if defined(CONFIG_HOST_BLOCK_DEVICE) + #if defined(__APPLE__) && defined(__MACH__) static kern_return_t GetBSDPath(io_iterator_t mediaIterator, char *bsdPath, CFIndex maxPathSize, int flags); @@ -3872,6 +3874,8 @@ static BlockDriver bdrv_host_cdrom = { }; #endif /* __FreeBSD__ */ +#endif /* CONFIG_HOST_BLOCK_DEVICE */ + static void bdrv_file_init(void) { /* @@ -3879,6 +3883,7 @@ static void bdrv_file_init(void) * registered last will get probed first. */ bdrv_register(&bdrv_file); +#if defined(CONFIG_HOST_BLOCK_DEVICE) bdrv_register(&bdrv_host_device); #ifdef __linux__ bdrv_register(&bdrv_host_cdrom); @@ -3886,6 +3891,7 @@ static void bdrv_file_init(void) #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) bdrv_register(&bdrv_host_cdrom); #endif +#endif /* CONFIG_HOST_BLOCK_DEVICE */ } block_init(bdrv_file_init); diff --git a/configure b/configure index b553288c5e..3c63879750 100755 --- a/configure +++ b/configure @@ -446,6 +446,7 @@ meson="" ninja="" skip_meson=no gettext="" +host_block_device_support="yes" bogus_os="no" malloc_trim="auto" @@ -6098,6 +6099,9 @@ if test "$default_devices" = "yes" ; then else echo "CONFIG_MINIKCONF_MODE=--allnoconfig" >> $config_host_mak fi +if test "$host_block_device_support" = "yes" ; then + echo "CONFIG_HOST_BLOCK_DEVICE=y" >> $config_host_mak +fi if test "$debug_tcg" = "yes" ; then echo "CONFIG_DEBUG_TCG=y" >> $config_host_mak fi diff --git a/meson.build b/meson.build index 17c89c87c6..5d3a47784b 100644 --- a/meson.build +++ b/meson.build @@ -1947,6 +1947,7 @@ summary_info += {'vvfat support': config_host.has_key('CONFIG_VVFAT')} summary_info += {'qed support': config_host.has_key('CONFIG_QED')} summary_info += {'parallels support': config_host.has_key('CONFIG_PARALLELS')} summary_info += {'sheepdog support': config_host.has_key('CONFIG_SHEEPDOG')} +summary_info += {'host block dev support': config_host.has_key('CONFIG_HOST_BLOCK_DEVICE')} summary_info += {'capstone': capstone_opt == 'disabled' ? false : capstone_opt} summary_info += {'libpmem support': config_host.has_key('CONFIG_LIBPMEM')} summary_info += {'libdaxctl support': config_host.has_key('CONFIG_LIBDAXCTL')} From patchwork Mon Oct 12 23:29:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A5B61592 for ; Tue, 13 Oct 2020 01:04:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DAFC820870 for ; Tue, 13 Oct 2020 01:04:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DAFC820870 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=getutm.app Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:41404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kS8jS-00005H-09 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 12 Oct 2020 21:04:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kS7Gd-0001md-Bh for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:11 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:36937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kS7GC-00060x-Kf for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:11 -0400 Received: by mail-pg1-f196.google.com with SMTP id h6so15997551pgk.4 for ; Mon, 12 Oct 2020 16:29:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eIy9eojQ+A3Gbcofa/FLlYhzE10ebVrgvbdbxHUT22Q=; b=X5hX1vOf33Z27/I9kuGjY21+o2M8188oRd5DWE/gwdL5e/JEZFNBfX8A4gRLf2I8ai 6Ji941rbZbL2YKJ4We9QjKXjO7n6qNckUAO2jkqKExmaDVcJ/pn7rJM/mscM4v07JDd0 pTf+JTsyJELwL0ztdxKPWnUTGDwGC39T8yVYb9c8x7CA5iSUpjc6LprNY4JCahQhp7fr MZQ7LGNDcSL5Q/4pNNaAP8L44HCJYl6NEmYceSAn2WZ/A5RHKihrY6h1VjvWkWcQgde0 2k27LMyWm0J54fiNpXaSTzVssviXNj3vitcmXXOF6cIWBVkUfTKyQ2UYVamuzWaaGDP7 K7Tw== X-Gm-Message-State: AOAM530BfyXQsvVf1TgTgbpMbNwtlDBrofy6sldqT1hWsj8gIn/c6Pdj 3nGQQwYGsND4Gkq3v8JXwilCz9xFfJg= X-Google-Smtp-Source: ABdhPJwxtrbn7XnIFTlIVFzSGROUJA5QKE2FIv30edAU/w28J6yiaEZ9emmdF6b4ZgE9g9woUkJl/Q== X-Received: by 2002:a17:90a:c68d:: with SMTP id n13mr22236747pjt.94.1602545383213; Mon, 12 Oct 2020 16:29:43 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:42 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 02/10] configure: cross-compiling without cross_prefix Date: Mon, 12 Oct 2020 16:29:31 -0700 Message-Id: <20201012232939.48481-3-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.196; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f196.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:43 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy The iOS toolchain does not use the host prefix naming convention. We add a new option `--enable-cross-compile` that forces cross-compile even without a cross_prefix. Signed-off-by: Joelle van Dyne --- configure | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 3c63879750..46d5db63e8 100755 --- a/configure +++ b/configure @@ -234,6 +234,7 @@ cpu="" iasl="iasl" interp_prefix="/usr/gnemul/qemu-%M" static="no" +cross_compile="no" cross_prefix="" audio_drv_list="" block_drv_rw_whitelist="" @@ -456,6 +457,11 @@ for opt do optarg=$(expr "x$opt" : 'x[^=]*=\(.*\)') case "$opt" in --cross-prefix=*) cross_prefix="$optarg" + cross_compile="yes" + ;; + --enable-cross-compile) cross_compile="yes" + ;; + --disable-cross-compile) cross_compile="no" ;; --cc=*) CC="$optarg" ;; @@ -878,6 +884,10 @@ for opt do ;; --cross-prefix=*) ;; + --enable-cross-compile) + ;; + --disable-cross-compile) + ;; --cc=*) ;; --host-cc=*) host_cc="$optarg" @@ -1687,6 +1697,7 @@ Advanced options (experts only): --efi-aarch64=PATH PATH of efi file to use for aarch64 VMs. --with-suffix=SUFFIX suffix for QEMU data inside datadir/libdir/sysconfdir/docdir [$qemu_suffix] --with-pkgversion=VERS use specified string as sub-version of the package + --enable-cross-compile enable cross compiling (set automatically if $cross_prefix is set) --enable-debug enable common debug build options --enable-sanitizers enable default sanitizers --enable-tsan enable thread sanitizer @@ -7164,7 +7175,7 @@ if has $sdl2_config; then fi echo "strip = [$(meson_quote $strip)]" >> $cross echo "windres = [$(meson_quote $windres)]" >> $cross -if test -n "$cross_prefix"; then +if test "$cross_compile" = "yes"; then cross_arg="--cross-file config-meson.cross" echo "[host_machine]" >> $cross if test "$mingw32" = "yes" ; then From patchwork Mon Oct 12 23:29:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834657 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E62C139F for ; Tue, 13 Oct 2020 00:59:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1DDED218AC for ; Tue, 13 Oct 2020 00:59:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1DDED218AC Authentication-Results: mail.kernel.org; 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Mon, 12 Oct 2020 16:29:44 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 03/10] qemu: add support for iOS host Date: Mon, 12 Oct 2020 16:29:32 -0700 Message-Id: <20201012232939.48481-4-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.195; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f195.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:45 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Peter Maydell , Thomas Huth , Marek Vasut , "open list:Block layer core" , Jason Wang , Chris Wulff , Richard Henderson , Michael Roth , Max Reitz , "open list:ARM TCG CPUs" , Joelle van Dyne , Paolo Bonzini , Samuel Thibault , Laurent Vivier Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy This introduces support for building for iOS hosts. When the correct Xcode toolchain is used, iOS host will be detected automatically. block: disable features not supported by iOS sandbox slirp: disable SMB features for iOS target: disable system() calls for iOS tcg: use sys_icache_invalidate() instead of GCC builtin for iOS tests: disable tests on iOS which uses system() Signed-off-by: Joelle van Dyne --- block.c | 2 +- block/file-posix.c | 30 ++++++++++++++++----------- configure | 43 ++++++++++++++++++++++++++++++++++++++- meson.build | 2 +- net/slirp.c | 16 +++++++-------- qga/commands-posix.c | 6 ++++++ target/arm/arm-semi.c | 2 ++ target/m68k/m68k-semi.c | 2 ++ target/nios2/nios2-semi.c | 2 ++ tcg/aarch64/tcg-target.h | 10 +++++++++ tests/qtest/meson.build | 7 +++---- 11 files changed, 95 insertions(+), 27 deletions(-) diff --git a/block.c b/block.c index 430edf79bb..5d49869d02 100644 --- a/block.c +++ b/block.c @@ -53,7 +53,7 @@ #ifdef CONFIG_BSD #include #include -#ifndef __DragonFly__ +#if !defined(__DragonFly__) && !defined(CONFIG_IOS) #include #endif #endif diff --git a/block/file-posix.c b/block/file-posix.c index 52f7c20525..cdc73b5f1d 100644 --- a/block/file-posix.c +++ b/block/file-posix.c @@ -181,7 +181,16 @@ typedef struct BDRVRawReopenState { bool check_cache_dropped; } BDRVRawReopenState; -static int fd_open(BlockDriverState *bs); +static int fd_open(BlockDriverState *bs) +{ + BDRVRawState *s = bs->opaque; + + /* this is just to ensure s->fd is sane (its called by io ops) */ + if (s->fd >= 0) + return 0; + return -EIO; +} + static int64_t raw_getlength(BlockDriverState *bs); typedef struct RawPosixAIOData { @@ -252,6 +261,12 @@ static int raw_normalize_devicepath(const char **filename, Error **errp) } #endif +#if defined(CONFIG_IOS) +static int probe_logical_blocksize(int fd, unsigned int *sector_size_p) +{ + return -ENOTSUP; /* not supported on iOS */ +} +#else /* CONFIG_IOS */ /* * Get logical block size via ioctl. On success store it in @sector_size_p. */ @@ -284,6 +299,7 @@ static int probe_logical_blocksize(int fd, unsigned int *sector_size_p) return success ? 0 : -errno; } +#endif /* !CONFIG_IOS */ /** * Get physical block size of @fd. @@ -2306,7 +2322,7 @@ again: } if (size == 0) #endif -#if defined(__APPLE__) && defined(__MACH__) +#if !defined(CONFIG_IOS) && defined(__APPLE__) && defined(__MACH__) { uint64_t sectors = 0; uint32_t sector_size = 0; @@ -3541,16 +3557,6 @@ hdev_co_ioctl(BlockDriverState *bs, unsigned long int req, void *buf) } #endif /* linux */ -static int fd_open(BlockDriverState *bs) -{ - BDRVRawState *s = bs->opaque; - - /* this is just to ensure s->fd is sane (its called by io ops) */ - if (s->fd >= 0) - return 0; - return -EIO; -} - static coroutine_fn int hdev_co_pdiscard(BlockDriverState *bs, int64_t offset, int bytes) { diff --git a/configure b/configure index 46d5db63e8..c474d7c221 100755 --- a/configure +++ b/configure @@ -561,6 +561,19 @@ EOF compile_object } +check_ios() { + cat > $TMPC < $TMPC < @@ -603,7 +616,11 @@ elif check_define __DragonFly__ ; then elif check_define __NetBSD__; then targetos='NetBSD' elif check_define __APPLE__; then - targetos='Darwin' + if check_ios ; then + targetos='iOS' + else + targetos='Darwin' + fi else # This is a fatal error, but don't report it yet, because we # might be going to just print the --help text, or it might @@ -780,6 +797,22 @@ Darwin) # won't work when we're compiling with gcc as a C compiler. QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" ;; +iOS) + bsd="yes" + darwin="yes" + ios="yes" + if [ "$cpu" = "x86_64" ] ; then + QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS" + QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS" + fi + host_block_device_support="no" + audio_drv_list="" + audio_possible_drivers="" + QEMU_LDFLAGS="-framework CoreFoundation $QEMU_LDFLAGS" + # Disable attempts to use ObjectiveC features in os/object.h since they + # won't work when we're compiling with gcc as a C compiler. + QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" +;; SunOS) solaris="yes" make="${MAKE-gmake}" @@ -6162,6 +6195,10 @@ if test "$darwin" = "yes" ; then echo "CONFIG_DARWIN=y" >> $config_host_mak fi +if test "$ios" = "yes" ; then + echo "CONFIG_IOS=y" >> $config_host_mak +fi + if test "$solaris" = "yes" ; then echo "CONFIG_SOLARIS=y" >> $config_host_mak fi @@ -7166,6 +7203,7 @@ echo "cpp_link_args = [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross echo "[binaries]" >> $cross echo "c = [$(meson_quote $cc)]" >> $cross test -n "$cxx" && echo "cpp = [$(meson_quote $cxx)]" >> $cross +test -n "$objcc" && echo "objc = [$(meson_quote $objcc)]" >> $cross echo "ar = [$(meson_quote $ar)]" >> $cross echo "nm = [$(meson_quote $nm)]" >> $cross echo "pkgconfig = [$(meson_quote $pkg_config_exe)]" >> $cross @@ -7184,6 +7222,9 @@ if test "$cross_compile" = "yes"; then if test "$linux" = "yes" ; then echo "system = 'linux'" >> $cross fi + if test "$darwin" = "yes" ; then + echo "system = 'darwin'" >> $cross + fi case "$ARCH" in i386|x86_64) echo "cpu_family = 'x86'" >> $cross diff --git a/meson.build b/meson.build index 5d3a47784b..69a3c00cce 100644 --- a/meson.build +++ b/meson.build @@ -140,7 +140,7 @@ if targetos == 'windows' include_directories: include_directories('.')) elif targetos == 'darwin' coref = dependency('appleframeworks', modules: 'CoreFoundation') - iokit = dependency('appleframeworks', modules: 'IOKit') + iokit = dependency('appleframeworks', modules: 'IOKit', required: 'CONFIG_IOS' not in config_host) cocoa = dependency('appleframeworks', modules: 'Cocoa', required: get_option('cocoa')) elif targetos == 'sunos' socket = [cc.find_library('socket'), diff --git a/net/slirp.c b/net/slirp.c index 77042e6df7..8413042c09 100644 --- a/net/slirp.c +++ b/net/slirp.c @@ -27,7 +27,7 @@ #include "net/slirp.h" -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) #include #include #endif @@ -90,7 +90,7 @@ typedef struct SlirpState { Slirp *slirp; Notifier poll_notifier; Notifier exit_notifier; -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) gchar *smb_dir; #endif GSList *fwd; @@ -103,7 +103,7 @@ static QTAILQ_HEAD(, SlirpState) slirp_stacks = static int slirp_hostfwd(SlirpState *s, const char *redir_str, Error **errp); static int slirp_guestfwd(SlirpState *s, const char *config_str, Error **errp); -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) static int slirp_smb(SlirpState *s, const char *exported_dir, struct in_addr vserver_addr, Error **errp); static void slirp_smb_cleanup(SlirpState *s); @@ -368,7 +368,7 @@ static int net_slirp_init(NetClientState *peer, const char *model, struct in6_addr ip6_prefix; struct in6_addr ip6_host; struct in6_addr ip6_dns; -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) struct in_addr smbsrv = { .s_addr = 0 }; #endif NetClientState *nc; @@ -478,7 +478,7 @@ static int net_slirp_init(NetClientState *peer, const char *model, return -1; } -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) if (vsmbserver && !inet_aton(vsmbserver, &smbsrv)) { error_setg(errp, "Failed to parse SMB address"); return -1; @@ -593,7 +593,7 @@ static int net_slirp_init(NetClientState *peer, const char *model, } } } -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) if (smb_export) { if (slirp_smb(s, smb_export, smbsrv, errp) < 0) { goto error; @@ -785,7 +785,7 @@ void hmp_hostfwd_add(Monitor *mon, const QDict *qdict) } -#ifndef _WIN32 +#if !defined(_WIN32) && !defined(CONFIG_IOS) /* automatic user mode samba server configuration */ static void slirp_smb_cleanup(SlirpState *s) @@ -900,7 +900,7 @@ static int slirp_smb(SlirpState* s, const char *exported_dir, return 0; } -#endif /* !defined(_WIN32) */ +#endif /* !defined(_WIN32) && !defined(CONFIG_IOS) */ static int guestfwd_can_read(void *opaque) { diff --git a/qga/commands-posix.c b/qga/commands-posix.c index 3bffee99d4..ebb63b2188 100644 --- a/qga/commands-posix.c +++ b/qga/commands-posix.c @@ -34,6 +34,12 @@ #ifndef CONFIG_HAS_ENVIRON #ifdef __APPLE__ +#include "TargetConditionals.h" +#if !TARGET_OS_IPHONE && !TARGET_IPHONE_SIMULATOR +#define APPLE_USE_CRT_EXTERNS +#endif +#endif +#ifdef APPLE_USE_CRT_EXTERNS #include #define environ (*_NSGetEnviron()) #else diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 8718fd0194..3704f19df6 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -891,6 +891,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) return clock() / (CLOCKS_PER_SEC / 100); case TARGET_SYS_TIME: return set_swi_errno(env, time(NULL)); +#if !defined(CONFIG_IOS) /* iOS does not have system() */ case TARGET_SYS_SYSTEM: GET_ARG(0); GET_ARG(1); @@ -907,6 +908,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) unlock_user(s, arg0, 0); return ret; } +#endif /* CONFIG_IOS */ case TARGET_SYS_ERRNO: return get_swi_errno(env); case TARGET_SYS_GET_CMDLINE: diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 8e5fbfc8fa..6b8941839e 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -402,6 +402,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) result = isatty(arg0); } break; +#if !defined(CONFIG_IOS) /* iOS does not have system() */ case HOSTED_SYSTEM: GET_ARG(0); GET_ARG(1); @@ -420,6 +421,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) } } break; +#endif /* CONFIG_IOS */ case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index d7a80dd303..bb029070d3 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -426,6 +426,7 @@ void do_nios2_semihosting(CPUNios2State *env) result = isatty(arg0); } break; +#if !defined(CONFIG_IOS) /* iOS does not have system() */ case HOSTED_SYSTEM: GET_ARG(0); GET_ARG(1); @@ -444,6 +445,7 @@ void do_nios2_semihosting(CPUNios2State *env) } } break; +#endif default: qemu_log_mask(LOG_GUEST_ERROR, "nios2-semihosting: unsupported " "semihosting syscall %d\n", nr); diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..a2b22b4305 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -148,9 +148,19 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#if defined(__APPLE__) +void sys_icache_invalidate(void *start, size_t len); +#endif + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { +#if defined(__APPLE__) + sys_icache_invalidate((char *)start, stop - start); +#elif defined(__GNUC__) __builtin___clear_cache((char *)start, (char *)stop); +#else +#error "Missing builtin to flush instruction cache" +#endif } void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 0f32ca0895..7184edcafa 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -46,12 +46,11 @@ qtests_i386 = \ (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-swtpm-test'] : []) + \ (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : []) + \ + (not config_host.has_key('CONFIG_IOS') ? ['bios-tables-test', 'hd-geo-test'] : []) + \ qtests_pci + \ ['fdc-test', 'ide-test', - 'hd-geo-test', 'boot-order-test', - 'bios-tables-test', 'rtc-test', 'i440fx-test', 'fw_cfg-test', @@ -141,9 +140,9 @@ qtests_arm = \ 'boot-serial-test', 'hexloader-test'] -# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional +# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional (except on iOS) qtests_aarch64 = \ - (cpu != 'arm' ? ['bios-tables-test'] : []) + \ + (cpu != 'arm' and not config_host.has_key('CONFIG_IOS') ? ['bios-tables-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ ['arm-cpu-features', From patchwork Mon Oct 12 23:29:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834665 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63E3316BC for ; Tue, 13 Oct 2020 01:04:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34CAE20870 for ; Tue, 13 Oct 2020 01:04:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 34CAE20870 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=getutm.app Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:41212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kS8jP-0008SI-6I for patchwork-qemu-devel@patchwork.kernel.org; Mon, 12 Oct 2020 21:03:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kS7Ge-0001nB-HS for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:12 -0400 Received: from mail-pl1-f176.google.com ([209.85.214.176]:47035) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kS7GF-00061C-R3 for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:12 -0400 Received: by mail-pl1-f176.google.com with SMTP id d6so9582516plo.13 for ; Mon, 12 Oct 2020 16:29:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jWqVdHQoyHsP7HwjPTpZZR6nLfrh+meA4KPwnOVwA4A=; b=PexoPZIQRK1pApxZW71ehfKyJC1Pm1ObSy6qtzWay8xYf/Covr9ZGbvZEVeZgWd9xE CMZ9yUSUHHEi75EAzpSGo41b8nEdd5gwSB/b3R3ISJMHk5eDm1Yj5BmPJewmqkx/eY7h lcz/OKCQ+MSbF5pvSmnsQQYFaEOjuzglrzX46hbwKHRCLgGvgu4T3kX+I/GT4Z4Y3E4L G0A5rqN87Unvz8oMIIq4g8cqpoLTMap8fr40ZfFDgo2/6vIGpMU8gm3gonPrFSF9nHeJ qH/2UDLFIWaShSITsZmRMS5abjKgDBKJECkUaVELhistC+c//1lumpFddinqy6krLDBj Ccyw== X-Gm-Message-State: AOAM532oscPs6i/E0LxBpTkLhQsuaWPTbUSq4UAMYXXVmyAinyNnBA5Z WpfWtvAmFPy86/PRIHIVIek6tp8Gi7U= X-Google-Smtp-Source: ABdhPJyNlvrDxUlHnFuLqOCplO2HRMY0ntzafO0mrClEfmErE9yxDNnokualu35konH5QwYUPC2MOA== X-Received: by 2002:a17:902:b111:b029:d4:cf7c:2ff1 with SMTP id q17-20020a170902b111b02900d4cf7c2ff1mr11936452plr.59.1602545386298; Mon, 12 Oct 2020 16:29:46 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.45 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:45 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 04/10] meson: option to build as shared library Date: Mon, 12 Oct 2020 16:29:33 -0700 Message-Id: <20201012232939.48481-5-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.176; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f176.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:46 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy On iOS, we cannot fork() new processes, so the best way to load QEMU into an app is through a shared library. We add a new configure option `--enable-shared-lib` that will build the bulk of QEMU into a shared lib. The usual executables will then link to the library. Signed-off-by: Joelle van Dyne --- configure | 14 ++++++++++++-- meson.build | 40 ++++++++++++++++++++++++++++++++++------ meson_options.txt | 2 ++ 3 files changed, 48 insertions(+), 8 deletions(-) diff --git a/configure b/configure index c474d7c221..37b27d9e35 100755 --- a/configure +++ b/configure @@ -448,6 +448,7 @@ ninja="" skip_meson=no gettext="" host_block_device_support="yes" +shared_lib="false" bogus_os="no" malloc_trim="auto" @@ -1563,6 +1564,10 @@ for opt do ;; --disable-libdaxctl) libdaxctl=no ;; + --enable-shared-lib) shared_lib=true + ;; + --disable-shared-lib) shared_lib=false + ;; *) echo "ERROR: unknown option $opt" echo "Try '$0 --help' for more information" @@ -1770,6 +1775,7 @@ Advanced options (experts only): enable plugins via shared library loading --disable-containers don't use containers for cross-building --gdb=GDB-path gdb to use for gdbstub tests [$gdb_bin] + --enable-shared-lib build QEMU as a shared library Optional features, enabled with --enable-FEATURE and disabled with --disable-FEATURE, default is enabled if available: @@ -7211,7 +7217,11 @@ echo "ranlib = [$(meson_quote $ranlib)]" >> $cross if has $sdl2_config; then echo "sdl2-config = [$(meson_quote $sdl2_config)]" >> $cross fi -echo "strip = [$(meson_quote $strip)]" >> $cross +if test "$shared_lib" = "true"; then + echo "strip = [$(meson_quote $strip), '-x']" >> $cross +else + echo "strip = [$(meson_quote $strip)]" >> $cross +fi echo "windres = [$(meson_quote $windres)]" >> $cross if test "$cross_compile" = "yes"; then cross_arg="--cross-file config-meson.cross" @@ -7273,7 +7283,7 @@ NINJA=${ninja:-$PWD/ninjatool} $meson setup \ -Dcocoa=$cocoa -Dmpath=$mpath -Dsdl=$sdl -Dsdl_image=$sdl_image \ -Dvnc=$vnc -Dvnc_sasl=$vnc_sasl -Dvnc_jpeg=$vnc_jpeg -Dvnc_png=$vnc_png \ -Dgettext=$gettext -Dxkbcommon=$xkbcommon -Du2f=$u2f \ - -Dcapstone=$capstone -Dslirp=$slirp -Dfdt=$fdt \ + -Dcapstone=$capstone -Dslirp=$slirp -Dfdt=$fdt -Dshared-lib=$shared_lib \ $cross_arg \ "$PWD" "$source_path" diff --git a/meson.build b/meson.build index 69a3c00cce..32cf08619f 100644 --- a/meson.build +++ b/meson.build @@ -1565,14 +1565,31 @@ foreach target : target_dirs arch_srcs += target_specific.sources() arch_deps += target_specific.dependencies() - lib = static_library('qemu-' + target, + if get_option('shared-lib') + build_lib_args = { + 'target_type': 'shared_library', + 'install': true, + 'dependencies': arch_deps + deps, + 'link_language': link_language, + 'link_depends': [block_syms, qemu_syms], + 'link_args': link_args + cc.get_supported_link_arguments(['-Wl,-U,_qemu_main']) + } + else + build_lib_args = { + 'target_type': 'static_library', + 'install': false, + 'dependencies': arch_deps, + 'name_suffix': 'fa' + } + endif + + lib = build_target('qemu-' + target, sources: arch_srcs + genh, - dependencies: arch_deps, objects: objects, include_directories: target_inc, c_args: c_args, build_by_default: false, - name_suffix: 'fa') + kwargs: build_lib_args) if target.endswith('-softmmu') execs = [{ @@ -1606,17 +1623,27 @@ foreach target : target_dirs 'dependencies': [] }] endif + if get_option('shared-lib') + build_exe_args = { + 'link_with': lib, + 'link_args': link_args + cc.get_supported_link_arguments(['-Wl,--exclude-libs,ALL']) + } + else + build_exe_args = { + 'objects': lib.extract_all_objects(recursive: true), + 'link_args': link_args + } + endif foreach exe: execs emulators += {exe['name']: executable(exe['name'], exe['sources'], install: true, c_args: c_args, dependencies: arch_deps + deps + exe['dependencies'], - objects: lib.extract_all_objects(recursive: true), link_language: link_language, link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []), - link_args: link_args, - gui_app: exe['gui']) + gui_app: exe['gui'], + kwargs: build_exe_args) } if 'CONFIG_TRACE_SYSTEMTAP' in config_host @@ -1758,6 +1785,7 @@ endif summary_info += {'Doc directory': get_option('docdir')} summary_info += {'Build directory': meson.current_build_dir()} summary_info += {'Source path': meson.current_source_dir()} +summary_info += {'build shared lib': get_option('shared-lib')} summary_info += {'GIT binary': config_host['GIT']} summary_info += {'GIT submodules': config_host['GIT_SUBMODULES']} summary_info += {'C compiler': meson.get_compiler('c').cmd_array()[0]} diff --git a/meson_options.txt b/meson_options.txt index 1d3c94840a..bcecbd5e12 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -2,6 +2,8 @@ option('qemu_suffix', type : 'string', value: 'qemu', description: 'Suffix for QEMU data/modules/config directories (can be empty)') option('docdir', type : 'string', value : 'doc', description: 'Base directory for documentation installation (can be empty)') +option('shared-lib', type : 'boolean', value : false, + description: 'build QEMU as a shared library') option('gettext', type : 'boolean', value : true, description: 'Localization of the GTK+ user interface') From patchwork Mon Oct 12 23:29:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834669 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A380016BC for ; Tue, 13 Oct 2020 01:04:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7385820870 for ; Tue, 13 Oct 2020 01:04:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7385820870 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=getutm.app Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kS8jg-0000Ma-DC for patchwork-qemu-devel@patchwork.kernel.org; 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Mon, 12 Oct 2020 16:29:47 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:46 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 05/10] slirp: update for iOS resolv fix Date: Mon, 12 Oct 2020 16:29:34 -0700 Message-Id: <20201012232939.48481-6-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.174; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f174.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:47 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy We cannot access /etc/resolv.conf on iOS so libslirp is modified to use libresolv instead. Signed-off-by: Joelle van Dyne --- .gitmodules | 2 +- meson.build | 2 ++ slirp | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 2bdeeacef8..f23e859210 100644 --- a/.gitmodules +++ b/.gitmodules @@ -51,7 +51,7 @@ url = https://git.qemu.org/git/edk2.git [submodule "slirp"] path = slirp - url = https://git.qemu.org/git/libslirp.git + url = https://github.com/utmapp/libslirp.git [submodule "roms/opensbi"] path = roms/opensbi url = https://git.qemu.org/git/opensbi.git diff --git a/meson.build b/meson.build index 32cf08619f..da96e296e0 100644 --- a/meson.build +++ b/meson.build @@ -996,6 +996,8 @@ if have_system slirp_deps = [] if targetos == 'windows' slirp_deps = cc.find_library('iphlpapi') + elif targetos == 'darwin' + slirp_deps = cc.find_library('resolv') endif slirp_conf = configuration_data() slirp_conf.set('SLIRP_MAJOR_VERSION', meson.project_version().split('.')[0]) diff --git a/slirp b/slirp index ce94eba204..452c389d82 160000 --- a/slirp +++ b/slirp @@ -1 +1 @@ -Subproject commit ce94eba2042d52a0ba3d9e252ebce86715e94275 +Subproject commit 452c389d8288f81ec9d59d983a047d4e54f3194e From patchwork Mon Oct 12 23:29:35 2020 Content-Type: text/plain; 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Mon, 12 Oct 2020 16:29:48 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:48 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 06/10] coroutine: add libucontext as external library Date: Mon, 12 Oct 2020 16:29:35 -0700 Message-Id: <20201012232939.48481-7-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.196; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f196.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:49 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Joelle van Dyne , Stefan Hajnoczi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy iOS does not support ucontext natively for aarch64 and the sigaltstack is also unsupported (even worse, it fails silently, see: https://openradar.appspot.com/13002712 ) As a workaround we include a library implementation of ucontext and add it as a build option. Signed-off-by: Joelle van Dyne --- .gitmodules | 3 +++ configure | 23 ++++++++++++++++++++--- libucontext | 1 + meson.build | 29 ++++++++++++++++++++++++++++- meson_options.txt | 2 ++ util/coroutine-ucontext.c | 9 +++++++++ 6 files changed, 63 insertions(+), 4 deletions(-) create mode 160000 libucontext diff --git a/.gitmodules b/.gitmodules index f23e859210..f5a1dc3c5a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -64,3 +64,6 @@ [submodule "roms/vbootrom"] path = roms/vbootrom url = https://git.qemu.org/git/vbootrom.git +[submodule "libucontext"] + path = libucontext + url = https://github.com/utmapp/libucontext.git diff --git a/configure b/configure index 37b27d9e35..16c66b437c 100755 --- a/configure +++ b/configure @@ -1761,7 +1761,7 @@ Advanced options (experts only): --oss-lib path to OSS library --cpu=CPU Build for host CPU [$cpu] --with-coroutine=BACKEND coroutine backend. Supported options: - ucontext, sigaltstack, windows + ucontext, libucontext, sigaltstack, windows --enable-gcov enable test coverage analysis with gcov --disable-blobs disable installing provided firmware blobs --with-vss-sdk=SDK-path enable Windows VSS support in QEMU Guest Agent @@ -5064,6 +5064,8 @@ if test "$coroutine" = ""; then coroutine=win32 elif test "$ucontext_works" = "yes"; then coroutine=ucontext + elif test "$ios" = "yes"; then + coroutine=libucontext else coroutine=sigaltstack fi @@ -5087,12 +5089,27 @@ else error_exit "only the 'windows' coroutine backend is valid for Windows" fi ;; + libucontext) + ;; *) error_exit "unknown coroutine backend $coroutine" ;; esac fi +case $coroutine in +libucontext) + git_submodules="${git_submodules} libucontext" + mkdir -p libucontext + coroutine_impl=ucontext + libucontext="enabled" + ;; +*) + coroutine_impl=$coroutine + libucontext="disabled" + ;; +esac + if test "$coroutine_pool" = ""; then coroutine_pool=yes fi @@ -6682,7 +6699,7 @@ if test "$rbd" = "yes" ; then echo "RBD_LIBS=$rbd_libs" >> $config_host_mak fi -echo "CONFIG_COROUTINE_BACKEND=$coroutine" >> $config_host_mak +echo "CONFIG_COROUTINE_BACKEND=$coroutine_impl" >> $config_host_mak if test "$coroutine_pool" = "yes" ; then echo "CONFIG_COROUTINE_POOL=1" >> $config_host_mak else @@ -7282,7 +7299,7 @@ NINJA=${ninja:-$PWD/ninjatool} $meson setup \ -Dxen=$xen -Dxen_pci_passthrough=$xen_pci_passthrough -Dtcg=$tcg \ -Dcocoa=$cocoa -Dmpath=$mpath -Dsdl=$sdl -Dsdl_image=$sdl_image \ -Dvnc=$vnc -Dvnc_sasl=$vnc_sasl -Dvnc_jpeg=$vnc_jpeg -Dvnc_png=$vnc_png \ - -Dgettext=$gettext -Dxkbcommon=$xkbcommon -Du2f=$u2f \ + -Dgettext=$gettext -Dxkbcommon=$xkbcommon -Du2f=$u2f -Ducontext=$libucontext \ -Dcapstone=$capstone -Dslirp=$slirp -Dfdt=$fdt -Dshared-lib=$shared_lib \ $cross_arg \ "$PWD" "$source_path" diff --git a/libucontext b/libucontext new file mode 160000 index 0000000000..7094e4c427 --- /dev/null +++ b/libucontext @@ -0,0 +1 @@ +Subproject commit 7094e4c42723b6178a4e2b60d4631d8a88f40719 diff --git a/meson.build b/meson.build index da96e296e0..118276edb7 100644 --- a/meson.build +++ b/meson.build @@ -1101,9 +1101,35 @@ if not fdt.found() and fdt_required.length() > 0 error('fdt not available but required by targets ' + ', '.join(fdt_required)) endif +ucontext = not_found +slirp_opt = 'disabled' +if get_option('ucontext').enabled() + if not fs.is_dir(meson.current_source_dir() / 'libucontext/arch' / cpu) + error('libucontext is wanted but not implemented for host ' + cpu) + endif + arch = host_machine.cpu() + ucontext_cargs = ['-DG_LOG_DOMAIN="ucontext"', '-DCUSTOM_IMPL'] + ucontext_files = [ + 'libucontext/arch' / arch / 'getcontext.S', + 'libucontext/arch' / arch / 'setcontext.S', + 'libucontext/arch' / arch / 'makecontext.c', + 'libucontext/arch' / arch / 'startcontext.S', + 'libucontext/arch' / arch / 'swapcontext.S', + ] + + ucontext_inc = include_directories('libucontext/include') + libucontext = static_library('ucontext', + sources: ucontext_files, + c_args: ucontext_cargs, + include_directories: ucontext_inc) + ucontext = declare_dependency(link_with: libucontext, + include_directories: ucontext_inc) +endif + config_host_data.set('CONFIG_CAPSTONE', capstone.found()) config_host_data.set('CONFIG_FDT', fdt.found()) config_host_data.set('CONFIG_SLIRP', slirp.found()) +config_host_data.set('CONFIG_LIBUCONTEXT', ucontext.found()) genh += configure_file(output: 'config-host.h', configuration: config_host_data) @@ -1323,7 +1349,7 @@ util_ss.add_all(trace_ss) util_ss = util_ss.apply(config_all, strict: false) libqemuutil = static_library('qemuutil', sources: util_ss.sources() + stub_ss.sources() + genh, - dependencies: [util_ss.dependencies(), m, glib, socket, malloc]) + dependencies: [util_ss.dependencies(), m, glib, socket, malloc, ucontext]) qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) @@ -1946,6 +1972,7 @@ if targetos == 'windows' summary_info += {'QGA MSI support': config_host.has_key('CONFIG_QGA_MSI')} endif summary_info += {'seccomp support': config_host.has_key('CONFIG_SECCOMP')} +summary_info += {'libucontext support': ucontext.found()} summary_info += {'coroutine backend': config_host['CONFIG_COROUTINE_BACKEND']} summary_info += {'coroutine pool': config_host['CONFIG_COROUTINE_POOL'] == '1'} summary_info += {'debug stack usage': config_host.has_key('CONFIG_DEBUG_STACK_USAGE')} diff --git a/meson_options.txt b/meson_options.txt index bcecbd5e12..acd989dfa2 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -50,6 +50,8 @@ option('vnc_sasl', type : 'feature', value : 'auto', description: 'SASL authentication for VNC server') option('xkbcommon', type : 'feature', value : 'auto', description: 'xkbcommon support') +option('ucontext', type : 'feature', value : 'disabled', + description: 'libucontext support') option('capstone', type: 'combo', value: 'auto', choices: ['disabled', 'enabled', 'auto', 'system', 'internal'], diff --git a/util/coroutine-ucontext.c b/util/coroutine-ucontext.c index 904b375192..1e1dd43512 100644 --- a/util/coroutine-ucontext.c +++ b/util/coroutine-ucontext.c @@ -23,7 +23,16 @@ #undef _FORTIFY_SOURCE #endif #include "qemu/osdep.h" +#if defined(CONFIG_LIBUCONTEXT) +#include +#define ucontext_t libucontext_ucontext_t +#define getcontext libucontext_getcontext +#define setcontext libucontext_setcontext +#define swapcontext libucontext_swapcontext +#define makecontext libucontext_makecontext +#else #include +#endif #include "qemu/coroutine_int.h" #ifdef CONFIG_VALGRIND_H From patchwork Mon Oct 12 23:29:36 2020 Content-Type: text/plain; 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Mon, 12 Oct 2020 16:29:51 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.49 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:50 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 07/10] tcg: implement bulletproof JIT Date: Mon, 12 Oct 2020 16:29:36 -0700 Message-Id: <20201012232939.48481-8-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.196; envelope-from=osy86dev@gmail.com; helo=mail-pg1-f196.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:43 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , "open list:RISC-V TCG target" , Stefan Weil , "open list:S390 TCG target" , Aleksandar Markovic , "open list:AArch64 TCG target" , Palmer Dabbelt , Joelle van Dyne , Huacai Chen , Paolo Bonzini , Alistair Francis , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy On iOS, we cannot allocate RWX pages without special entitlements. As a workaround, we can a RX region and then mirror map it to a separate RX region. Then we can write to one region and execute from the other one. To better keep track of pointers to RW/RX memory, we mark any tcg_insn_unit pointers as `const` if they will never be written to. We also define a new macro `TCG_CODE_PTR_RW` that returns a pointer to RW memory. Only the difference between the two regions is stored in the TCG context. To ensure cache coherency, we flush the data cache in the RW mapping and then invalidate the instruction cache in the RX mapping (where applicable). Because data cache flush is OS defined on some architectures, we do not provide implementations for non iOS platforms (ARM/x86). Signed-off-by: Joelle van Dyne --- accel/tcg/cpu-exec.c | 7 +++- accel/tcg/translate-all.c | 78 ++++++++++++++++++++++++++++++++++-- configure | 1 + docs/devel/ios.rst | 40 ++++++++++++++++++ include/exec/exec-all.h | 8 ++++ include/tcg/tcg.h | 18 +++++++-- tcg/aarch64/tcg-target.c.inc | 48 +++++++++++++--------- tcg/aarch64/tcg-target.h | 13 +++++- tcg/arm/tcg-target.c.inc | 33 ++++++++------- tcg/arm/tcg-target.h | 9 ++++- tcg/i386/tcg-target.c.inc | 28 ++++++------- tcg/i386/tcg-target.h | 24 ++++++++++- tcg/mips/tcg-target.c.inc | 64 +++++++++++++++++------------ tcg/mips/tcg-target.h | 8 +++- tcg/ppc/tcg-target.c.inc | 55 ++++++++++++++++--------- tcg/ppc/tcg-target.h | 8 +++- tcg/riscv/tcg-target.c.inc | 51 +++++++++++++---------- tcg/riscv/tcg-target.h | 9 ++++- tcg/s390/tcg-target.c.inc | 25 ++++++------ tcg/s390/tcg-target.h | 13 +++++- tcg/sparc/tcg-target.c.inc | 33 +++++++++------ tcg/sparc/tcg-target.h | 8 +++- tcg/tcg-ldst.c.inc | 2 +- tcg/tcg-pool.c.inc | 9 +++-- tcg/tcg.c | 60 +++++++++++++++++---------- tcg/tci/tcg-target.c.inc | 8 ++-- tcg/tci/tcg-target.h | 9 ++++- 27 files changed, 481 insertions(+), 188 deletions(-) create mode 100644 docs/devel/ios.rst diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 58aea605d8..821aefdea2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -354,7 +354,12 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset = tb->jmp_target_arg[n]; uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr; - tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); +#if defined(CONFIG_IOS_JIT) + uintptr_t wr_addr = tc_ptr + offset + tb->code_rw_mirror_diff; +#else + uintptr_t wr_addr = tc_ptr + offset; +#endif + tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr, wr_addr); } else { tb->jmp_target_arg[n] = addr; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d76097296d..76d8dc3d7b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -60,6 +60,22 @@ #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" +#if defined(CONFIG_IOS_JIT) +#include +extern kern_return_t mach_vm_remap(vm_map_t target_task, + mach_vm_address_t *target_address, + mach_vm_size_t size, + mach_vm_offset_t mask, + int flags, + vm_map_t src_task, + mach_vm_address_t src_address, + boolean_t copy, + vm_prot_t *cur_protection, + vm_prot_t *max_protection, + vm_inherit_t inheritance + ); +#endif + /* #define DEBUG_TB_INVALIDATE */ /* #define DEBUG_TB_FLUSH */ /* make various TB consistency checks */ @@ -302,10 +318,13 @@ static target_long decode_sleb128(uint8_t **pp) static int encode_search(TranslationBlock *tb, uint8_t *block) { - uint8_t *highwater = tcg_ctx->code_gen_highwater; - uint8_t *p = block; + uint8_t *highwater; + uint8_t *p; int i, j, n; + highwater = (uint8_t *)TCG_CODE_PTR_RW(tcg_ctx, + tcg_ctx->code_gen_highwater); + p = (uint8_t *)TCG_CODE_PTR_RW(tcg_ctx, block); for (i = 0, n = tb->icount; i < n; ++i) { target_ulong prev; @@ -329,7 +348,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) } } - return p - block; + return p - (uint8_t *)TCG_CODE_PTR_RW(tcg_ctx, block); } /* The cpu state corresponding to 'searched_pc' is restored. @@ -1067,7 +1086,11 @@ static inline void *alloc_code_gen_buffer(void) #else static inline void *alloc_code_gen_buffer(void) { +#if defined(CONFIG_IOS_JIT) + int prot = PROT_READ | PROT_EXEC; +#else int prot = PROT_WRITE | PROT_READ | PROT_EXEC; +#endif int flags = MAP_PRIVATE | MAP_ANONYMOUS; size_t size = tcg_ctx->code_gen_buffer_size; void *buf; @@ -1118,6 +1141,39 @@ static inline void *alloc_code_gen_buffer(void) } #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ +#if defined(CONFIG_IOS_JIT) +static inline void *alloc_jit_rw_mirror(void *base, size_t size) +{ + kern_return_t ret; + mach_vm_address_t mirror; + vm_prot_t cur_prot, max_prot; + + mirror = 0; + ret = mach_vm_remap(mach_task_self(), + &mirror, + size, + 0, + VM_FLAGS_ANYWHERE | VM_FLAGS_RANDOM_ADDR, + mach_task_self(), + (mach_vm_address_t)base, + false, + &cur_prot, + &max_prot, + VM_INHERIT_NONE + ); + if (ret != KERN_SUCCESS) { + return NULL; + } + + if (mprotect((void *)mirror, size, PROT_READ | PROT_WRITE) != 0) { + munmap((void *)mirror, size); + return NULL; + } + + return (void *)mirror; +} +#endif /* CONFIG_IOS_JIT */ + static inline void code_gen_alloc(size_t tb_size) { tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size); @@ -1126,6 +1182,19 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } +#if defined(CONFIG_IOS_JIT) + void *mirror; + + /* For iOS JIT we need a mirror mapping for code execution */ + mirror = alloc_jit_rw_mirror(tcg_ctx->code_gen_buffer, + tcg_ctx->code_gen_buffer_size + ); + if (mirror == NULL) { + fprintf(stderr, "Could not remap code buffer mirror\n"); + exit(1); + } + tcg_ctx->code_rw_mirror_diff = mirror - tcg_ctx->code_gen_buffer; +#endif /* CONFIG_IOS_JIT */ } static bool tb_cmp(const void *ap, const void *bp) @@ -1721,6 +1790,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cpu_loop_exit(cpu); } +#if defined(CONFIG_IOS_JIT) + tb->code_rw_mirror_diff = tcg_ctx->code_rw_mirror_diff; +#endif gen_code_buf = tcg_ctx->code_gen_ptr; tb->tc.ptr = gen_code_buf; tb->pc = pc; diff --git a/configure b/configure index 16c66b437c..c5a6584683 100755 --- a/configure +++ b/configure @@ -6220,6 +6220,7 @@ fi if test "$ios" = "yes" ; then echo "CONFIG_IOS=y" >> $config_host_mak + echo "CONFIG_IOS_JIT=y" >> $config_host_mak fi if test "$solaris" = "yes" ; then diff --git a/docs/devel/ios.rst b/docs/devel/ios.rst new file mode 100644 index 0000000000..dba9fdd868 --- /dev/null +++ b/docs/devel/ios.rst @@ -0,0 +1,40 @@ +=========== +iOS Support +=========== + +To run qemu on the iOS platform, some modifications were required. Most of the +modifications are conditioned on the ``CONFIG_IOS`` and ``CONFIG_IOS_JIT`` +configuration variables. + +Build support +------------- + +For the code to compile, certain changes in the block driver and the slirp +driver had to be made. There is no ``system()`` call, so code requiring it had +to be disabled. + +``ucontext`` support is broken on iOS. The implementation from ``libucontext`` +is used instead. + +Because ``fork()`` is not allowed on iOS apps, the option to build qemu and the +utilities as shared libraries is added. Note that because qemu does not perform +resource cleanup in most cases (open files, allocated memory, etc), it is +advisable that the user implements a proxy layer for syscalls so resources can +be kept track by the app that uses qemu as a shared library. + +JIT support +----------- + +On iOS, allocating RWX pages require special entitlements not usually granted to +apps. However, it is possible to use `bulletproof JIT`_ with a development +certificate. This means that we need to allocate one chunk of memory with RX +permissions and then mirror map the same memory with RW permissions. We generate +code to the mirror mapping and execute the original mapping. + +With ``CONFIG_IOS_JIT`` defined, we store inside the TCG context the difference +between the two mappings. Then, we make sure that any writes to JIT memory is +done to the pointer + the difference (in order to get a pointer to the mirror +mapped space). Additionally, we make sure to flush the data cache before we +invalidate the instruction cache so the changes are seen in both mappings. + +.. _bulletproof JIT: https://www.blackhat.com/docs/us-16/materials/us-16-Krstic.pdf diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 66f9b4cca6..2db155a772 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -483,6 +483,14 @@ struct TranslationBlock { uintptr_t jmp_list_head; uintptr_t jmp_list_next[2]; uintptr_t jmp_dest[2]; + +#if defined(CONFIG_IOS_JIT) + /* + * Store difference to writable mirror + * We need this when patching the jump instructions + */ + ptrdiff_t code_rw_mirror_diff; +#endif }; extern bool parallel_cpus; diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8804a8c4a2..40d1a7a85e 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -261,7 +261,7 @@ struct TCGLabel { unsigned refs : 16; union { uintptr_t value; - tcg_insn_unit *value_ptr; + const tcg_insn_unit *value_ptr; } u; QSIMPLEQ_HEAD(, TCGRelocation) relocs; QSIMPLEQ_ENTRY(TCGLabel) next; @@ -593,7 +593,7 @@ struct TCGContext { int nb_ops; /* goto_tb support */ - tcg_insn_unit *code_buf; + const tcg_insn_unit *code_buf; uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ @@ -627,6 +627,9 @@ struct TCGContext { size_t code_gen_buffer_size; void *code_gen_ptr; void *data_gen_ptr; +#if defined(CONFIG_IOS_JIT) + ptrdiff_t code_rw_mirror_diff; +#endif /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; @@ -677,6 +680,13 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; +#if defined(CONFIG_IOS_JIT) +# define TCG_CODE_PTR_RW(s, code_ptr) \ + (tcg_insn_unit *)((uintptr_t)(code_ptr) + (s)->code_rw_mirror_diff) +#else +# define TCG_CODE_PTR_RW(s, code_ptr) (code_ptr) +#endif + extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; extern TCGv_env cpu_env; @@ -1099,7 +1109,7 @@ static inline TCGLabel *arg_label(TCGArg i) * correct result. */ -static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) +static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) { return a - b; } @@ -1113,7 +1123,7 @@ static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) * to the destination address. */ -static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) +static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) { return tcg_ptr_byte_diff(target, s->code_ptr); } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 26f71cb599..9cfa2703b3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -78,38 +78,44 @@ static const int tcg_target_call_oarg_regs[1] = { #define TCG_REG_GUEST_BASE TCG_REG_X28 #endif -static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static inline bool reloc_pc26(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { ptrdiff_t offset = target - code_ptr; if (offset == sextract64(offset, 0, 26)) { /* read instruction, mask away previous PC_REL26 parameter contents, set the proper offset, then write back the instruction. */ - *code_ptr = deposit32(*code_ptr, 0, 26, offset); + *TCG_CODE_PTR_RW(s, code_ptr) = + deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 0, 26, offset); return true; } return false; } -static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static inline bool reloc_pc19(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { ptrdiff_t offset = target - code_ptr; if (offset == sextract64(offset, 0, 19)) { - *code_ptr = deposit32(*code_ptr, 5, 19, offset); + *TCG_CODE_PTR_RW(s, code_ptr) = + deposit32(*TCG_CODE_PTR_RW(s, code_ptr), 5, 19, offset); return true; } return false; } -static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static inline bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend == 0); switch (type) { case R_AARCH64_JUMP26: case R_AARCH64_CALL26: - return reloc_pc26(code_ptr, (tcg_insn_unit *)value); + return reloc_pc26(s, code_ptr, (tcg_insn_unit *)value); case R_AARCH64_CONDBR19: - return reloc_pc19(code_ptr, (tcg_insn_unit *)value); + return reloc_pc19(s, code_ptr, (tcg_insn_unit *)value); default: g_assert_not_reached(); } @@ -1306,14 +1312,14 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, } } -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; tcg_debug_assert(offset == sextract64(offset, 0, 26)); tcg_out_insn(s, 3206, B, offset); } -static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { @@ -1329,7 +1335,7 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg) tcg_out_insn(s, 3207, BLR, reg); } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { @@ -1341,7 +1347,7 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) } void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) + uintptr_t addr, uintptr_t wr_addr) { tcg_insn_unit i1, i2; TCGType rt = TCG_TYPE_I64; @@ -1362,7 +1368,10 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; } pair = (uint64_t)i2 << 32 | i1; - qatomic_set((uint64_t *)jmp_addr, pair); + qatomic_set((uint64_t *)wr_addr, pair); +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 8); +#endif flush_icache_range(jmp_addr, jmp_addr + 8); } @@ -1568,7 +1577,7 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) +static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) { ptrdiff_t offset = tcg_pcrel_diff(s, target); tcg_debug_assert(offset == sextract64(offset, 0, 21)); @@ -1581,7 +1590,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); MemOp size = opc & MO_SIZE; - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc19(s, lb->label_ptr[0], s->code_ptr)) { return false; } @@ -1606,7 +1615,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); MemOp size = opc & MO_SIZE; - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc19(s, lb->label_ptr[0], s->code_ptr)) { return false; } @@ -1622,7 +1631,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, TCGType ext, TCGReg data_reg, TCGReg addr_reg, - tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) + const tcg_insn_unit *raddr, + tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -1849,7 +1859,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, #endif /* CONFIG_SOFTMMU */ } -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], @@ -2916,11 +2926,11 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, 3207, RET, TCG_REG_LR); } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { int i; for (i = 0; i < count; ++i) { - p[i] = NOP; + (TCG_CODE_PTR_RW(s, p))[i] = NOP; } } diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a2b22b4305..78c97460a1 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -150,6 +150,7 @@ typedef enum { #if defined(__APPLE__) void sys_icache_invalidate(void *start, size_t len); +void sys_dcache_flush(void *start, size_t len); #endif static inline void flush_icache_range(uintptr_t start, uintptr_t stop) @@ -163,7 +164,17 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) #endif } -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#if defined(__APPLE__) + sys_dcache_flush((char *)start, stop - start); +#else +#error "Missing function to flush data cache" +#endif +} +#endif #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..d27ad851b5 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -187,17 +187,22 @@ static const uint8_t tcg_cond_to_arm_cond[] = { [TCG_COND_GTU] = COND_HI, }; -static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static inline bool reloc_pc24(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; if (offset == sextract32(offset, 0, 24)) { - *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); + *TCG_CODE_PTR_RW(s, code_ptr) = + (*TCG_CODE_PTR_RW(s, code_ptr) & ~0xffffff) | (offset & 0xffffff); return true; } return false; } -static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static inline bool reloc_pc13(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8; @@ -209,21 +214,21 @@ static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target) } insn = deposit32(insn, 23, 1, u); insn = deposit32(insn, 0, 12, offset); - *code_ptr = insn; + *TCG_CODE_PTR_RW(s, code_ptr) = insn; return true; } return false; } -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(addend == 0); if (type == R_ARM_PC24) { - return reloc_pc24(code_ptr, (tcg_insn_unit *)value); + return reloc_pc24(s, code_ptr, (tcg_insn_unit *)value); } else if (type == R_ARM_PC13) { - return reloc_pc13(code_ptr, (tcg_insn_unit *)value); + return reloc_pc13(s, code_ptr, (tcg_insn_unit *)value); } else { g_assert_not_reached(); } @@ -1019,7 +1024,7 @@ static inline void tcg_out_st8(TCGContext *s, int cond, * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which does. */ -static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) +static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); @@ -1033,7 +1038,7 @@ static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) /* The call case is mostly used for helpers - so it's not unreasonable * for them to be beyond branch range */ -static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); @@ -1326,7 +1331,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, helper code. */ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, - TCGReg addrhi, tcg_insn_unit *raddr, + TCGReg addrhi, const tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -1348,7 +1353,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); void *func; - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc24(s, lb->label_ptr[0], s->code_ptr)) { return false; } @@ -1411,7 +1416,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; MemOp opc = get_memop(oi); - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc24(s, lb->label_ptr[0], s->code_ptr)) { return false; } @@ -2255,11 +2260,11 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { int i; for (i = 0; i < count; ++i) { - p[i] = INSN_NOP; + (TCG_CODE_PTR_RW(s, p))[i] = INSN_NOP; } } diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..d8d7e7e239 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -139,8 +139,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#error "Unimplemented dcache flush function" +} +#endif + /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..e9c128d9e7 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -165,9 +165,9 @@ static bool have_lzcnt; # define have_lzcnt 0 #endif -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { value += addend; @@ -179,14 +179,14 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, } /* FALLTHRU */ case R_386_32: - tcg_patch32(code_ptr, value); + tcg_patch32(s, code_ptr, value); break; case R_386_PC8: value -= (uintptr_t)code_ptr; if (value != (int8_t)value) { return false; } - tcg_patch8(code_ptr, value); + tcg_patch8(s, code_ptr, value); break; default: tcg_abort(); @@ -1591,7 +1591,7 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, } } -static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) +static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) { intptr_t disp = tcg_pcrel_diff(s, dest) - 5; @@ -1610,12 +1610,12 @@ static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) } } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_branch(s, 1, dest); } -static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_branch(s, 0, dest); } @@ -1774,7 +1774,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, TCGMemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, + const tcg_insn_unit *raddr, tcg_insn_unit **label_ptr) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -1805,9 +1805,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0); /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); + tcg_patch32(s, label_ptr[0], s->code_ptr - label_ptr[0] - 4); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); + tcg_patch32(s, label_ptr[1], s->code_ptr - label_ptr[1] - 4); } if (TCG_TARGET_REG_BITS == 32) { @@ -1890,9 +1890,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) TCGReg retaddr; /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); + tcg_patch32(s, label_ptr[0], s->code_ptr - label_ptr[0] - 4); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); + tcg_patch32(s, label_ptr[1], s->code_ptr - label_ptr[1] - 4); } if (TCG_TARGET_REG_BITS == 32) { @@ -3842,9 +3842,9 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc(s, OPC_RET, 0, 0, 0); } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { - memset(p, 0x90, count); + memset(TCG_CODE_PTR_RW(s, p), 0x90, count); } static void tcg_target_init(TCGContext *s) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..cdc440ce36 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -206,16 +206,36 @@ extern bool have_avx2; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) +#ifdef __APPLE__ +void sys_dcache_flush(void *start, size_t len); +#endif + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#if defined(__APPLE__) + sys_dcache_flush((char *)start, stop - start); +#else +#error "Missing function to flush data cache" +#endif +} +#endif + static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) + uintptr_t jmp_addr, uintptr_t addr, + uintptr_t wr_addr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)wr_addr, addr - (jmp_addr + 4)); /* no need to flush icache explicitly */ +#if defined(CONFIG_IOS_JIT) + /* we do need to flush mirror dcache */ + flush_dcache_range(wr_addr, wr_addr + 4); +#endif } /* This defines the natural memory order supported by this diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..e798527437 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -139,12 +139,13 @@ static const TCGReg tcg_target_call_oarg_regs[2] = { TCG_REG_V1 }; -static tcg_insn_unit *tb_ret_addr; -static tcg_insn_unit *bswap32_addr; -static tcg_insn_unit *bswap32u_addr; -static tcg_insn_unit *bswap64_addr; +static const tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *bswap32_addr; +static const tcg_insn_unit *bswap32u_addr; +static const tcg_insn_unit *bswap64_addr; -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline uint32_t reloc_pc16_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); @@ -152,28 +153,35 @@ static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) return disp & 0xffff; } -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline void reloc_pc16(TCGContext *s, + tcg_insn_unit *pc, + const tcg_insn_unit *target) { - *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); + *TCG_CODE_PTR_RW(s, pc) = + deposit32(*TCG_CODE_PTR_RW(s, pc), 0, 16, reloc_pc16_val(pc, target)); } -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline uint32_t reloc_26_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); return ((uintptr_t)target >> 2) & 0x3ffffff; } -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline void reloc_26(TCGContext *s, + tcg_insn_unit *pc, + const tcg_insn_unit *target) { - *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); + *TCG_CODE_PTR_RW(s, pc) = + deposit32(*TCG_CODE_PTR_RW(s, pc), 0, 26, reloc_26_val(pc, target)); } -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(type == R_MIPS_PC16); tcg_debug_assert(addend == 0); - reloc_pc16(code_ptr, (tcg_insn_unit *)value); + reloc_pc16(s, code_ptr, (tcg_insn_unit *)value); return true; } @@ -516,7 +524,7 @@ static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, * Type jump. * Returns true if the branch was in range and the insn was emitted. */ -static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target) +static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) { uintptr_t dest = (uintptr_t)target; uintptr_t from = (uintptr_t)s->code_ptr + 4; @@ -631,7 +639,7 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) } } -static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) +static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); tcg_debug_assert(ok); @@ -925,7 +933,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, tcg_out_opc_br(s, b_opc, arg1, arg2); if (l->has_value) { - reloc_pc16(s->code_ptr - 1, l->u.value_ptr); + reloc_pc16(s, s->code_ptr - 1, l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); } @@ -1079,7 +1087,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, } } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { /* Note that the ABI requires the called function's address to be loaded into T9, even if a direct branch is in range. */ @@ -1097,7 +1105,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); tcg_out_nop(s); @@ -1289,7 +1297,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, TCGType ext, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit *label_ptr[2]) + const tcg_insn_unit *raddr, + tcg_insn_unit *label_ptr[2]) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -1315,9 +1324,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int i; /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); + reloc_pc16(s, l->label_ptr[0], s->code_ptr); if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); + reloc_pc16(s, l->label_ptr[1], s->code_ptr); } i = 1; @@ -1345,7 +1354,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); - reloc_pc16(s->code_ptr - 1, l->raddr); + reloc_pc16(s, s->code_ptr - 1, l->raddr); /* delay slot */ if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { @@ -1365,9 +1374,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int i; /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); + reloc_pc16(s, l->label_ptr[0], s->code_ptr); if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); + reloc_pc16(s, l->label_ptr[1], s->code_ptr); } i = 1; @@ -2430,7 +2439,7 @@ static void tcg_target_detect_isa(void) sigaction(SIGILL, &sa_old, NULL); } -static tcg_insn_unit *align_code_ptr(TCGContext *s) +static const tcg_insn_unit *align_code_ptr(TCGContext *s) { uintptr_t p = (uintptr_t)s->code_ptr; if (p & 15) { @@ -2657,9 +2666,12 @@ static void tcg_target_init(TCGContext *s) } void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) + uintptr_t addr, uintptr_t wr_addr) { - qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); + qatomic_set((uint32_t *)wr_addr, deposit32(OPC_J, 0, 26, addr >> 2)); +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 4); +#endif flush_icache_range(jmp_addr, jmp_addr + 4); } diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..80dcba5358 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -212,7 +212,13 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#error "Unimplemented dcache flush function" +} +#endif #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..f5a44e9852 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -62,7 +62,7 @@ #define TCG_CT_CONST_MONE 0x2000 #define TCG_CT_CONST_WSZ 0x4000 -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; TCGPowerISA have_isa; static bool have_isel; @@ -184,35 +184,43 @@ static inline bool in_range_b(tcg_target_long target) return target == sextract64(target, 0, 26); } -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); return disp & 0x3fffffc; } -static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc24(TCGContext *s, + tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); if (in_range_b(disp)) { - *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc); + *TCG_CODE_PTR_RW(s, pc) = + (*TCG_CODE_PTR_RW(s, pc) & ~0x3fffffc) | (disp & 0x3fffffc); return true; } return false; } -static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp == (int16_t) disp); return disp & 0xfffc; } -static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc14(TCGContext *s, + tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); if (disp == (int16_t) disp) { - *pc = (*pc & ~0xfffc) | (disp & 0xfffc); + *TCG_CODE_PTR_RW(s, pc) = + (*TCG_CODE_PTR_RW(s, pc) & ~0xfffc) | (disp & 0xfffc); return true; } return false; @@ -670,7 +678,7 @@ static const uint32_t tcg_to_isel[] = { [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), }; -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_insn_unit *target; @@ -682,9 +690,9 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, switch (type) { case R_PPC_REL14: - return reloc_pc14(code_ptr, target); + return reloc_pc14(s, code_ptr, target); case R_PPC_REL24: - return reloc_pc24(code_ptr, target); + return reloc_pc24(s, code_ptr, target); case R_PPC_ADDR16: /* * We are (slightly) abusing this relocation type. In particular, @@ -1106,7 +1114,7 @@ static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) tcg_out_zori32(s, dst, src, c, XORI, XORIS); } -static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target) +static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_pcrel_diff(s, target); if (in_range_b(disp)) { @@ -1723,7 +1731,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) + uintptr_t addr, uintptr_t wr_addr) { if (TCG_TARGET_REG_BITS == 64) { tcg_insn_unit i1, i2; @@ -1752,17 +1760,23 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, /* As per the enclosing if, this is ppc64. Avoid the _Static_assert within qatomic_set that would fail to build a ppc32 host. */ - qatomic_set__nocheck((uint64_t *)jmp_addr, pair); + qatomic_set__nocheck((uint64_t *)wr_addr, pair); +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 8); +#endif flush_icache_range(jmp_addr, jmp_addr + 8); } else { intptr_t diff = addr - jmp_addr; tcg_debug_assert(in_range_b(diff)); - qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); + qatomic_set((uint32_t *)wr_addr, B | (diff & 0x3fffffc)); +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 8); +#endif flush_icache_range(jmp_addr, jmp_addr + 4); } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we @@ -1987,7 +2001,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) + const tcg_insn_unit *raddr, + tcg_insn_unit *lptr) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -2007,7 +2022,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); TCGReg hi, lo, arg = TCG_REG_R3; - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc14(s, lb->label_ptr[0], s->code_ptr)) { return false; } @@ -2055,7 +2070,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp s_bits = opc & MO_SIZE; TCGReg hi, lo, arg = TCG_REG_R3; - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc14(s, lb->label_ptr[0], s->code_ptr)) { return false; } @@ -2252,11 +2267,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #endif } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { int i; for (i = 0; i < count; ++i) { - p[i] = NOP; + (TCG_CODE_PTR_RW(s, p))[i] = NOP; } } diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..23d7a337c9 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -176,7 +176,13 @@ extern bool have_vsx; #define TCG_TARGET_HAS_cmpsel_vec 0 void flush_icache_range(uintptr_t start, uintptr_t stop); -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#error "Unimplemented dcache flush function" +} +#endif #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..2d96c83c4b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -413,11 +413,11 @@ static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, tcg_out32(s, encode_uj(opc, rd, imm)); } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { int i; for (i = 0; i < count; ++i) { - p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + (TCG_CODE_PTR_RW(s, p))[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); } } @@ -425,46 +425,52 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) * Relocations */ -static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_sbimm12(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; if (offset == sextreg(offset, 1, 12) << 1) { - code_ptr[0] |= encode_sbimm12(offset); + (TCG_CODE_PTR_RW(s, code_ptr))[0] |= encode_sbimm12(offset); return true; } return false; } -static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_jimm20(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; if (offset == sextreg(offset, 1, 20) << 1) { - code_ptr[0] |= encode_ujimm20(offset); + (TCG_CODE_PTR_RW(s, code_ptr))[0] |= encode_ujimm20(offset); return true; } return false; } -static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_call(TCGContext *s, + tcg_insn_unit *code_ptr, + const tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; int32_t lo = sextreg(offset, 0, 12); int32_t hi = offset - lo; if (offset == hi + lo) { - code_ptr[0] |= encode_uimm20(hi); - code_ptr[1] |= encode_imm12(lo); + (TCG_CODE_PTR_RW(s, code_ptr))[0] |= encode_uimm20(hi); + (TCG_CODE_PTR_RW(s, code_ptr))[1] |= encode_imm12(lo); return true; } return false; } -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { uint32_t insn = *code_ptr; @@ -478,7 +484,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, diff = value - (uintptr_t)code_ptr; short_jmp = diff == sextreg(diff, 0, 12); if (short_jmp) { - return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); + return reloc_sbimm12(s, code_ptr, (tcg_insn_unit *)value); } else { /* Invert the condition */ insn = insn ^ (1 << 12); @@ -499,9 +505,9 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, } break; case R_RISCV_JAL: - return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); + return reloc_jimm20(s, code_ptr, (tcg_insn_unit *)value); case R_RISCV_CALL: - return reloc_call(code_ptr, (tcg_insn_unit *)value); + return reloc_call(s, code_ptr, (tcg_insn_unit *)value); default: tcg_abort(); } @@ -557,7 +563,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, if (tmp == (int32_t)tmp) { tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); - ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); + ret = reloc_call(s, s->code_ptr - 2, (tcg_insn_unit *)val); tcg_debug_assert(ret == true); return; } @@ -854,14 +860,14 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, g_assert_not_reached(); } -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = tcg_pcrel_diff(s, target); tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; ptrdiff_t offset = tcg_pcrel_diff(s, arg); @@ -875,7 +881,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) /* long jump: -2147483646 to 2147483648 */ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); - ret = reloc_call(s->code_ptr - 2, arg);\ + ret = reloc_call(s, s->code_ptr - 2, arg);\ tcg_debug_assert(ret == true); } else if (TCG_TARGET_REG_BITS == 64) { /* far jump: 64-bit */ @@ -888,7 +894,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); } @@ -1022,7 +1028,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, TCGType ext, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit **label_ptr) + const tcg_insn_unit *raddr, + tcg_insn_unit **label_ptr) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -1052,7 +1059,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + if (!patch_reloc(s, l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0)) { return false; } @@ -1087,7 +1094,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + if (!patch_reloc(s, l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0)) { return false; } @@ -1274,7 +1281,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #endif } -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..d42b361991 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -164,8 +164,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *)start, (char *)stop); } +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#error "Unimplemented dcache flush function" +} +#endif + /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..49a96ca15f 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -363,10 +363,10 @@ static void * const qemu_st_helpers[16] = { }; #endif -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; uint64_t s390_facilities; -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { intptr_t pcrel2; @@ -378,13 +378,13 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, switch (type) { case R_390_PC16DBL: if (pcrel2 == (int16_t)pcrel2) { - tcg_patch16(code_ptr, pcrel2); + tcg_patch16(s, code_ptr, pcrel2); return true; } break; case R_390_PC32DBL: if (pcrel2 == (int32_t)pcrel2) { - tcg_patch32(code_ptr, pcrel2); + tcg_patch32(s, code_ptr, pcrel2); return true; } break; @@ -392,7 +392,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, if (value == sextract64(value, 0, 20)) { old = *(uint32_t *)code_ptr & 0xf00000ff; old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); - tcg_patch32(code_ptr, old); + tcg_patch32(s, code_ptr, old); return true; } break; @@ -1302,7 +1302,7 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); } -static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest) +static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) { ptrdiff_t off = dest - s->code_ptr; if (off == (int16_t)off) { @@ -1415,7 +1415,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, tgen_branch(s, cc, l); } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { ptrdiff_t off = dest - s->code_ptr; if (off == (int32_t)off) { @@ -1593,7 +1593,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, TCGReg data, TCGReg addr, - tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) + const tcg_insn_unit *raddr, + tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label = new_ldst_label(s); @@ -1612,7 +1613,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; MemOp opc = get_memop(oi); - if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + if (!patch_reloc(s, lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2)) { return false; } @@ -1637,7 +1638,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; MemOp opc = get_memop(oi); - if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + if (!patch_reloc(s, lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2)) { return false; } @@ -2575,9 +2576,9 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { - memset(p, 0x07, count * sizeof(tcg_insn_unit)); + memset(TCG_CODE_PTR_RW(s, p), 0x07, count * sizeof(tcg_insn_unit)); } typedef struct { diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..d67632512d 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -149,13 +149,24 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#error "Unimplemented dcache flush function" +} +#endif + static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) + uintptr_t jmp_addr, uintptr_t addr, + uintptr_t wr_addr) { /* patch the branch destination */ intptr_t disp = addr - (jmp_addr - 2); qatomic_set((int32_t *)jmp_addr, disp / 2); /* no need to flush icache explicitly */ +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 4); +#endif } #ifdef CONFIG_SOFTMMU diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6775bd30fc..af97cbdeef 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -291,14 +291,14 @@ static inline int check_fit_i32(int32_t val, unsigned int bits) # define check_fit_ptr check_fit_i32 #endif -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { uint32_t insn = *code_ptr; intptr_t pcrel; value += addend; - pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); + pcrel = tcg_ptr_byte_diff((const tcg_insn_unit *)value, code_ptr); switch (type) { case R_SPARC_WDISP16: @@ -840,7 +840,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } -static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, +static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, bool in_prologue) { ptrdiff_t disp = tcg_pcrel_diff(s, dest); @@ -855,7 +855,7 @@ static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_call_nodelay(s, dest, false); tcg_out_nop(s); @@ -868,8 +868,8 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } #ifdef CONFIG_SOFTMMU -static tcg_insn_unit *qemu_ld_trampoline[16]; -static tcg_insn_unit *qemu_st_trampoline[16]; +static const tcg_insn_unit *qemu_ld_trampoline[16]; +static const tcg_insn_unit *qemu_st_trampoline[16]; static void emit_extend(TCGContext *s, TCGReg r, int op) { @@ -1048,11 +1048,11 @@ static void tcg_target_qemu_prologue(TCGContext *s) #endif } -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count) { int i; for (i = 0; i < count; ++i) { - p[i] = NOP; + (TCG_CODE_PTR_RW(s, p))[i] = NOP; } } @@ -1163,7 +1163,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; - tcg_insn_unit *func; + const tcg_insn_unit *func; tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, @@ -1226,7 +1226,8 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, } } - *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); + *TCG_CODE_PTR_RW(s, label_ptr) |= + INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else if (SPARC64 && TARGET_LONG_BITS == 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); @@ -1822,7 +1823,7 @@ void tcg_register_jit(void *buf, size_t buf_size) } void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) + uintptr_t addr, uintptr_t wr_addr) { intptr_t tb_disp = addr - tc_ptr; intptr_t br_disp = addr - jmp_addr; @@ -1834,8 +1835,11 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, tcg_debug_assert(br_disp == (int32_t)br_disp); if (!USE_REG_TB) { - qatomic_set((uint32_t *)jmp_addr, + qatomic_set((uint32_t *)wr_addr, deposit32(CALL, 0, 30, br_disp >> 2)); +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 4); +#endif flush_icache_range(jmp_addr, jmp_addr + 4); return; } @@ -1859,6 +1863,9 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); } - qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); + qatomic_set((uint64_t *)wr_addr, deposit64(i2, 32, 32, i1)); +#if defined(CONFIG_IOS_JIT) + flush_dcache_range(wr_addr, wr_addr + 8); +#endif flush_icache_range(jmp_addr, jmp_addr + 8); } diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..d102e13692 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -176,7 +176,13 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) } } -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +#error "Unimplemented dcache flush function" +} +#endif #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 05f9b3ccd6..eaba08700e 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -28,7 +28,7 @@ typedef struct TCGLabelQemuLdst { TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ - tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ + const tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st */ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; } TCGLabelQemuLdst; diff --git a/tcg/tcg-pool.c.inc b/tcg/tcg-pool.c.inc index 82cbcc89bd..97bb90b7cc 100644 --- a/tcg/tcg-pool.c.inc +++ b/tcg/tcg-pool.c.inc @@ -119,7 +119,7 @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, } /* To be provided by cpu/tcg-target.c.inc. */ -static void tcg_out_nop_fill(tcg_insn_unit *p, int count); +static void tcg_out_nop_fill(TCGContext *s, tcg_insn_unit *p, int count); static int tcg_out_pool_finalize(TCGContext *s) { @@ -135,7 +135,7 @@ static int tcg_out_pool_finalize(TCGContext *s) again when allocating the next TranslationBlock structure. */ a = (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong) * p->nlong); - tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); + tcg_out_nop_fill(s, s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); s->data_gen_ptr = a; for (; p != NULL; p = p->next) { @@ -144,11 +144,12 @@ static int tcg_out_pool_finalize(TCGContext *s) if (unlikely(a > s->code_gen_highwater)) { return -1; } - memcpy(a, p->data, size); + memcpy(TCG_CODE_PTR_RW(s, a), p->data, size); a += size; l = p; } - if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) { + if (!patch_reloc(s, p->label, p->rtype, + (intptr_t)a - size, p->addend)) { return -2; } } diff --git a/tcg/tcg.c b/tcg/tcg.c index a8c28440e2..ef203a34a6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -70,7 +70,7 @@ static void tcg_target_init(TCGContext *s); static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); static void tcg_target_qemu_prologue(TCGContext *s); -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend); /* The CIE and FDE header definitions will be common to all hosts. */ @@ -148,7 +148,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2); static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); #ifdef TCG_TARGET_NEED_LDST_LABELS @@ -203,13 +203,15 @@ static TCGRegSet tcg_target_call_clobber_regs; #if TCG_TARGET_INSN_UNIT_SIZE == 1 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) { - *s->code_ptr++ = v; + *TCG_CODE_PTR_RW(s, s->code_ptr) = v; + s->code_ptr++; } -static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, +static __attribute__((unused)) inline void tcg_patch8(TCGContext *s, + tcg_insn_unit *p, uint8_t v) { - *p = v; + *TCG_CODE_PTR_RW(s, p) = v; } #endif @@ -217,21 +219,23 @@ static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 2) { - *s->code_ptr++ = v; + *TCG_CODE_PTR_RW(s, s->code_ptr) = v; + s->code_ptr++; } else { tcg_insn_unit *p = s->code_ptr; - memcpy(p, &v, sizeof(v)); + memcpy(TCG_CODE_PTR_RW(s, p), &v, sizeof(v)); s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); } } -static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, +static __attribute__((unused)) inline void tcg_patch16(TCGContext *s, + tcg_insn_unit *p, uint16_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 2) { - *p = v; + *TCG_CODE_PTR_RW(s, p) = v; } else { - memcpy(p, &v, sizeof(v)); + memcpy(TCG_CODE_PTR_RW(s, p), &v, sizeof(v)); } } #endif @@ -240,21 +244,23 @@ static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 4) { - *s->code_ptr++ = v; + *TCG_CODE_PTR_RW(s, s->code_ptr) = v; + s->code_ptr++; } else { tcg_insn_unit *p = s->code_ptr; - memcpy(p, &v, sizeof(v)); + memcpy(TCG_CODE_PTR_RW(s, p), &v, sizeof(v)); s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); } } -static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, +static __attribute__((unused)) inline void tcg_patch32(TCGContext *s, + tcg_insn_unit *p, uint32_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 4) { *p = v; } else { - memcpy(p, &v, sizeof(v)); + memcpy(TCG_CODE_PTR_RW(s, p), &v, sizeof(v)); } } #endif @@ -263,21 +269,23 @@ static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 8) { - *s->code_ptr++ = v; + *TCG_CODE_PTR_RW(s, s->code_ptr) = v; + s->code_ptr++; } else { tcg_insn_unit *p = s->code_ptr; - memcpy(p, &v, sizeof(v)); + memcpy(TCG_CODE_PTR_RW(s, p), &v, sizeof(v)); s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); } } -static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, +static __attribute__((unused)) inline void tcg_patch64(TCGContext *s, + tcg_insn_unit *p, uint64_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 8) { *p = v; } else { - memcpy(p, &v, sizeof(v)); + memcpy(TCG_CODE_PTR_RW(s, p), &v, sizeof(v)); } } #endif @@ -295,7 +303,7 @@ static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); } -static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) +static void tcg_out_label(TCGContext *s, TCGLabel *l, const tcg_insn_unit *ptr) { tcg_debug_assert(!l->has_value); l->has_value = 1; @@ -325,7 +333,7 @@ static bool tcg_resolve_relocs(TCGContext *s) uintptr_t value = l->u.value; QSIMPLEQ_FOREACH(r, &l->relocs, next) { - if (!patch_reloc(r->ptr, r->type, value, r->addend)) { + if (!patch_reloc(s, r->ptr, r->type, value, r->addend)) { return false; } } @@ -1039,7 +1047,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) } qatomic_set(&s->code_gen_ptr, next); s->data_gen_ptr = NULL; - return tb; + return (TranslationBlock *)TCG_CODE_PTR_RW(s, tb); } void tcg_prologue_init(TCGContext *s) @@ -1076,6 +1084,10 @@ void tcg_prologue_init(TCGContext *s) #endif buf1 = s->code_ptr; +#if defined(CONFIG_IOS_JIT) + flush_dcache_range((uintptr_t)TCG_CODE_PTR_RW(s, buf0), + (uintptr_t)TCG_CODE_PTR_RW(s, buf1)); +#endif flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); /* Deduct the prologue from the buffer. */ @@ -4267,6 +4279,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -2; } +#if defined(CONFIG_IOS_JIT) + /* flush data cache on mirror */ + flush_dcache_range((uintptr_t)TCG_CODE_PTR_RW(s, s->code_buf), + (uintptr_t)TCG_CODE_PTR_RW(s, s->code_ptr)); +#endif + /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..133213be3a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -369,7 +369,7 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { }; #endif -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { /* tcg_out_reloc always uses the same type, addend. */ @@ -377,9 +377,9 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, tcg_debug_assert(addend == 0); tcg_debug_assert(value != 0); if (TCG_TARGET_REG_BITS == 32) { - tcg_patch32(code_ptr, value); + tcg_patch32(s, code_ptr, value); } else { - tcg_patch64(code_ptr, value); + tcg_patch64(s, code_ptr, value); } return true; } @@ -545,7 +545,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr = s->code_ptr; tcg_out_op_t(s, INDEX_op_call); diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..2a258ea350 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -195,6 +195,12 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +#if defined(CONFIG_IOS_JIT) +static inline void flush_dcache_range(uintptr_t start, uintptr_t stop) +{ +} +#endif + /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. We prefer consistency across hosts on this. */ @@ -203,7 +209,8 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) + uintptr_t jmp_addr, uintptr_t addr, + uintptr_t wr_addr) { /* patch the branch destination */ qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); From patchwork Mon Oct 12 23:29:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 845B31592 for ; Tue, 13 Oct 2020 00:59:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E907218AC for ; Tue, 13 Oct 2020 00:59:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2E907218AC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=getutm.app Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:59936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kS8ef-0004FB-9j for patchwork-qemu-devel@patchwork.kernel.org; Mon, 12 Oct 2020 20:59:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kS7Gf-0001ne-2r for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:13 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:39619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kS7GM-00061n-2i for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:12 -0400 Received: by mail-pl1-f194.google.com with SMTP id y1so6064556plp.6 for ; Mon, 12 Oct 2020 16:29:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jq5S7DfTMucYeMtF3v3i8XupTbrbwTvgXcH0YvcLue8=; b=t0djxunai7uHfuWWEGuGRTnQHK/NSTV0ZAmlCkymkFB90QKlZHgUKQ6m6+wVFcgMnu sv+/cA3p8fEYFZShJgQ1Neupmoq8FIGw/sOORvhZCd086m5CpJDDwZARepXyMzC2GTL+ 6OFkuTjh+nuAC5BvI4iSmF62Xbspo0UgsiA7VRrRK6rCKnrbj4gm1O89765H0x4wk5PC yNMygRc2VrxbXxfPq0TJAZmBkNW3sW9HqWsqNrjIWbkl3lJqmkOGuRh5dZDyyEEdpm5C /Xt1WtT1sjJ/hqUKiwQ8ZZ7kN17GpMe58fWnBtPnABMhsENd8+IjY6dAQpV6Tg+pTk21 eXAQ== X-Gm-Message-State: AOAM531xaSXqC+DNPvzkxGBm1oiMXAaSR7IDqhIgF/lveSJeitHdaC9q RzqRnQ6PhiV9znMTrlqn8TgcGTrSjRU= X-Google-Smtp-Source: ABdhPJwN2gtfkGFrH9T9aHyT7uUvFnAICHRx3gJ9YXHNZ2wwz1TfjktlW19IOcvnl8opxGqX5EHTAA== X-Received: by 2002:a17:902:6ac1:b029:d3:b4c9:e92f with SMTP id i1-20020a1709026ac1b02900d3b4c9e92fmr24641978plt.38.1602545392485; Mon, 12 Oct 2020 16:29:52 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.51 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:52 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 08/10] tcg: mirror mapping RWX pages for iOS optional Date: Mon, 12 Oct 2020 16:29:37 -0700 Message-Id: <20201012232939.48481-9-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.194; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f194.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:53 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Laurent Vivier , Joelle van Dyne , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy This allows jailbroken devices with entitlements to switch the option off. Signed-off-by: Joelle van Dyne --- accel/tcg/tcg-all.c | 27 +++++++++++++++++- accel/tcg/translate-all.c | 60 +++++++++++++++++++++++++-------------- bsd-user/main.c | 2 +- include/sysemu/tcg.h | 2 +- linux-user/main.c | 2 +- qemu-options.hx | 11 +++++++ 6 files changed, 79 insertions(+), 25 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index fa1208158f..5845744396 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -39,6 +39,7 @@ struct TCGState { bool mttcg_enabled; unsigned long tb_size; + bool mirror_rwx; }; typedef struct TCGState TCGState; @@ -94,6 +95,7 @@ static void tcg_accel_instance_init(Object *obj) TCGState *s = TCG_STATE(obj); s->mttcg_enabled = default_mttcg_enabled(); + s->mirror_rwx = false; } bool mttcg_enabled; @@ -102,7 +104,7 @@ static int tcg_init(MachineState *ms) { TCGState *s = TCG_STATE(current_accel()); - tcg_exec_init(s->tb_size * 1024 * 1024); + tcg_exec_init(s->tb_size * 1024 * 1024, s->mirror_rwx); mttcg_enabled = s->mttcg_enabled; cpus_register_accel(&tcg_cpus); @@ -168,6 +170,22 @@ static void tcg_set_tb_size(Object *obj, Visitor *v, s->tb_size = value; } +#ifdef CONFIG_IOS_JIT +static bool tcg_get_mirror_rwx(Object *obj, Error **errp) +{ + TCGState *s = TCG_STATE(obj); + + return s->mirror_rwx; +} + +static void tcg_set_mirror_rwx(Object *obj, bool value, Error **errp) +{ + TCGState *s = TCG_STATE(obj); + + s->mirror_rwx = value; +} +#endif + static void tcg_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); @@ -185,6 +203,13 @@ static void tcg_accel_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "tb-size", "TCG translation block cache size"); +#ifdef CONFIG_IOS_JIT + object_class_property_add_bool(oc, "mirror-rwx", + tcg_get_mirror_rwx, tcg_set_mirror_rwx); + object_class_property_set_description(oc, "mirror-rwx", + "mirror map executable pages for TCG on iOS"); +#endif + } static const TypeInfo tcg_accel_type = { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 76d8dc3d7b..de9b7d9ab6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1043,12 +1043,15 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); -static inline void *alloc_code_gen_buffer(void) +static inline void *alloc_code_gen_buffer(bool no_rwx_pages) { void *buf = static_code_gen_buffer; void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); size_t size; + /* not applicable */ + assert(!no_rwx_pages); + /* page-align the beginning and end of the buffer */ buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); @@ -1077,24 +1080,32 @@ static inline void *alloc_code_gen_buffer(void) return buf; } #elif defined(_WIN32) -static inline void *alloc_code_gen_buffer(void) +static inline void *alloc_code_gen_buffer(bool no_rwx_pages) { size_t size = tcg_ctx->code_gen_buffer_size; + assert(!no_rwx_pages); /* not applicable */ return VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, PAGE_EXECUTE_READWRITE); } #else -static inline void *alloc_code_gen_buffer(void) +static inline void *alloc_code_gen_buffer(bool no_rwx_pages) { -#if defined(CONFIG_IOS_JIT) int prot = PROT_READ | PROT_EXEC; -#else - int prot = PROT_WRITE | PROT_READ | PROT_EXEC; -#endif int flags = MAP_PRIVATE | MAP_ANONYMOUS; size_t size = tcg_ctx->code_gen_buffer_size; void *buf; +#if defined(CONFIG_DARWIN) /* both iOS and macOS (Apple Silicon) applicable */ + if (!no_rwx_pages) { + prot |= PROT_WRITE; + flags |= MAP_JIT; + } +#else + /* not applicable */ + assert(!no_rwx_pages); + prot |= PROT_WRITE; +#endif + buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { return NULL; @@ -1174,10 +1185,10 @@ static inline void *alloc_jit_rw_mirror(void *base, size_t size) } #endif /* CONFIG_IOS_JIT */ -static inline void code_gen_alloc(size_t tb_size) +static inline void code_gen_alloc(size_t tb_size, bool mirror_rwx) { tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size); - tcg_ctx->code_gen_buffer = alloc_code_gen_buffer(); + tcg_ctx->code_gen_buffer = alloc_code_gen_buffer(mirror_rwx); if (tcg_ctx->code_gen_buffer == NULL) { fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); @@ -1185,13 +1196,18 @@ static inline void code_gen_alloc(size_t tb_size) #if defined(CONFIG_IOS_JIT) void *mirror; - /* For iOS JIT we need a mirror mapping for code execution */ - mirror = alloc_jit_rw_mirror(tcg_ctx->code_gen_buffer, - tcg_ctx->code_gen_buffer_size - ); - if (mirror == NULL) { - fprintf(stderr, "Could not remap code buffer mirror\n"); - exit(1); + if (mirror_rwx) { + /* For iOS JIT we need a mirror mapping for code execution */ + mirror = alloc_jit_rw_mirror(tcg_ctx->code_gen_buffer, + tcg_ctx->code_gen_buffer_size + ); + if (mirror == NULL) { + fprintf(stderr, "Could not remap code buffer mirror\n"); + exit(1); + } + } else { + /* If we have JIT entitlements */ + mirror = tcg_ctx->code_gen_buffer; } tcg_ctx->code_rw_mirror_diff = mirror - tcg_ctx->code_gen_buffer; #endif /* CONFIG_IOS_JIT */ @@ -1218,16 +1234,18 @@ static void tb_htable_init(void) qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode); } -/* Must be called before using the QEMU cpus. 'tb_size' is the size - (in bytes) allocated to the translation buffer. Zero means default - size. */ -void tcg_exec_init(unsigned long tb_size) +/* + * Must be called before using the QEMU cpus. 'tb_size' is the size + * (in bytes) allocated to the translation buffer. Zero means default + * size. mirror_rwx only applicable on iOS. + */ +void tcg_exec_init(unsigned long tb_size, bool mirror_rwx) { tcg_allowed = true; cpu_gen_init(); page_init(); tb_htable_init(); - code_gen_alloc(tb_size); + code_gen_alloc(tb_size, mirror_rwx); #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ diff --git a/bsd-user/main.c b/bsd-user/main.c index ac40d79bfa..ffd4888a26 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -910,7 +910,7 @@ int main(int argc, char **argv) } /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + tcg_exec_init(0, false); cpu_type = parse_cpu_option(cpu_model); cpu = cpu_create(cpu_type); diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index d9d3ca8559..569f90b11d 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -8,7 +8,7 @@ #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H -void tcg_exec_init(unsigned long tb_size); +void tcg_exec_init(unsigned long tb_size, bool mirror_rwx); #ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) diff --git a/linux-user/main.c b/linux-user/main.c index 75c9785157..3856b2611d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -705,7 +705,7 @@ int main(int argc, char **argv, char **envp) cpu_type = parse_cpu_option(cpu_model); /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + tcg_exec_init(0, false); cpu = cpu_create(cpu_type); env = cpu->env_ptr; diff --git a/qemu-options.hx b/qemu-options.hx index 1da52a269c..deb39d56f5 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -123,6 +123,9 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, " igd-passthru=on|off (enable Xen integrated Intel graphics passthrough, default=off)\n" " kernel-irqchip=on|off|split controls accelerated irqchip support (default=on)\n" " kvm-shadow-mem=size of KVM shadow MMU in bytes\n" +#ifdef CONFIG_IOS_JIT + " mirror-rwx=on|off (mirror map executable pages for TCG on iOS)\n" +#endif " tb-size=n (TCG translation block cache size)\n" " thread=single|multi (enable multi-threaded TCG)\n", QEMU_ARCH_ALL) SRST @@ -148,6 +151,14 @@ SRST ``kvm-shadow-mem=size`` Defines the size of the KVM shadow MMU. +#ifdef CONFIG_IOS_JIT + + ``mirror-rwx=on|off`` + Only applicable to TCG running on iOS hosts. When enabled, TB code + is written to a mirror mapped address separate from the address that is + executed. By default, this is disabled. +#endif + ``tb-size=n`` Controls the size (in MiB) of the TCG translation block cache. From patchwork Mon Oct 12 23:29:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834679 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F3A18697 for ; Tue, 13 Oct 2020 01:12:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8AD5420870 for ; Tue, 13 Oct 2020 01:12:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8AD5420870 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=getutm.app Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:34004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kS8rB-0000gC-Ko for patchwork-qemu-devel@patchwork.kernel.org; Mon, 12 Oct 2020 21:12:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kS7Gh-0001oS-7C for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:15 -0400 Received: from mail-pl1-f170.google.com ([209.85.214.170]:35906) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kS7GN-000621-EB for qemu-devel@nongnu.org; Mon, 12 Oct 2020 19:30:14 -0400 Received: by mail-pl1-f170.google.com with SMTP id w21so6828165plq.3 for ; Mon, 12 Oct 2020 16:29:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g46hQzXfYsVfDOAEjWsJ5/ziWAju7INePcqlbhhfRHU=; b=UJrBO1lI1xsC/fi7/iFDV177e0e7Upu6gbI8a8oh31ObD39tV16at0WD4e+YEC7DUy bmBdjF2UNNzRJuF/bghqBzuXFfkpA1BCAWFZRhHxjEvxVzX3zHJSABMav+sGwi5RgZ5F nWU5Vl83b0pmt//1JTtNwMUC4mnMwi/EGX2ypewp5IkiYqqf/KJWtGeSwyue7SYahyhI VwbzdbtBqQtL4mtpaLG45YRkMKlSwmexeRXcFFCmMcD+Izhbg4ELiEueeNb/VVWiShQI oeLCIp8VExPiAEq+k2S/wO/KzGKIZtfLUklE46aw/+SiTcTqdOrjPonVedBaSMJA7205 R4Eg== X-Gm-Message-State: AOAM533fHFmJdBjWniL4gGTwIip8ZMJtyeIkBjUCV/uq22qzvdOn1DYR ATlsfFbeEqFRpGf6A6uaSYaIGcH22bU= X-Google-Smtp-Source: ABdhPJwA4IABniys11eyN6yvhiuOU/Z0ACncgHjY2JIiUAwS0aQ8T6yyXjCBejilCXI8a4c3eytDjQ== X-Received: by 2002:a17:902:7441:b029:d3:eaa4:8f35 with SMTP id e1-20020a1709027441b02900d3eaa48f35mr26156674plt.74.1602545393736; Mon, 12 Oct 2020 16:29:53 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:53 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 09/10] tcg: support JIT on Apple Silicon Date: Mon, 12 Oct 2020 16:29:38 -0700 Message-Id: <20201012232939.48481-10-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.170; envelope-from=osy86dev@gmail.com; helo=mail-pl1-f170.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:54 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Joelle van Dyne , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon For < iOS 14, reverse engineered functions from libsystem_pthread.dylib is implemented to handle APRR supported SoCs. The following rules apply for JIT write protect: * JIT write-protect is enabled before tcg_qemu_tb_exec() * JIT write-protect is disabled after tcg_qemu_tb_exec() returns * JIT write-protect is disabled inside do_tb_phys_invalidate() but if it is called inside of tcg_qemu_tb_exec() then write-protect will be enabled again before returning. * JIT write-protect is disabled by cpu_loop_exit() for interrupt handling. * JIT write-protect is disabled everywhere else. Signed-off-by: Joelle van Dyne --- accel/tcg/cpu-exec-common.c | 2 + accel/tcg/cpu-exec.c | 2 + accel/tcg/translate-all.c | 51 ++++++++++++++++++++++ configure | 20 +++++++++ include/exec/exec-all.h | 2 + include/tcg/tcg-apple-jit.h | 85 +++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 3 ++ tcg/tcg.c | 4 ++ 8 files changed, 169 insertions(+) create mode 100644 include/tcg/tcg-apple-jit.h diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 12c1e3e974..f1eb767b02 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -64,6 +64,8 @@ void cpu_reloading_memory_map(void) void cpu_loop_exit(CPUState *cpu) { + /* Unlock JIT write protect if applicable. */ + tb_exec_unlock(); /* Undo the setting in cpu_tb_exec. */ cpu->can_do_io = 1; siglongjmp(cpu->jmp_env, 1); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 821aefdea2..d00d17f3c6 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -175,7 +175,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) } #endif /* DEBUG_DISAS */ + tb_exec_lock(); ret = tcg_qemu_tb_exec(env, tb_ptr); + tb_exec_unlock(); cpu->can_do_io = 1; last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); tb_exit = ret & TB_EXIT_MASK; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index de9b7d9ab6..98daabbfc0 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -27,6 +27,9 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg.h" +#if defined(CONFIG_DARWIN) +#include "tcg/tcg-apple-jit.h" +#endif #if defined(CONFIG_USER_ONLY) #include "qemu.h" #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) @@ -76,6 +79,9 @@ extern kern_return_t mach_vm_remap(vm_map_t target_task, ); #endif +static bool tb_exec_is_locked(void); +static void tb_exec_change(bool locked); + /* #define DEBUG_TB_INVALIDATE */ /* #define DEBUG_TB_FLUSH */ /* make various TB consistency checks */ @@ -1246,6 +1252,7 @@ void tcg_exec_init(unsigned long tb_size, bool mirror_rwx) page_init(); tb_htable_init(); code_gen_alloc(tb_size, mirror_rwx); + tb_exec_unlock(); #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ @@ -1522,8 +1529,11 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) PageDesc *p; uint32_t h; tb_page_addr_t phys_pc; + bool code_gen_locked; assert_memory_lock(); + code_gen_locked = tb_exec_is_locked(); + tb_exec_unlock(); /* make sure no further incoming jumps will be chained to this TB */ qemu_spin_lock(&tb->jmp_lock); @@ -1536,6 +1546,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) tb->trace_vcpu_dstate); if (!(tb->cflags & CF_NOCACHE) && !qht_remove(&tb_ctx.htable, tb, h)) { + tb_exec_change(code_gen_locked); return; } @@ -1568,6 +1579,8 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) qatomic_set(&tcg_ctx->tb_phys_invalidate_count, tcg_ctx->tb_phys_invalidate_count + 1); + + tb_exec_change(code_gen_locked); } static void tb_phys_invalidate__locked(TranslationBlock *tb) @@ -2808,3 +2821,41 @@ void tcg_flush_softmmu_tlb(CPUState *cs) tlb_flush(cs); #endif } + +#if defined(CONFIG_DARWIN) && !defined(CONFIG_TCG_INTERPRETER) +static bool tb_exec_is_locked(void) +{ + return tcg_ctx->code_gen_locked; +} + +static void tb_exec_change(bool locked) +{ +#if defined(HAVE_PTHREAD_JIT_PROTECT) + if (__builtin_available(macOS 11, iOS 14, watchOS 7, tvOS 14, *)) { + pthread_jit_write_protect_np(locked); + } else +#endif + if (jit_write_protect_supported()) { + jit_write_protect(locked); + } + tcg_ctx->code_gen_locked = locked; +} +#else /* not needed on non-Darwin platforms */ +static bool tb_exec_is_locked(void) +{ + return false; +} + +static void tb_exec_change(bool locked) {} +#endif + +void tb_exec_lock(void) +{ + /* assumes sys_icache_invalidate already called */ + tb_exec_change(true); +} + +void tb_exec_unlock(void) +{ + tb_exec_change(false); +} diff --git a/configure b/configure index c5a6584683..4c8cb63670 100755 --- a/configure +++ b/configure @@ -5874,6 +5874,22 @@ but not implemented on your system" fi fi +########################################## +# check for Apple Silicon JIT function + +if [ "$darwin" = "yes" ] ; then + cat > $TMPC << EOF +#include +int main() { pthread_jit_write_protect_np(0); return 0; } +EOF + if ! compile_prog ""; then + have_pthread_jit_protect='no' + else + have_pthread_jit_protect='yes' + fi +fi + + ########################################## # End of CC checks # After here, no more $cc or $ld runs @@ -6994,6 +7010,10 @@ if test "$secret_keyring" = "yes" ; then echo "CONFIG_SECRET_KEYRING=y" >> $config_host_mak fi +if test "$have_pthread_jit_protect" = "yes" ; then + echo "HAVE_PTHREAD_JIT_PROTECT=y" >> $config_host_mak +fi + if test "$tcg_interpreter" = "yes"; then QEMU_INCLUDES="-iquote ${source_path}/tcg/tci $QEMU_INCLUDES" elif test "$ARCH" = "sparc64" ; then diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2db155a772..253af30a2e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -521,6 +521,8 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, uint32_t cf_mask); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); +void tb_exec_lock(void); +void tb_exec_unlock(void); /* GETPC is the true target of the return instruction that we'll execute. */ #if defined(CONFIG_TCG_INTERPRETER) diff --git a/include/tcg/tcg-apple-jit.h b/include/tcg/tcg-apple-jit.h new file mode 100644 index 0000000000..1e70bf3afe --- /dev/null +++ b/include/tcg/tcg-apple-jit.h @@ -0,0 +1,85 @@ +/* + * Apple Silicon APRR functions for JIT handling + * + * Copyright (c) 2020 osy + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * Credits to: https://siguza.github.io/APRR/ + * Reversed from /usr/lib/system/libsystem_pthread.dylib + */ + +#ifndef TCG_APPLE_JIT_H +#define TCG_APPLE_JIT_H + +#if defined(__aarch64__) && defined(CONFIG_DARWIN) + +#define _COMM_PAGE_START_ADDRESS (0x0000000FFFFFC000ULL) /* In TTBR0 */ +#define _COMM_PAGE_APRR_SUPPORT (_COMM_PAGE_START_ADDRESS + 0x10C) +#define _COMM_PAGE_APPR_WRITE_ENABLE (_COMM_PAGE_START_ADDRESS + 0x110) +#define _COMM_PAGE_APRR_WRITE_DISABLE (_COMM_PAGE_START_ADDRESS + 0x118) + +static __attribute__((__always_inline__)) bool jit_write_protect_supported(void) +{ + /* Access shared kernel page at fixed memory location. */ + uint8_t aprr_support = *(volatile uint8_t *)_COMM_PAGE_APRR_SUPPORT; + return aprr_support > 0; +} + +/* write protect enable = write disable */ +static __attribute__((__always_inline__)) void jit_write_protect(int enabled) +{ + /* Access shared kernel page at fixed memory location. */ + uint8_t aprr_support = *(volatile uint8_t *)_COMM_PAGE_APRR_SUPPORT; + if (aprr_support == 0 || aprr_support > 3) { + return; + } else if (aprr_support == 1) { + __asm__ __volatile__ ( + "mov x0, %0\n" + "ldr x0, [x0]\n" + "msr S3_4_c15_c2_7, x0\n" + "isb sy\n" + :: "r" (enabled ? _COMM_PAGE_APRR_WRITE_DISABLE + : _COMM_PAGE_APPR_WRITE_ENABLE) + : "memory", "x0" + ); + } else { + __asm__ __volatile__ ( + "mov x0, %0\n" + "ldr x0, [x0]\n" + "msr S3_6_c15_c1_5, x0\n" + "isb sy\n" + :: "r" (enabled ? _COMM_PAGE_APRR_WRITE_DISABLE + : _COMM_PAGE_APPR_WRITE_ENABLE) + : "memory", "x0" + ); + } +} + +#else /* defined(__aarch64__) && defined(CONFIG_DARWIN) */ + +static __attribute__((__always_inline__)) bool jit_write_protect_supported(void) +{ + return false; +} + +static __attribute__((__always_inline__)) void jit_write_protect(int enabled) +{ +} + +#endif + +#endif /* define TCG_APPLE_JIT_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 40d1a7a85e..fbe00af4e1 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -630,6 +630,9 @@ struct TCGContext { #if defined(CONFIG_IOS_JIT) ptrdiff_t code_rw_mirror_diff; #endif +#if defined(CONFIG_DARWIN) && !defined(CONFIG_TCG_INTERPRETER) + bool code_gen_locked; /* on Darwin each thread tracks W^X flags */ +#endif /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; diff --git a/tcg/tcg.c b/tcg/tcg.c index ef203a34a6..244a0a43bf 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -781,6 +781,8 @@ static void alloc_tcg_plugin_context(TCGContext *s) void tcg_register_thread(void) { tcg_ctx = &tcg_init_ctx; + + tb_exec_unlock(); } #else void tcg_register_thread(void) @@ -815,6 +817,8 @@ void tcg_register_thread(void) err = tcg_region_initial_alloc__locked(tcg_ctx); g_assert(!err); qemu_mutex_unlock(®ion.lock); + + tb_exec_unlock(); } #endif /* !CONFIG_USER_ONLY */ From patchwork Mon Oct 12 23:29:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joelle van Dyne X-Patchwork-Id: 11834671 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D25A175A for ; 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Mon, 12 Oct 2020 16:29:54 -0700 (PDT) Received: from localhost.localdomain ([73.93.152.174]) by smtp.gmail.com with ESMTPSA id f21sm8088315pfk.169.2020.10.12.16.29.53 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Oct 2020 16:29:54 -0700 (PDT) From: Joelle van Dyne To: qemu-devel@nongnu.org Subject: [PATCH 10/10] block: check availablity for preadv/pwritev on mac Date: Mon, 12 Oct 2020 16:29:39 -0700 Message-Id: <20201012232939.48481-11-j@getutm.app> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012232939.48481-1-j@getutm.app> References: <20201012232939.48481-1-j@getutm.app> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.196; envelope-from=osy86dev@gmail.com; helo=mail-pf1-f196.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/12 19:29:55 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 12 Oct 2020 20:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Joelle van Dyne , "open list:raw" , Max Reitz Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: osy macOS 11/iOS 14 added preadv/pwritev APIs. Due to weak linking, configure will succeed with CONFIG_PREADV even when targeting a lower OS version. We therefore need to check at run time if we can actually use these APIs. Signed-off-by: Joelle van Dyne --- block/file-posix.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/block/file-posix.c b/block/file-posix.c index cdc73b5f1d..d7482036a3 100644 --- a/block/file-posix.c +++ b/block/file-posix.c @@ -1393,12 +1393,24 @@ static bool preadv_present = true; static ssize_t qemu_preadv(int fd, const struct iovec *iov, int nr_iov, off_t offset) { +#ifdef CONFIG_DARWIN /* preadv introduced in macOS 11 */ + if (!__builtin_available(macOS 11, iOS 14, watchOS 7, tvOS 14, *)) { + preadv_present = false; + return -ENOSYS; + } else +#endif return preadv(fd, iov, nr_iov, offset); } static ssize_t qemu_pwritev(int fd, const struct iovec *iov, int nr_iov, off_t offset) { +#ifdef CONFIG_DARWIN /* pwritev introduced in macOS 11 */ + if (!__builtin_available(macOS 11, iOS 14, watchOS 7, tvOS 14, *)) { + preadv_present = false; + return -ENOSYS; + } else +#endif return pwritev(fd, iov, nr_iov, offset); }