From patchwork Wed Oct 21 02:55:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11848187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B99AF1580 for ; Wed, 21 Oct 2020 02:55:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2D4B2224E for ; Wed, 21 Oct 2020 02:55:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2411428AbgJUCzS (ORCPT ); Tue, 20 Oct 2020 22:55:18 -0400 Received: from mga18.intel.com ([134.134.136.126]:30398 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2411425AbgJUCzS (ORCPT ); Tue, 20 Oct 2020 22:55:18 -0400 IronPort-SDR: t2lJt3/qyMxWk1+Wt4H6jKhZkw6QCzvSOyR7++ef0lRyE5ykDxPa3HknTMGS/4NMOujMOf1O+y Oo1MqmLgWewQ== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="155092204" X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="155092204" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 19:55:17 -0700 IronPort-SDR: LzXMk1kv2jLAvG2gjlDiMCIVKJMVlv5vanJfBSe4oez5Hvd3QZxBs32fy6PaWcCIk389oBtfgL JXzR0DN6wreQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="301940988" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga007.fm.intel.com with ESMTP; 20 Oct 2020 19:55:14 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v2 1/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC Date: Wed, 21 Oct 2020 10:55:02 +0800 Message-Id: <20201021025507.51001-2-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add QSPI controller support for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/Kconfig | 2 +- drivers/spi/spi-cadence-quadspi.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d2c976e55b8b..926da61eee5a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -203,7 +203,7 @@ config SPI_CADENCE config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || COMPILE_TEST) + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST) help Enable support for the Cadence Quad SPI Flash controller. diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 40938cf3806d..d7b10c46fa70 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "ti,am654-ospi", .data = &am654_ospi, }, + { + .compatible = "intel,lgm-qspi", + }, { /* end of table */ } }; From patchwork Wed Oct 21 02:55:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11848189 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 112C514B7 for ; Wed, 21 Oct 2020 02:55:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00FEF2224E for ; Wed, 21 Oct 2020 02:55:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2411439AbgJUCzX (ORCPT ); Tue, 20 Oct 2020 22:55:23 -0400 Received: from mga11.intel.com ([192.55.52.93]:13102 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2411425AbgJUCzV (ORCPT ); Tue, 20 Oct 2020 22:55:21 -0400 IronPort-SDR: CyBlKc/MQFLyyLJFJJdSRcM/jj5/V/0IiE0Dd2lxSwhoK2HNrfo5WEz/y7+48FgOwMmN2VHbJU Pq/qxd7I4V3Q== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="163816067" X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="163816067" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 19:55:21 -0700 IronPort-SDR: kNCfmM3ws3QPZaRW3UUpCC/j+epIFogcpVdB1JnA0x4KiiT/TlnoI+57Chaa+R6zU/uxSdmlxn 0o0suuizLzAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="358745551" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by FMSMGA003.fm.intel.com with ESMTP; 20 Oct 2020 19:55:18 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC Date: Wed, 21 Oct 2020 10:55:03 +0800 Message-Id: <20201021025507.51001-3-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use Direct Access Controller(DAC). This patch adds a quirk to disable the Direct Access Controller for data transfer instead it uses indirect data transfer. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index d7b10c46fa70..3d017b484114 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + /* Disable direct access controller */ + if (!cqspi->use_direct_mode) { + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + } + cqspi_controller_enable(cqspi, 1); } @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = { .quirks = CQSPI_NEEDS_WR_DELAY, }; +static const struct cqspi_driver_platdata intel_lgm_qspi = { + .quirks = CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = { }, { .compatible = "intel,lgm-qspi", + .data = &intel_lgm_qspi, }, { /* end of table */ } }; From patchwork Wed Oct 21 02:55:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11848191 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B77C14B7 for ; Wed, 21 Oct 2020 02:55:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 610BE22251 for ; Wed, 21 Oct 2020 02:55:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2411411AbgJUCz3 (ORCPT ); Tue, 20 Oct 2020 22:55:29 -0400 Received: from mga18.intel.com ([134.134.136.126]:30406 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2411450AbgJUCz0 (ORCPT ); Tue, 20 Oct 2020 22:55:26 -0400 IronPort-SDR: BQ2L2obfg4lnxqWbIqvB/U4mSe6CT3sVQoeHLTw+p9F2N4Nwqr3QPb2IHrWXMUggaGuEQ9qlVy pp/b7jeWhbkw== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="155092213" X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="155092213" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 19:55:25 -0700 IronPort-SDR: FqDQEjs2WQ4KAoCyVEVES60mNnkc0AkvAVIPVfTaYfuWpnsZnzCKa9GT6xSCEC0aS6TTbZ3okz jPTXVhmAXF1A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="522595579" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga006.fm.intel.com with ESMTP; 20 Oct 2020 19:55:22 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Date: Wed, 21 Oct 2020 10:55:04 +0800 Message-Id: <20201021025507.51001-4-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 3d017b484114..3bf6d3697631 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -38,6 +38,7 @@ /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1) struct cqspi_st; @@ -75,6 +76,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (!cqspi->use_direct_mode) { + if (of_property_read_u32(np, "num-chipselect", + &cqspi->num_chipselect)) { + dev_err(dev, "couldn't determine number of cs\n"); + return -ENXIO; + } + } + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); @@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = { }; static const struct cqspi_driver_platdata intel_lgm_qspi = { + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT, .quirks = CQSPI_DISABLE_DAC_MODE, }; From patchwork Wed Oct 21 02:55:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11848197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0137D14B7 for ; Wed, 21 Oct 2020 02:55:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E06E92224E for ; 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20 Oct 2020 19:55:26 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v2 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Date: Wed, 21 Oct 2020 10:55:05 +0800 Message-Id: <20201021025507.51001-5-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan Acked-by: Rob Herring --- Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (100%) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt similarity index 100% rename from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt rename to Documentation/devicetree/bindings/spi/cadence-quadspi.txt From patchwork Wed Oct 21 02:55:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11848193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D9D714B7 for ; Wed, 21 Oct 2020 02:55:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 73AB72242E for ; Wed, 21 Oct 2020 02:55:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2411477AbgJUCzf (ORCPT ); Tue, 20 Oct 2020 22:55:35 -0400 Received: from mga01.intel.com ([192.55.52.88]:14455 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2411454AbgJUCze (ORCPT ); Tue, 20 Oct 2020 22:55:34 -0400 IronPort-SDR: mghJNXQvoZLATHlY7KnCdIy+6/1dOrYMw+iPwbsa72nMWvVjvTWASVHODJngRKGgxyj/932dYn utBAkhM2bf2g== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="184957171" X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="184957171" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 19:55:34 -0700 IronPort-SDR: 1xctb7fjAaGZN+83tMAGQ/DxPm0ttMCH9RMVp+/xiwZEbQncPGbUhZelG6rW1ZqD5rSo2Ktwfq 4NyyQUqMJSLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="348436519" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga008.jf.intel.com with ESMTP; 20 Oct 2020 19:55:30 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Date: Wed, 21 Oct 2020 10:55:06 +0800 Message-Id: <20201021025507.51001-6-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan --- .../devicetree/bindings/spi/cadence-quadspi.txt | 67 ---------- .../devicetree/bindings/spi/cadence-quadspi.yaml | 148 +++++++++++++++++++++ 2 files changed, 148 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt deleted file mode 100644 index 945be7d5b236..000000000000 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include either "qspi" and/or "qspi-ocp". - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml new file mode 100644 index 000000000000..57be1a730e7b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence Quad SPI controller + +maintainers: + - Vadivel Murugan + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + oneOf: + - items: + - const: cdns,qspi-nor + - const: ti,k2g-qspi, cdns,qspi-nor + - const: ti,am654-ospi, cdns,qspi-nor + + reg: + items: + - description: the controller register set + - description: the controller data area + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cdns,fifo-depth: + description: + Size of the data FIFO in words. + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [ 128, 256 ] + default: 128 + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bus width of the data FIFO in bytes. + default: 4 + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 32-bit indirect AHB trigger address. + + cdns,is-decoded-cs: + type: boolean + description: + Flag to indicate whether decoder is used or not. + + cdns,rclk-en: + type: boolean + description: + Flag to indicate that QSPI return clock is used to latch the read + data rather than the QSPI clock. Make sure that QSPI return clock + is populated on the board before using this property. + + resets: + maxItems : 2 + + reset-names: + minItems: 1 + maxItems: 2 + items: + enum: [ qspi, qspi-ocp ] + +# subnode's properties +patternProperties: + "@[0-9a-f]+$": + type: object + description: + flash device uses the subnodes below defined properties. + + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay for read capture logic, in clock cycles. + + cdns,tshsl-ns: + description: | + Delay in nanoseconds for the length that the master mode chip select + outputs are de-asserted between transactions. + + cdns,tsd2d-ns: + description: | + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + description: | + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + description: | + Delay in nanoseconds between setting qspi_n_ss_out low and + first bit transfer. + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + - cdns,is-decoded-cs + - cdns,rclk-en + - resets + - reset-names + +additionalProperties: false + +examples: + - | + qspi: spi@ff705000 { + compatible = "cadence,qspi","cdns,qpsi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst 0x1>, <&rst 0x2>; + reset-names = "qspi", "qspi-ocp"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + + }; + +... From patchwork Wed Oct 21 02:55:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11848195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 359B91580 for ; Wed, 21 Oct 2020 02:55:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2199B2224E for ; Wed, 21 Oct 2020 02:55:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2411495AbgJUCzm (ORCPT ); Tue, 20 Oct 2020 22:55:42 -0400 Received: from mga07.intel.com ([134.134.136.100]:25975 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2411487AbgJUCzi (ORCPT ); Tue, 20 Oct 2020 22:55:38 -0400 IronPort-SDR: 59BKMXXPqdlb/vAstq+t8vUszD6lA5BE35vvfrzjb4av51kKuyUsqRn83dJrh2ra9hlKTIZ2Yd dYwcwGbdn2wg== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="231499863" X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="231499863" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 19:55:38 -0700 IronPort-SDR: 70LGWsdaXU9n0iKhNqL2yXLYMd62wnMaW3vpwUWPiJReJC+zR5jtirxO20DWcnIn8poR3/F/tU E7AU+TdlDH5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,400,1596524400"; d="scan'208";a="320871854" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga006.jf.intel.com with ESMTP; 20 Oct 2020 19:55:34 -0700 From: "Ramuthevar,Vadivel MuruganX" To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v2 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Date: Wed, 21 Oct 2020 10:55:07 +0800 Message-Id: <20201021025507.51001-7-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201021025507.51001-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add compatible string for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml index 57be1a730e7b..44378d2d2b9e 100644 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -19,6 +19,7 @@ properties: - const: cdns,qspi-nor - const: ti,k2g-qspi, cdns,qspi-nor - const: ti,am654-ospi, cdns,qspi-nor + - const: intel,lgm-qspi, cdns,qspi-nor reg: items: