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Fri, 23 Oct 2020 17:14:54 +0800 From: Miles Chen To: Catalin Marinas , Russell King , Minchan Kim Subject: [PATCH v2 1/4] arm: mm: use strict p[gum]d types Date: Fri, 23 Oct 2020 17:14:34 +0800 Message-ID: <20201023091437.8225-2-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com> References: <20201023091437.8225-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_052722_301200_023E12E1 X-CRM114-Status: GOOD ( 14.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Miles Chen , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When use mm/gup.c, it is necessary to use strict p*d types. Otherwise, we will get build breaks such as: mm/gup.c:2589:9: error: incompatible pointer types passing 'pmdval_t **' (aka 'unsigned int **') to parameter of type 'pgd_t *' (aka 'pmdval_t (*)[2]') [-Werror,-Wincompatible-pointer-types] mm/gup.c:2616:9: error: array initializer must be an initializer list Fix some types errors in fixmap.h after using strict types. Cc: Russell King Cc: Catalin Marinas Cc: Minchan Kim Cc: Suren Baghdasaryan Signed-off-by: Miles Chen --- arch/arm/include/asm/fixmap.h | 6 ++--- arch/arm/include/asm/pgtable-2level-types.h | 26 --------------------- arch/arm/include/asm/pgtable-2level.h | 1 + 3 files changed, 4 insertions(+), 29 deletions(-) diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h index fc56fc3e1931..3ea12b2da708 100644 --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -42,11 +42,11 @@ static const enum fixed_addresses __end_of_fixed_addresses = #define FIXMAP_PAGE_COMMON (L_PTE_YOUNG | L_PTE_PRESENT | L_PTE_XN | L_PTE_DIRTY) -#define FIXMAP_PAGE_NORMAL (pgprot_kernel | L_PTE_XN) -#define FIXMAP_PAGE_RO (FIXMAP_PAGE_NORMAL | L_PTE_RDONLY) +#define FIXMAP_PAGE_NORMAL __pgprot(pgprot_val(pgprot_kernel) | L_PTE_XN) +#define FIXMAP_PAGE_RO __pgprot(pgprot_val(FIXMAP_PAGE_NORMAL) | L_PTE_RDONLY) /* Used by set_fixmap_(io|nocache), both meant for mapping a device */ -#define FIXMAP_PAGE_IO (FIXMAP_PAGE_COMMON | L_PTE_MT_DEV_SHARED | L_PTE_SHARED) +#define FIXMAP_PAGE_IO __pgprot(FIXMAP_PAGE_COMMON | L_PTE_MT_DEV_SHARED | L_PTE_SHARED) #define FIXMAP_PAGE_NOCACHE FIXMAP_PAGE_IO #define __early_set_fixmap __set_fixmap diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h index 650e793f4142..64fd5b8d9dc2 100644 --- a/arch/arm/include/asm/pgtable-2level-types.h +++ b/arch/arm/include/asm/pgtable-2level-types.h @@ -12,12 +12,6 @@ typedef u32 pteval_t; typedef u32 pmdval_t; -#undef STRICT_MM_TYPECHECKS - -#ifdef STRICT_MM_TYPECHECKS -/* - * These are used to make use of C type-checking.. - */ typedef struct { pteval_t pte; } pte_t; typedef struct { pmdval_t pmd; } pmd_t; typedef struct { pmdval_t pgd[2]; } pgd_t; @@ -32,24 +26,4 @@ typedef struct { pteval_t pgprot; } pgprot_t; #define __pmd(x) ((pmd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) -#else -/* - * .. while these make it easier on the compiler - */ -typedef pteval_t pte_t; -typedef pmdval_t pmd_t; -typedef pmdval_t pgd_t[2]; -typedef pteval_t pgprot_t; - -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgd_val(x) ((x)[0]) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgprot(x) (x) - -#endif /* STRICT_MM_TYPECHECKS */ - #endif /* _ASM_PGTABLE_2LEVEL_TYPES_H */ diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 3502c2f746ca..27a8635abea0 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -180,6 +180,7 @@ #define pud_none(pud) (0) #define pud_bad(pud) (0) #define pud_present(pud) (1) +#define pud_page(pud) pmd_page(__pmd(pud_val(pud))) #define pud_clear(pudp) do { } while (0) #define set_pud(pud,pudp) do { } while (0) From patchwork Fri Oct 23 09:14:35 2020 Content-Type: text/plain; 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b=t68cxbSnlk2HoqECMOoGY/tZevDiss5sfGYnQlnmWAiYR/0iacDkeaZ5H1RXip6oAYroxHOuYqCCtdpSOeaTANlwER32SNOgnRI8QUu1tEWyfmWMVTjKquAo6zlQANFynx1R3TApFFk+DIiTCk0lNe5PYk9ocx3YuLEXSaeWu9Q=; X-UUID: 01a91038ac3543aba470d7cde9358751-20201023 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 850186017; Fri, 23 Oct 2020 01:14:58 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 02:14:56 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 17:14:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 17:14:54 +0800 From: Miles Chen To: Catalin Marinas , Russell King , Minchan Kim Subject: [PATCH v2 2/4] arm: mm: reordering memory type table Date: Fri, 23 Oct 2020 17:14:35 +0800 Message-ID: <20201023091437.8225-3-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com> References: <20201023091437.8225-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 39A6E743CB437B5F42C75816813A91AAC33538F9F78B64AC671EE6541AB26FFA2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_052731_342641_50C90F73 X-CRM114-Status: GOOD ( 17.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , wsd_upstream@mediatek.com, Will Deacon , linux-kernel@vger.kernel.org, Miles Chen , Simon Horman , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Minchan Kim To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. It seems we don't need 4 bits for the memory type with ARMv6+. If it's true, let's reorder bits to make bit 5 free. We will use the bit for L_PTE_SPECIAL in next patch. A note from Catalin in [1]: " > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to > shared device in hardware. Looking through the arm32 code, it seems that > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile). " [1] https://lore.kernel.org/patchwork/patch/986574/ Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Steve Capper Cc: Simon Horman Cc: Minchan Kim Cc: Suren Baghdasaryan Signed-off-by: Minchan Kim Signed-off-by: Miles Chen --- arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++---- arch/arm/mm/proc-macros.S | 4 ++-- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 27a8635abea0..cdcd55cca37d 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -161,14 +161,27 @@ #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ +#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +/* + * On ARMv7 or ARMv7+LPAE, the non-shared and shared device types get + * mapped to the same TEX remapping index. On classic ARMv7, the + * shareability is controlled by the PRRR[17:16] field, indexed by + * L_PTE_SHARED. On ARMv7+LPAE the device mapping is always shareable. + */ +#define L_PTE_MT_DEV_NONSHARED L_PTE_MT_DEV_SHARED +#define L_PTE_MT_DEV_WC L_PTE_MT_BUFFERABLE +#define L_PTE_MT_DEV_CACHED L_PTE_MT_WRITEBACK +#define L_PTE_MT_MASK (_AT(pteval_t, 0x07) << 2) +#else #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ -#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */ -#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) +#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ +#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) +#endif #ifndef __ASSEMBLY__ diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index e2c743aa2eb2..dde1d6374250 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -137,7 +137,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long 0x00 @ unused + .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused @@ -147,7 +147,7 @@ .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED .long 0x00 @ unused .long 0x00 @ unused - .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS + .long 0x00 @ unused .endm .macro armv6_set_pte_ext pfx From patchwork Fri Oct 23 09:14:36 2020 Content-Type: text/plain; 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b=cbvsxBADek+rvwMG6nw5Cl1r9TQWXhoelUI++NbYbnZG5y7wboSjIEh8Heiu48V8DlH6SRcBUDM6FBVOziUGgi49VDgmPGYcyOqTDvA8H8yvvV8OZsq9KNdYb0GniXp7Hfvxgpk+m0QaOIuyhfsRdnWqCVSzTiQdO89edhrCqNc=; X-UUID: 93b0baf5a4034c79a4c618581ff9916f-20201023 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1981476347; Fri, 23 Oct 2020 01:14:58 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 02:14:56 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 17:14:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 17:14:54 +0800 From: Miles Chen To: Catalin Marinas , Russell King , Minchan Kim Subject: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL Date: Fri, 23 Oct 2020 17:14:36 +0800 Message-ID: <20201023091437.8225-4-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com> References: <20201023091437.8225-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_052724_900373_55EE228F X-CRM114-Status: GOOD ( 13.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , wsd_upstream@mediatek.com, Will Deacon , linux-kernel@vger.kernel.org, Miles Chen , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Minchan Kim This patch introduces L_PTE_SPECIAL and pte functions for supporting get_user_pages_fast. Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Steve Capper Cc: Minchan Kim Cc: Suren Baghdasaryan Signed-off-by: Minchan Kim Signed-off-by: Miles Chen --- arch/arm/Kconfig | 4 ++-- arch/arm/include/asm/pgtable-2level.h | 1 + arch/arm/include/asm/pgtable-3level.h | 6 ------ arch/arm/include/asm/pgtable.h | 13 +++++++++++++ 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c18fa9d382b7..1f75864b7c7a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -13,7 +13,7 @@ config ARM select ARCH_HAS_KCOV select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - select ARCH_HAS_PTE_SPECIAL if ARM_LPAE + select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K) select ARCH_HAS_PHYS_TO_DMA select ARCH_HAS_SETUP_DMA_OPS select ARCH_HAS_SET_MEMORY @@ -82,7 +82,7 @@ config ARM select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU select HAVE_EXIT_THREAD - select HAVE_FAST_GUP if ARM_LPAE + select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K) select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG select HAVE_FUNCTION_TRACER if !XIP_KERNEL diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index cdcd55cca37d..385e7a32394e 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -117,6 +117,7 @@ #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5) #define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) #define L_PTE_USER (_AT(pteval_t, 1) << 8) diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index fbb6693c3352..46fcc6725d3e 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -175,12 +175,6 @@ static inline pmd_t *pud_page_vaddr(pud_t pud) #define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID)) #define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF)) -#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL)) -static inline pte_t pte_mkspecial(pte_t pte) -{ - pte_val(pte) |= L_PTE_SPECIAL; - return pte; -} #define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY)) #define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY)) diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index c02f24400369..4092154ca779 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -195,6 +195,11 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) #define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY)) #define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG)) #define pte_exec(pte) (pte_isclear((pte), L_PTE_XN)) +#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL +#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL)) +#else +#define pte_special(pte) (0) +#endif #define pte_valid_user(pte) \ (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte)) @@ -274,6 +279,14 @@ static inline pte_t pte_mknexec(pte_t pte) return set_pte_bit(pte, __pgprot(L_PTE_XN)); } +#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL +static inline pte_t pte_mkspecial(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(L_PTE_SPECIAL)); +} +#else +static inline pte_t pte_mkspecial(pte_t pte) { return pte; } +#endif static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | From patchwork Fri Oct 23 09:14:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miles Chen X-Patchwork-Id: 11852619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64EC8C55178 for ; Fri, 23 Oct 2020 09:29:31 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E36A02192A for ; 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Fri, 23 Oct 2020 17:14:54 +0800 From: Miles Chen To: Catalin Marinas , Russell King , Minchan Kim Subject: [PATCH v2 4/4] arm: replace vector mem type with read-only type Date: Fri, 23 Oct 2020 17:14:37 +0800 Message-ID: <20201023091437.8225-5-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201023091437.8225-1-miles.chen@mediatek.com> References: <20201023091437.8225-1-miles.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E8A464A3D2B693A78F39320912CA98801136E8EB1B1EEC0E5212E5D3E01CC5D02000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_052721_859403_97732250 X-CRM114-Status: GOOD ( 19.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Miles Chen , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since kernel no longer writes to the vector, try to replace the vector mem type with read-only type and remove L_PTE_MT_VECTORS. from Catalin in [1]: " > I don't think this matters since the kernel no longer writes to the > vectors page at run-time but it needs cleaning up a bit (and testing in > case I missed something). IOW, do we still need a dedicated mapping type > for the vectors or we can simply use the read-only user page attributes? " [1] https://lore.kernel.org/patchwork/patch/986574/ Cc: Russell King Cc: Catalin Marinas Cc: Minchan Kim Cc: Suren Baghdasaryan Signed-off-by: Miles Chen --- arch/arm/include/asm/pgtable-2level.h | 1 - arch/arm/mm/mmu.c | 7 +++---- arch/arm/mm/proc-macros.S | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 385e7a32394e..438359d3675f 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -163,7 +163,6 @@ #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */ #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ #if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ab69250a86bc..0b6b377e2cce 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -536,12 +536,11 @@ static void __init build_mem_type_table(void) #ifndef CONFIG_ARM_LPAE /* - * We don't use domains on ARMv6 (since this causes problems with - * v6/v7 kernels), so we must use a separate memory type for user - * r/o, kernel r/w to map the vectors page. + * We no longer write to the vector pages ar run-time, to + * use read-only user page attribute for vector. */ if (cpu_arch == CPU_ARCH_ARMv6) - vecs_pgprot |= L_PTE_MT_VECTORS; + vecs_pgprot |= L_PTE_RDONLY; /* * Check is it with support for the PXN bit diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index dde1d6374250..f3e6551b4a7e 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -137,7 +137,7 @@ .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED - .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS + .long 0x00 @ unused .long 0x00 @ L_PTE_MT_MINICACHE (not present) .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC .long 0x00 @ unused