From patchwork Thu Nov 5 13:52:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 11884441 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29D05921 for ; Thu, 5 Nov 2020 13:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F04DE20739 for ; Thu, 5 Nov 2020 13:52:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JkuUCZh6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729992AbgKENwN (ORCPT ); Thu, 5 Nov 2020 08:52:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727275AbgKENwM (ORCPT ); Thu, 5 Nov 2020 08:52:12 -0500 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3A13C0613D2 for ; Thu, 5 Nov 2020 05:52:11 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id x12so1846127wrm.8 for ; Thu, 05 Nov 2020 05:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VhmVl6pKH58mc5ZE+7CUGBcwsFA40PZ3itcLExg+u5c=; b=JkuUCZh6IA5iY059NHQMyGdYhNZ+Hq/TJYeapKdolU41BkISmKJzkMe1fcsBbJ7W4v vLRmx7GcZPBuSTCzvnLvpu1/kKAhB2u/rjxzN4hNCqGvyYCknLpdqzdZ2NouZm/KAL7+ 9qtXGfOdKBzDxv5ROsX9kK+YmWaYNCNi/++n/eCScRvrZLKfnDDdH6fxuEf5p2gb/Fky nDJJnThz89Hb3NKsXrjCif0vuKozBeStlmfii4gQIgzjEVdbTyxmc+YmC4XZ/q2I1b5w NHRn4P54e+ZjcC8XcXE3uxde9GqBzu161eMa3z91lx//yd5A7stCJULbyjk95cJs2Fjn x6Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VhmVl6pKH58mc5ZE+7CUGBcwsFA40PZ3itcLExg+u5c=; b=QderWaCQ7VNVdbiJf6x/aGPZkzDv88qgs4fstLE0HkMI3OXI3ezwLrVwNpfHvuIptU qYkzMAPATzfXYGbHqdrcroF9CLiraSXDaPNZjrawFJCS2kf4q+y2DiT6Lwf5qn4C9VLw DhnXLqtmYtG5/nJOxxqUUqNA2gbuILFmQZmTaec+B7XuNm/+PmyVrfZ833jblgqgAdZI n1UHl33apaVY1IYkxER8HnMrDxmnlfoQj41Nxm1g5zFjhAW1WQbddIsv7NQ7/1njuWSg aDex2n9AKWjm1UHbVXQ6YeBhJxvdvl44d7U+ijru9cQEtULHF4KGXIb3OZPSZVpYMXYi syOA== X-Gm-Message-State: AOAM533Ml/r4W+5b9qVH0ApRAWAoiFYXcHZxBl9d5di1lrvzY6CyExNK thQK+NPtgOiL96+1wxTFDR6m8w== X-Google-Smtp-Source: ABdhPJwmvHKNJov/2BVpFq10F2Na1KUGphbOUkkN35QRPUo3OVpq2uebDe4i8Ol+uzRRutXK/6hgZQ== X-Received: by 2002:adf:f3c4:: with SMTP id g4mr3256609wrp.207.1604584330630; Thu, 05 Nov 2020 05:52:10 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id h4sm2648541wrq.3.2020.11.05.05.52.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Nov 2020 05:52:10 -0800 (PST) From: Georgi Djakov To: linux-pm@vger.kernel.org, bjorn.andersson@linaro.org, mdtipton@codeaurora.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, akashast@codeaurora.org, georgi.djakov@linaro.org Subject: [PATCH 1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports Date: Thu, 5 Nov 2020 15:52:09 +0200 Message-Id: <20201105135211.7160-1-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QUP ports exist in the topology, but are not exposed as an endpoints in DT. Fix this by creating IDs and attach them to their NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able to request their interconnect paths and scale their bandwidth. Signed-off-by: Georgi Djakov Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h index 290be38f40e6..67b500e24915 100644 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ b/include/dt-bindings/interconnect/qcom,sdm845.h @@ -19,6 +19,7 @@ #define SLAVE_A1NOC_SNOC 7 #define SLAVE_SERVICE_A1NOC 8 #define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 +#define MASTER_QUP_1 10 #define MASTER_A2NOC_CFG 0 #define MASTER_QDSS_BAM 1 @@ -32,6 +33,7 @@ #define SLAVE_A2NOC_SNOC 9 #define SLAVE_ANOC_PCIE_SNOC 10 #define SLAVE_SERVICE_A2NOC 11 +#define MASTER_QUP_2 12 #define MASTER_SPDM 0 #define MASTER_TIC 1 From patchwork Thu Nov 5 13:52:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 11884443 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F20BC15E6 for ; Thu, 5 Nov 2020 13:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C846E22228 for ; Thu, 5 Nov 2020 13:52:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JFSJapFs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727275AbgKENwN (ORCPT ); Thu, 5 Nov 2020 08:52:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730461AbgKENwN (ORCPT ); Thu, 5 Nov 2020 08:52:13 -0500 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20923C0613D2 for ; Thu, 5 Nov 2020 05:52:13 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id x7so1867163wrl.3 for ; Thu, 05 Nov 2020 05:52:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=78Yqfg/j79d9NNkXhCSDFD9fF8BplsRrEs56vasrB44=; b=JFSJapFsRo6fFsFNT5fq3w8nSjl4V+HnuwbE7ug9ngodKD0vduSY+0kui8DwmjtAPJ kuDolIsvGEJeALyCIBBKgsqVPOqjVyHROxbcYLY7+FxTk/hWaXgWQF4gxBp4m7jPPu/e V/wGGsC0G9QRt/fJF94Ey4675nYZViP77HuFt7BecddqP4nIOBARYYXi7Rj18BQ852ZX OcXBaznuft+Xyhfj5bo2NlAf2dr9C1Gb4MzntpvHJluLC0rzQ1C7vuXARFE0lu8fU/3D L9+zpZ3/bJ2L6Z7VCZRzR0Hur4Y4CV2E21NVkSdslSMKvKzu/BlwARcduggTxTSp7ZEo ERIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=78Yqfg/j79d9NNkXhCSDFD9fF8BplsRrEs56vasrB44=; b=FRgI6DEryFJ0oATDYi+wXNL9q0pIi87M0HxXCJJ2et0ib2fBN0bhcssO8e0e0zL4Mt 2IdMzCH+pbO9hJiJM/VkN8WFxl4Ow+6QhHTec1CJj+a2Ez8/iC8MAYUzSS36fFVRCP/g 5WpbFT77GCRgTcaeTZJ0prs8s1PQcOz/Clk9iGg8Ee7M7V5wjiLAiZ+aO2aQKKjJTItK znra92x4Eprzc6GrDdMzHtX/ylt2KqyhdVi1SYHwZp9o5OKlLOixS1XJDXCPa0+XM5ZD znL9APRRysA1gkKMnwEf6+v8QVSsMhM+XHu4lbvUi3WoGwAc+RwCahoeUEwZMxw2gZwX USKw== X-Gm-Message-State: AOAM530ZlfiS5Eu1AJgSG3CAdo3cEUsg6WMoSFGWTi4uET7m4vS/Fsb4 mb4eV9zDlZHv4y3DEqnPJAhYDA== X-Google-Smtp-Source: ABdhPJzTOx7XwqB2M/gYtejLYoKHQ4+Uv+vPHpnflGImQA3lZXNsJSYNIzCdzisV+S2ZiaSBlc5M5g== X-Received: by 2002:adf:e6cf:: with SMTP id y15mr3290322wrm.116.1604584331755; Thu, 05 Nov 2020 05:52:11 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id h4sm2648541wrq.3.2020.11.05.05.52.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Nov 2020 05:52:11 -0800 (PST) From: Georgi Djakov To: linux-pm@vger.kernel.org, bjorn.andersson@linaro.org, mdtipton@codeaurora.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, akashast@codeaurora.org, georgi.djakov@linaro.org Subject: [PATCH 2/3] interconnect: qcom: sdm845: Add the missing nodes for QUP Date: Thu, 5 Nov 2020 15:52:10 +0200 Message-Id: <20201105135211.7160-2-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201105135211.7160-1-georgi.djakov@linaro.org> References: <20201105135211.7160-1-georgi.djakov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QUP nodes are currently defined just as entries in the topology, but they are not referenced by any of the NoCs. Let's fix this and "attach" them to their NoCs, so that the QUP drivers are able to use them as path endpoints and scale their bandwidth. This is based on the information from the downstream msm-4.9 kernel. Signed-off-by: Georgi Djakov Reviewed-by: Bjorn Andersson --- drivers/interconnect/qcom/sdm845.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 5304aea3b058..366870150cbd 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -177,6 +177,7 @@ DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_sn9, + &bcm_qup0, }; static struct qcom_icc_node *aggre1_noc_nodes[] = { @@ -190,6 +191,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, + [MASTER_QUP_1] = &qhm_qup1, }; static const struct qcom_icc_desc sdm845_aggre1_noc = { @@ -218,6 +220,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, + [MASTER_QUP_2] = &qhm_qup2, }; static const struct qcom_icc_desc sdm845_aggre2_noc = { From patchwork Thu Nov 5 13:52:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 11884447 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D14CF921 for ; Thu, 5 Nov 2020 13:52:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9693920715 for ; Thu, 5 Nov 2020 13:52:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="T25OkuUQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730788AbgKENwP (ORCPT ); Thu, 5 Nov 2020 08:52:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730466AbgKENwP (ORCPT ); Thu, 5 Nov 2020 08:52:15 -0500 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EC75C0613CF for ; Thu, 5 Nov 2020 05:52:14 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id w14so1846081wrs.9 for ; Thu, 05 Nov 2020 05:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3y3h8Gt2B3dQV3uiCceEQJtTal2gmWJav/I0Vj+GOyU=; b=T25OkuUQXDWnngtej/+9ragOdTSWZdRg8+VnVRzO8J9CMxdJQRU2S2L2EpTfD5eyxo RMmVa35GY1K4ilU0FQiNMd1hs0CCVCKg1O12tX5cevu654FOwqI2vn8vlSNj6RDg8nX6 xGcwQNwhFXrDH6oy39zN1kOYELMUcIAzAoKqd2RAxF8mbS1EuU1tCTc+QO5AqrFI7C6j PlZerPoMdwkDLm9GZIV40/kwt+3ekNDKdFGfLAACyoVNISDlGeYNHJtaAfe0vKRb+wvF QXLCqSQ7VOUJesPd5YDlDZvPtNDJnCyHKO9bDMQFS6ugQdrQqxUczCidGWLYNtEd+6dp mx4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3y3h8Gt2B3dQV3uiCceEQJtTal2gmWJav/I0Vj+GOyU=; b=JDMPnvH2l7KnuuORuPwtYU4fh4bFjl9BXinfDy34TeTTpJLSCr8QuydhIvtPTwHlvR H0VZzhn0qu6IJZVaQoU1mjilmEl+5slznV5YUrq7gBxuREmCnbo9Rgp3lMqiItkiOpvR fmeVO454BzLiD0sutjZDHbrl5z34uADWdKoyLorSOjf+7q9m+2LUmRJ/n4/bVv5R492K bS7g9tEeCRzr60w2/TTTSRTfPNGMFhnzXIAz/PMnR4ip3Cuj8Z7t526P1TLRBs41CfEG N54BGNZEQ43idMzgJl6wuRJgwOEiPLm1GdmYU/OuZeIwxfTEbKTJLHl0Wf0LG8TN8uGp oJVw== X-Gm-Message-State: AOAM530vFse70YDyjf8krT1meOigs5nnaFyODTeNHzVeYe2+EpBFVGdp III3s9n/oKYXXkZ6rtDqketTj8sjUWcQdw== X-Google-Smtp-Source: ABdhPJz7/5ii7HK5bMoAedQL1YRUoj6Okm1V4pgzv17MB4XJKIgWAqVCA3hJO4rrgBuiUa0w9UrzLg== X-Received: by 2002:a5d:4bd1:: with SMTP id l17mr3305932wrt.38.1604584332989; Thu, 05 Nov 2020 05:52:12 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id h4sm2648541wrq.3.2020.11.05.05.52.11 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Nov 2020 05:52:12 -0800 (PST) From: Georgi Djakov To: linux-pm@vger.kernel.org, bjorn.andersson@linaro.org, mdtipton@codeaurora.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, akashast@codeaurora.org, georgi.djakov@linaro.org Subject: [PATCH 3/3] arm64: dts: sdm845: Add interconnect properties for QUP Date: Thu, 5 Nov 2020 15:52:11 +0200 Message-Id: <20201105135211.7160-3-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201105135211.7160-1-georgi.djakov@linaro.org> References: <20201105135211.7160-1-georgi.djakov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the interconnects DT property to describe the ports for GENI QUPs on the sdm845 platform. Signed-off-by: Georgi Djakov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 160 +++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index aca7e9c954e0..14e74ba889c3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1123,6 +1123,8 @@ qupv3_id_0: geniqup@8c0000 { #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -1137,6 +1139,10 @@ i2c0: i2c@880000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1150,6 +1156,9 @@ spi0: spi@880000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1163,6 +1172,9 @@ uart0: serial@880000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1178,6 +1190,10 @@ i2c1: i2c@884000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1191,6 +1207,9 @@ spi1: spi@884000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1204,6 +1223,9 @@ uart1: serial@884000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1219,6 +1241,10 @@ i2c2: i2c@888000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1232,6 +1258,9 @@ spi2: spi@888000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1245,6 +1274,9 @@ uart2: serial@888000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1260,6 +1292,10 @@ i2c3: i2c@88c000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1273,6 +1309,9 @@ spi3: spi@88c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1286,6 +1325,9 @@ uart3: serial@88c000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1301,6 +1343,10 @@ i2c4: i2c@890000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1314,6 +1360,9 @@ spi4: spi@890000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1327,6 +1376,9 @@ uart4: serial@890000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1342,6 +1394,10 @@ i2c5: i2c@894000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1355,6 +1411,9 @@ spi5: spi@894000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1368,6 +1427,9 @@ uart5: serial@894000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1383,6 +1445,10 @@ i2c6: i2c@898000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1396,6 +1462,9 @@ spi6: spi@898000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1409,6 +1478,9 @@ uart6: serial@898000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1437,6 +1509,9 @@ spi7: spi@89c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1450,6 +1525,9 @@ uart7: serial@89c000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -1463,6 +1541,8 @@ qupv3_id_1: geniqup@ac0000 { #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { @@ -1477,6 +1557,10 @@ i2c8: i2c@a80000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1490,6 +1574,9 @@ spi8: spi@a80000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1503,6 +1590,9 @@ uart8: serial@a80000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1518,6 +1608,10 @@ i2c9: i2c@a84000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1531,6 +1625,9 @@ spi9: spi@a84000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1544,6 +1641,9 @@ uart9: serial@a84000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1559,6 +1659,10 @@ i2c10: i2c@a88000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1572,6 +1676,9 @@ spi10: spi@a88000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1585,6 +1692,9 @@ uart10: serial@a88000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1600,6 +1710,10 @@ i2c11: i2c@a8c000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1613,6 +1727,9 @@ spi11: spi@a8c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1626,6 +1743,9 @@ uart11: serial@a8c000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1641,6 +1761,10 @@ i2c12: i2c@a90000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1654,6 +1778,9 @@ spi12: spi@a90000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1667,6 +1794,9 @@ uart12: serial@a90000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1682,6 +1812,10 @@ i2c13: i2c@a94000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1695,6 +1829,9 @@ spi13: spi@a94000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1708,6 +1845,9 @@ uart13: serial@a94000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1723,6 +1863,10 @@ i2c14: i2c@a98000 { #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1736,6 +1880,9 @@ spi14: spi@a98000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1749,6 +1896,9 @@ uart14: serial@a98000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1765,6 +1915,10 @@ i2c15: i2c@a9c000 { power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; }; spi15: spi@a9c000 { @@ -1777,6 +1931,9 @@ spi15: spi@a9c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1790,6 +1947,9 @@ uart15: serial@a9c000 { interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; };