From patchwork Fri Nov 6 16:34:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 11887371 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 430BF6A2 for ; Fri, 6 Nov 2020 16:38:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A8FC217A0 for ; Fri, 6 Nov 2020 16:38:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="V2hu9iyN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727020AbgKFQim (ORCPT ); Fri, 6 Nov 2020 11:38:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725868AbgKFQil (ORCPT ); Fri, 6 Nov 2020 11:38:41 -0500 Received: from mail-qt1-x835.google.com (mail-qt1-x835.google.com [IPv6:2607:f8b0:4864:20::835]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F8DFC0613CF for ; Fri, 6 Nov 2020 08:38:41 -0800 (PST) Received: by mail-qt1-x835.google.com with SMTP id r8so1156851qtp.13 for ; Fri, 06 Nov 2020 08:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Had0NO1OldvzTy/dDlNqjQKg348W7mzmn4iytrp+oxQ=; b=V2hu9iyNpp0yTzPUT7lZKUqbQ/2x7YnQrzVGbvUYq0G+YcJWUjF+46gV0o+FK/26vh Of+wrlgjlYkaT8tcI+l5nUoGXhEa2KBdlM+gLZ405p3MpZvEd9PudSivUEQHFOj6j0xv P8B2COSOrzBfz3zjjmgGwg1qz/7Wapve74QEoonB1WE8heMk3w7+FtxTOU9mdOYh2uNE ybQ9GCudcd2dniJhSOpvTNqMoNPet99w7Hmj0mZ/uWjvTHWl86FGNSJru6/CIdHLSBqm Tn8Il+iZyn0quArnaZx5+oNFlrLjNu0UnY82RZDbMrVQPhVmbUE2jHx1UpOPkxr35yDW DTaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Had0NO1OldvzTy/dDlNqjQKg348W7mzmn4iytrp+oxQ=; b=LLi4TAdHECwMfOFqpimY765+0xOqTsaO2Kr9TGMBdv0uUjBn1g1ErlHAI67+HESTBH j7uEnD0uKLezncpPmIfZnBRDGEQDqYTwENTK/zbzqdNVZP5snS5PlcrzxByHbcSrwdDt 3IzopUDILvL7PoEw2LinEtx2kOVaYC3UblvS9PaMu2byV7qKY+AwvgpTWSqIkK9gBcg5 zHVWSOwrMJXj4Q1Hs/I3svm/XzaCkonyNe4G1tvk0dVNLZmn2xIQJNlDGPByLK+I1K6v gJunD88AFYO6lVpbzbbC8JDh6Z6oatVrUPxC5JJHOs2A5WA8MuX7N4yQxfb79JQ5uwt0 DVug== X-Gm-Message-State: AOAM530S7ise/01isFMQcNOvIbIFkPQaIOfarzhtxPhcOQUwm+9dwzm4 1ELxTE0lYjCtYaPU+VZIXb7Upw== X-Google-Smtp-Source: ABdhPJyfJBGq5pbvY6DHwRd9vE1Q5GQnVMlutx1rNnL4Hh9g0+G/IzM1OxjFTx5xliniBDauqTkHDw== X-Received: by 2002:ac8:7604:: with SMTP id t4mr2374834qtq.366.1604680720838; Fri, 06 Nov 2020 08:38:40 -0800 (PST) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id s3sm860000qkj.27.2020.11.06.08.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2020 08:38:40 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Jordan Crouse , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Bjorn Andersson , Sharat Masetty , Shawn Guo , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/5] drm/msm: add MSM_BO_CACHED_COHERENT Date: Fri, 6 Nov 2020 11:34:30 -0500 Message-Id: <20201106163437.30836-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20201106163437.30836-1-jonathan@marek.ca> References: <20201106163437.30836-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a new cache mode for creating coherent host-cached BOs. Signed-off-by: Jonathan Marek Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gem.c | 8 ++++++++ include/uapi/drm/msm_drm.h | 5 ++--- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 58e03b20e1c7..21c9bc954f38 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -410,6 +410,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; + priv->has_cached_coherent = config.rev.core >= 6; gpu = info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f33281ac7913..22ebecb28349 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -168,6 +168,7 @@ struct msm_drm_private { struct msm_file_private *lastctx; /* gpu is only set on open(), but we need this info earlier */ bool is_a2xx; + bool has_cached_coherent; struct drm_fb_helper *fbdev; diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 04be4cfcccc1..3d8254b5de16 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -420,6 +420,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, if (msm_obj->flags & MSM_BO_MAP_PRIV) prot |= IOMMU_PRIV; + if (msm_obj->flags & MSM_BO_CACHED_COHERENT) + prot |= IOMMU_CACHE; + WARN_ON(!mutex_is_locked(&msm_obj->lock)); if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) @@ -1004,6 +1007,7 @@ static int msm_gem_new_impl(struct drm_device *dev, uint32_t size, uint32_t flags, struct drm_gem_object **obj) { + struct msm_drm_private *priv = dev->dev_private; struct msm_gem_object *msm_obj; switch (flags & MSM_BO_CACHE_MASK) { @@ -1011,6 +1015,10 @@ static int msm_gem_new_impl(struct drm_device *dev, case MSM_BO_CACHED: case MSM_BO_WC: break; + case MSM_BO_CACHED_COHERENT: + if (priv->has_cached_coherent) + break; + /* fallthrough */ default: DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n", (flags & MSM_BO_CACHE_MASK)); diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index a6c1f3eb2623..474497e8743a 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -94,12 +94,11 @@ struct drm_msm_param { #define MSM_BO_CACHED 0x00010000 #define MSM_BO_WC 0x00020000 #define MSM_BO_UNCACHED 0x00040000 +#define MSM_BO_CACHED_COHERENT 0x080000 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ MSM_BO_GPU_READONLY | \ - MSM_BO_CACHED | \ - MSM_BO_WC | \ - MSM_BO_UNCACHED) + MSM_BO_CACHE_MASK) struct drm_msm_gem_new { __u64 size; /* in */ From patchwork Fri Nov 6 16:34:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 11887373 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF09B15E6 for ; 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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id s3sm860000qkj.27.2020.11.06.08.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2020 08:38:43 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/5] drm/msm: call dma_direct_bypass() Date: Fri, 6 Nov 2020 11:34:32 -0500 Message-Id: <20201106163437.30836-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20201106163437.30836-1-jonathan@marek.ca> References: <20201106163437.30836-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Always use direct dma ops and no swiotlb. Note: arm-smmu-qcom already avoids creating iommu dma ops, but not everything uses arm-smmu-qcom and this also sets the dma mask. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/msm_drv.c | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index e5816b498494..07c50405970a 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -20,6 +20,7 @@ config DRM_MSM select SND_SOC_HDMI_CODEC if SND_SOC select SYNC_FILE select PM_OPP + select DMA_OPS_BYPASS help DRM/KMS driver for MSM/snapdragon. diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 49685571dc0e..bae48afca82e 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -1288,10 +1289,11 @@ static int msm_pdev_probe(struct platform_device *pdev) if (ret) goto fail; - /* on all devices that I am aware of, iommu's which can map - * any address the cpu can see are used: + /* always use direct dma ops and no swiotlb + * note: arm-smmu-qcom already avoids creating iommu dma ops, but + * not everything uses arm-smmu-qcom and this also sets the dma mask */ - ret = dma_set_mask_and_coherent(&pdev->dev, ~0); + ret = dma_direct_bypass(&pdev->dev); if (ret) goto fail; From patchwork Fri Nov 6 16:34:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 11887375 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 813246A2 for ; Fri, 6 Nov 2020 16:38:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 557DD21556 for ; Fri, 6 Nov 2020 16:38:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="YprrwzJH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727312AbgKFQis (ORCPT ); Fri, 6 Nov 2020 11:38:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727213AbgKFQiq (ORCPT ); Fri, 6 Nov 2020 11:38:46 -0500 Received: from mail-qv1-xf44.google.com (mail-qv1-xf44.google.com [IPv6:2607:f8b0:4864:20::f44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8D59C0613CF for ; Fri, 6 Nov 2020 08:38:46 -0800 (PST) Received: by mail-qv1-xf44.google.com with SMTP id d1so708898qvl.6 for ; Fri, 06 Nov 2020 08:38:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nz9fkxFdcHJ7ADLc2X+aLLgEbUSgZI45eX7FI+RDIco=; b=YprrwzJHGd5zC+abZoj17nWgMOHXzcGvRcqC+fRwiSUe1n215VgAqZCBZtCmhA2c18 lVAh6izQHx3Gok6f9X6hwjH7OemNhVCxoIBH00xFxVbi4wg+v/pOV2geUYl2g9I18yCU Pf9wzt5ZePHnXDN6GXQUuSAHrWtJRLIP5H3g/dFVz2WXaX9TF88rOXR1FidZi4BhStnW RP8ds1UWLtbT2+EX803qrxQpP6WqD9o0pyH9rMgIT81lZvO/Sixw/VsS6yYby+XcugT5 rGCLAxN0LjEJRCcI3Dz0nnD25SV96mmVZa+QWamoV6im/LJuv1HFtxmEaZBML9XSBT2h m3Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nz9fkxFdcHJ7ADLc2X+aLLgEbUSgZI45eX7FI+RDIco=; b=LPmZp3MGM+f7ADIwvP4foOph/nh0jPcFrhAqFY3sYeqzlXY1hMlxkT/yv5oIeU4Rkp wYv3tELbuSpoVN+ljzBNEUQjat0VfAKH4kE4XbgqK2NAVY5mPkfbH+y4Rtkp8r7UMfbW 7gUy+N0Mz5SJ7cNoNfqGqAztbFQ9LXPTNAAVl/nCdMegeLEJhwC/UK77v6Y44gprBYnI qE5b/4haxz1jdqwyxhzY30p9ZkdBBvg4sXVKwqgE/yYSll7910vq0Y6aHurVLGNlE1vL kkwQauYUXNmzoe+K4ISsEjDyT5j64gGzdCmACQWwQxU7Qe9fp3uLusvQSk6j800GsrWp xgRw== X-Gm-Message-State: AOAM533ejonIUYjiqpzMWcbNYA7/ZWTT8yNx2MUMWYmHk19D3IZkogq/ uIZxcvLWfHyJyhraXb6qEv6Skg== X-Google-Smtp-Source: ABdhPJwtilSBuJYfYaXlVmxWrU+ttzbHoc/4G/Yq+TmgFp3KyG8KAzxZCHi7nOXjHAXUO9CN42aFMA== X-Received: by 2002:ad4:4e84:: with SMTP id dy4mr2478454qvb.47.1604680725952; Fri, 06 Nov 2020 08:38:45 -0800 (PST) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id s3sm860000qkj.27.2020.11.06.08.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2020 08:38:45 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Date: Fri, 6 Nov 2020 11:34:33 -0500 Message-Id: <20201106163437.30836-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20201106163437.30836-1-jonathan@marek.ca> References: <20201106163437.30836-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This makes it possible to use the non-coherent cached MSM_BO_CACHED mode, which otherwise doesn't provide any method for cleaning/invalidating the cache to sync with the device. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_drv.c | 21 +++++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 2 ++ drivers/gpu/drm/msm/msm_gem.c | 23 +++++++++++++++++++++++ include/uapi/drm/msm_drm.h | 20 ++++++++++++++++++++ 4 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index bae48afca82e..3f17acdf6594 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -959,6 +959,26 @@ static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, return msm_submitqueue_remove(file->driver_priv, id); } +static int msm_ioctl_gem_sync_cache(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_msm_gem_sync_cache *args = data; + struct drm_gem_object *obj; + + if (args->flags & ~MSM_GEM_SYNC_CACHE_FLAGS) + return -EINVAL; + + obj = drm_gem_object_lookup(file, args->handle); + if (!obj) + return -ENOENT; + + msm_gem_sync_cache(obj, args->flags, args->offset, args->end); + + drm_gem_object_put(obj); + + return 0; +} + static const struct drm_ioctl_desc msm_ioctls[] = { DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), @@ -971,6 +991,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = { DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_SYNC_CACHE, msm_ioctl_gem_sync_cache, DRM_RENDER_ALLOW), }; static const struct vm_operations_struct vm_ops = { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 22ebecb28349..f170f843010e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -318,6 +318,8 @@ void msm_gem_active_get(struct drm_gem_object *obj, struct msm_gpu *gpu); void msm_gem_active_put(struct drm_gem_object *obj); int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); int msm_gem_cpu_fini(struct drm_gem_object *obj); +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags, + size_t range_start, size_t range_end); void msm_gem_free_object(struct drm_gem_object *obj); int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, uint32_t size, uint32_t flags, uint32_t *handle, char *name); diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 3d8254b5de16..039738696f9a 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -797,6 +797,29 @@ int msm_gem_cpu_fini(struct drm_gem_object *obj) return 0; } +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags, + size_t range_start, size_t range_end) +{ + struct msm_gem_object *msm_obj = to_msm_bo(obj); + struct device *dev = msm_obj->base.dev->dev; + + /* exit early if get_pages() hasn't been called yet */ + if (!msm_obj->pages) + return; + + /* TODO: sync only the specified range */ + + if (flags & MSM_GEM_SYNC_FOR_DEVICE) { + dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, + msm_obj->sgt->nents, DMA_TO_DEVICE); + } + + if (flags & MSM_GEM_SYNC_FOR_CPU) { + dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, + msm_obj->sgt->nents, DMA_FROM_DEVICE); + } +} + #ifdef CONFIG_DEBUG_FS static void describe_fence(struct dma_fence *fence, const char *type, struct seq_file *m) diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 474497e8743a..c8288f328528 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -319,6 +319,24 @@ struct drm_msm_submitqueue_query { __u32 pad; }; +/* + * Host cache maintenance (relevant for MSM_BO_CACHED) + * driver may both clean/invalidate (flush) for clean + */ + +#define MSM_GEM_SYNC_FOR_DEVICE 0x1 +#define MSM_GEM_SYNC_FOR_CPU 0x2 + +#define MSM_GEM_SYNC_CACHE_FLAGS (MSM_GEM_SYNC_FOR_DEVICE | \ + MSM_GEM_SYNC_FOR_CPU) + +struct drm_msm_gem_sync_cache { + __u32 handle; + __u32 flags; + __u64 offset; + __u64 end; /* offset + size */ +}; + #define DRM_MSM_GET_PARAM 0x00 /* placeholder: #define DRM_MSM_SET_PARAM 0x01 @@ -336,6 +354,7 @@ struct drm_msm_submitqueue_query { #define DRM_MSM_SUBMITQUEUE_NEW 0x0A #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C +#define DRM_MSM_GEM_SYNC_CACHE 0x0D #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) @@ -348,6 +367,7 @@ struct drm_msm_submitqueue_query { #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) +#define DRM_IOCTL_MSM_GEM_SYNC_CACHE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_SYNC_CACHE, struct drm_msm_gem_sync_cache) #if defined(__cplusplus) } From patchwork Fri Nov 6 16:34:34 2020 Content-Type: text/plain; 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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id s3sm860000qkj.27.2020.11.06.08.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2020 08:38:46 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 5/5] drm/msm: bump up the uapi version Date: Fri, 6 Nov 2020 11:34:34 -0500 Message-Id: <20201106163437.30836-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20201106163437.30836-1-jonathan@marek.ca> References: <20201106163437.30836-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Increase the minor version to indicate the presence of new features. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/msm_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 3f17acdf6594..7230d3c0eee5 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -39,9 +39,10 @@ * GEM object's debug name * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl * - 1.6.0 - Syncobj support + * - 1.7.0 - MSM_BO_CACHED_COHERENT and DRM_IOCTL_MSM_GEM_SYNC_CACHE */ #define MSM_VERSION_MAJOR 1 -#define MSM_VERSION_MINOR 6 +#define MSM_VERSION_MINOR 7 #define MSM_VERSION_PATCHLEVEL 0 static const struct drm_mode_config_funcs mode_config_funcs = {