From patchwork Sat Nov 14 13:50:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11905609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE57FC71156 for ; Sat, 14 Nov 2020 13:52:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7841122252 for ; Sat, 14 Nov 2020 13:52:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="l5FsBr48" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726827AbgKNNwY (ORCPT ); Sat, 14 Nov 2020 08:52:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726821AbgKNNwX (ORCPT ); Sat, 14 Nov 2020 08:52:23 -0500 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C748C061A47 for ; Sat, 14 Nov 2020 05:52:22 -0800 (PST) Received: by mail-pg1-x543.google.com with SMTP id f27so9179780pgl.1 for ; Sat, 14 Nov 2020 05:52:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F/nq3JnunleBEPmOqQ59JVNiFyN2h6AIwG//l7PiMiQ=; b=l5FsBr48D12H3HK8mLGUuPcnIWvJp1vzinlvLgFfovlMFugm7gKec4ctCEOoBdkoDz fSuT4W75rbTt7t2WFPTCG2GevKdL2TeqeE6PJhpx2Iy4vFvvncr6EhL35l37w+6Fe+G6 oV//uwgXt1OunaaouRB1KY7CSrhOl2eeo93qo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F/nq3JnunleBEPmOqQ59JVNiFyN2h6AIwG//l7PiMiQ=; b=fijcjkNM5M8tfQuwskVs+j2y7+e454GayGtS1zf6jlaIryTrhPjStORmJFiZD05SlZ OdBjDdOOzLQYC/SqY7Z2nQXLk6lIg4tpWLy8I4V9w8QI2LMe/vWvGYyCbLq4k5XwP26k INpeBbU3N7XwJh9u1fFb1+qi8MY6QH5rcqSnlcuIhNKkAp6eIgrKO7eLW/s2flOxsxbl Yx8A4VnQoSOyjB9PZJs9qChJKf9XxA9pFyFJUnpFBUKll2ZLcvvDjp6RpfdqVJfbFtww faKwtHJEFqXuOhPmwabne3ONAxtAl0xPImIsnqcTMzmneSHumkV71Bs1bZqi8TRF5tl4 09Lg== X-Gm-Message-State: AOAM5338oy5TlPjd5//0jPzWiiktGHtiarU1sD83Oe4PRMoVgk1shbMP hOUWJb9uqvRLg+WM7Xi3mN092HNvLKMYbg== X-Google-Smtp-Source: ABdhPJzq4Ydud7WeDfpMytkX7tslUBQ49azEQ7XkLoSKZEyI0EoGIy2e/XTGLLSPG5v8hRo5NIhAKw== X-Received: by 2002:aa7:8b12:0:b029:18c:7b88:d7fc with SMTP id f18-20020aa78b120000b029018c7b88d7fcmr6241210pfd.53.1605361941458; Sat, 14 Nov 2020 05:52:21 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id r205sm13008023pfr.25.2020.11.14.05.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 05:52:21 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 1/6] dt-bindings: clk: mstar msc313 mpll binding header Date: Sat, 14 Nov 2020 22:50:39 +0900 Message-Id: <20201114135044.724385-2-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201114135044.724385-1-daniel@0x0f.com> References: <20201114135044.724385-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Simple header to document the relationship between the MPLL outputs and which divider they come from. Output 0 is missing because it should not be consumed. Signed-off-by: Daniel Palmer Acked-by: Rob Herring --- MAINTAINERS | 1 + include/dt-bindings/clock/mstar-msc313-mpll.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/clock/mstar-msc313-mpll.h diff --git a/MAINTAINERS b/MAINTAINERS index a3f0aa46d0d8..1e874fda810e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2135,6 +2135,7 @@ F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ F: drivers/gpio/gpio-msc313.c +F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/include/dt-bindings/clock/mstar-msc313-mpll.h b/include/dt-bindings/clock/mstar-msc313-mpll.h new file mode 100644 index 000000000000..1b30b02317b6 --- /dev/null +++ b/include/dt-bindings/clock/mstar-msc313-mpll.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Output definitions for the MStar/SigmaStar MPLL + * + * Copyright (C) 2020 Daniel Palmer + */ + +#ifndef _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H +#define _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H + +#define MSTAR_MSC313_MPLL_DIV2 1 +#define MSTAR_MSC313_MPLL_DIV3 2 +#define MSTAR_MSC313_MPLL_DIV4 3 +#define MSTAR_MSC313_MPLL_DIV5 4 +#define MSTAR_MSC313_MPLL_DIV6 5 +#define MSTAR_MSC313_MPLL_DIV7 6 +#define MSTAR_MSC313_MPLL_DIV10 7 + +#endif From patchwork Sat Nov 14 13:50:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11905613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D7FC6369E for ; Sat, 14 Nov 2020 13:52:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC3F622252 for ; Sat, 14 Nov 2020 13:52:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="Uu7hY/Wd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726861AbgKNNw0 (ORCPT ); Sat, 14 Nov 2020 08:52:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726859AbgKNNwZ (ORCPT ); Sat, 14 Nov 2020 08:52:25 -0500 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44739C0617A6 for ; Sat, 14 Nov 2020 05:52:24 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id j19so2362775pgg.5 for ; Sat, 14 Nov 2020 05:52:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pQB8wgB7xeIzH4jYM33Ni/91/CZjY/s5lPEIdcq3mCs=; b=Uu7hY/WdqQASdhCOaP1aQEOiIjN5oC5jyTXW4bN0uyIfzp/ctO8WPQlZ/O0BY7gkKQ PVQRjcB2ShZ50gUFqHusQ8U4utYtgZr9ijG9dp54JAlRHUaDUw2gY1bwmmSMgaUjky3a XDUusT4Y9e9PJtJYcXwkuvvhDOny98vTjOUBw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pQB8wgB7xeIzH4jYM33Ni/91/CZjY/s5lPEIdcq3mCs=; b=Yr1ZeiDcq+YW/Wvrfkcqvh0FI7POVlBtwBG1p5qdVS4tNqqLcF9LQdRO7pAsvey+7s RzxplLCTjbpYx4tdEumHlAcC8C5WlQFgJgbVpKewEq2Y0CMQaqHGtCUwTmyqYvbJ9XnK gH8DLOWrjfTS7D3vb9clsYsM21TuYCZJdG8Xvrac9moETuW/8FTkm0tHlz/Mbl5+U8Yv T3Bjc0+HoF9ACcWUuXeaXhb/2ZFX7mc1H3JWGyvBldDBS1eHGYS/3zjXPvM7/oMECJ+x JcWE6ZbpIPVbuLvMUn0i9+n6QajCGQW7Wi9CkRyv2FYBSn5BVhm+ys65MksEMsANhGGc tXAg== X-Gm-Message-State: AOAM533jRxj3A8WvAskFVVWfxOPCwkmEYE4WlCdr/bH8OJWjjKVZApJM 3dl81PwA3KeZmikSQje+IuojCb8M+3H0ug== X-Google-Smtp-Source: ABdhPJybgsuJ2MR9afC4TvV1wuAq0kjAHSEVh7bgfL3c5ZOBk5Ui3Qqzj6j2VtFir9Yr6HaMI/hg/w== X-Received: by 2002:aa7:9414:0:b029:18c:23f6:bc6d with SMTP id x20-20020aa794140000b029018c23f6bc6dmr6451830pfo.21.1605361943642; Sat, 14 Nov 2020 05:52:23 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id r205sm13008023pfr.25.2020.11.14.05.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 05:52:23 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 2/6] dt-bindings: clk: mstar msc313 mpll binding description Date: Sat, 14 Nov 2020 22:50:40 +0900 Message-Id: <20201114135044.724385-3-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201114135044.724385-1-daniel@0x0f.com> References: <20201114135044.724385-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a binding description for the MStar/SigmaStar MPLL clock block. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring --- .../bindings/clock/mstar,msc313-mpll.yaml | 58 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml new file mode 100644 index 000000000000..9ddc1163b31b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 MPLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that + takes the external xtal input and multiplies it to create a high + frequency clock and divides that down into a number of clocks that + peripherals use. + +properties: + compatible: + const: mstar,msc313-mpll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-output-names: + minItems: 8 + maxItems: 8 + description: | + This should provide a name for the internal PLL clock and then + a name for each of the divided outputs. + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-output-names + - reg + +additionalProperties: false + +examples: + - | + mpll@206000 { + compatible = "mstar,msc313-mpll"; + reg = <0x206000 0x200>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-output-names = "mpll", "mpll_div_2", + "mpll_div_3", "mpll_div_4", + "mpll_div_5", "mpll_div_6", + "mpll_div_7", "mpll_div_10"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 1e874fda810e..d1c98a6f9f24 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2131,6 +2131,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* +F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ From patchwork Sat Nov 14 13:50:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11905617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9E3EC6379F for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id r205sm13008023pfr.25.2020.11.14.05.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 05:52:25 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 3/6] clk: mstar: MStar/SigmaStar MPLL driver Date: Sat, 14 Nov 2020 22:50:41 +0900 Message-Id: <20201114135044.724385-4-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201114135044.724385-1-daniel@0x0f.com> References: <20201114135044.724385-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This adds a basic driver for the MPLL block found in MStar/SigmaStar ARMv7 SoCs. Currently this driver is only good for calculating the rates of it's outputs and the actual configuration must be done before the kernel boots. Usually this is done even before u-boot starts. This driver targets the MPLL block found in the MSC313/MSC313E but there is no documentation this chip so the register descriptions for the another MStar chip the MST786 were used as they seem to match. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/mstar/Kconfig | 5 + drivers/clk/mstar/Makefile | 6 + drivers/clk/mstar/clk-msc313-mpll.c | 177 ++++++++++++++++++++++++++++ 6 files changed, 191 insertions(+) create mode 100644 drivers/clk/mstar/Kconfig create mode 100644 drivers/clk/mstar/Makefile create mode 100644 drivers/clk/mstar/clk-msc313-mpll.c diff --git a/MAINTAINERS b/MAINTAINERS index d1c98a6f9f24..1783022b4aa8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2135,6 +2135,7 @@ F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ +F: drivers/clk/mstar/ F: drivers/gpio/gpio-msc313.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c715d4681a0b..a002f2605fa3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -370,6 +370,7 @@ source "drivers/clk/ingenic/Kconfig" source "drivers/clk/keystone/Kconfig" source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" +source "drivers/clk/mstar/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index da8fcf147eb1..b758aae17ab8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -124,3 +124,4 @@ endif obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/ +obj-$(CONFIG_ARCH_MSTARV7) += mstar/ diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig new file mode 100644 index 000000000000..23765edde3af --- /dev/null +++ b/drivers/clk/mstar/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +config MSTAR_MSC313_MPLL + bool + select REGMAP + select REGMAP_MMIO diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile new file mode 100644 index 000000000000..f8dcd25ede1d --- /dev/null +++ b/drivers/clk/mstar/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for mstar specific clk +# + +obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o diff --git a/drivers/clk/mstar/clk-msc313-mpll.c b/drivers/clk/mstar/clk-msc313-mpll.c new file mode 100644 index 000000000000..c1e2fe0fc412 --- /dev/null +++ b/drivers/clk/mstar/clk-msc313-mpll.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MStar MSC313 MPLL driver + * + * Copyright (C) 2020 Daniel Palmer + */ + +#include +#include +#include +#include +#include +#include +#include + +#define REG_CONFIG1 0x8 +#define REG_CONFIG2 0xc + +static const struct regmap_config msc313_mpll_regmap_config = { + .reg_bits = 16, + .val_bits = 16, + .reg_stride = 4, +}; + +static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9); +static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5); +static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13); +static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7); + +static const unsigned int output_dividers[] = { + 2, 3, 4, 5, 6, 7, 10 +}; + +#define NUMOUTPUTS (ARRAY_SIZE(output_dividers) + 1) + +struct msc313_mpll { + struct clk_hw clk_hw; + struct regmap_field *input_div; + struct regmap_field *loop_div_first; + struct regmap_field *loop_div_second; + struct regmap_field *output_div; + struct clk_hw_onecell_data *clk_data; +}; + +#define to_mpll(_hw) container_of(_hw, struct msc313_mpll, clk_hw) +#define to_divider_hw(_mpll, _which) _mpll->clk_data->hws[_which + 1] + +static unsigned long msc313_mpll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msc313_mpll *mpll = to_mpll(hw); + unsigned int input_div, output_div, loop_first, loop_second; + unsigned long output_rate; + + regmap_field_read(mpll->input_div, &input_div); + regmap_field_read(mpll->output_div, &output_div); + regmap_field_read(mpll->loop_div_first, &loop_first); + regmap_field_read(mpll->loop_div_second, &loop_second); + + output_rate = parent_rate / (1 << input_div); + output_rate *= (1 << loop_first) * max(loop_second, 1U); + output_rate /= max(output_div, 1U); + + return output_rate; +} + +static const struct clk_ops msc313_mpll_ops = { + .recalc_rate = msc313_mpll_recalc_rate, +}; + +static int msc313_mpll_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct msc313_mpll *mpll; + struct clk_init_data clk_init; + struct device *dev = &pdev->dev; + struct regmap *regmap; + const char *parents[1], *outputnames[NUMOUTPUTS]; + const int numparents = ARRAY_SIZE(parents); + int ret, i; + + if (of_clk_parent_fill(dev->of_node, parents, numparents) != numparents) + return -EINVAL; + + if (of_property_read_string_array(pdev->dev.of_node, "clock-output-names", + outputnames, NUMOUTPUTS) != NUMOUTPUTS) + return -EINVAL; + + mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL); + if (!mpll) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &msc313_mpll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first); + if (IS_ERR(mpll->input_div)) + return PTR_ERR(mpll->input_div); + mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first); + if (IS_ERR(mpll->output_div)) + return PTR_ERR(mpll->output_div); + mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first); + if (IS_ERR(mpll->loop_div_first)) + return PTR_ERR(mpll->loop_div_first); + mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second); + if (IS_ERR(mpll->loop_div_second)) + return PTR_ERR(mpll->loop_div_second); + + mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws, + ARRAY_SIZE(output_dividers)), GFP_KERNEL); + if (!mpll->clk_data) + return -ENOMEM; + + clk_init.name = outputnames[0]; + clk_init.ops = &msc313_mpll_ops; + clk_init.num_parents = 1; + clk_init.parent_names = parents; + mpll->clk_hw.init = &clk_init; + + ret = devm_clk_hw_register(dev, &mpll->clk_hw); + if (ret) + return ret; + + mpll->clk_data->num = NUMOUTPUTS; + mpll->clk_data->hws[0] = &mpll->clk_hw; + + for (i = 0; i < ARRAY_SIZE(output_dividers); i++) { + to_divider_hw(mpll, i) = clk_hw_register_fixed_factor(dev, + outputnames[i + 1], outputnames[0], 0, 1, output_dividers[i]); + if (IS_ERR(to_divider_hw(mpll, i))) { + ret = PTR_ERR(to_divider_hw(mpll, i)); + goto unregister_dividers; + } + } + + platform_set_drvdata(pdev, mpll); + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + mpll->clk_data); + +unregister_dividers: + for (i--; i >= 0; i--) + clk_hw_unregister_fixed_factor(to_divider_hw(mpll, i)); + return ret; +} + +static int msc313_mpll_remove(struct platform_device *pdev) +{ + struct msc313_mpll *mpll = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < ARRAY_SIZE(output_dividers); i++) + clk_hw_unregister_fixed_factor(to_divider_hw(mpll, i)); + + return 0; +} + +static const struct of_device_id msc313_mpll_of_match[] = { + { .compatible = "mstar,msc313-mpll", }, + {} +}; +MODULE_DEVICE_TABLE(of, msc313_mpll_of_match); + +static struct platform_driver msc313_mpll_driver = { + .driver = { + .name = "mstar-msc313-mpll", + .of_match_table = msc313_mpll_of_match, + }, + .probe = msc313_mpll_probe, + .remove = msc313_mpll_remove, +}; +builtin_platform_driver(msc313_mpll_driver); From patchwork Sat Nov 14 13:50:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11905607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 033F6C64E69 for ; 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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id r205sm13008023pfr.25.2020.11.14.05.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 05:52:27 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 4/6] ARM: mstar: Select MSTAR_MSC313_MPLL Date: Sat, 14 Nov 2020 22:50:42 +0900 Message-Id: <20201114135044.724385-5-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201114135044.724385-1-daniel@0x0f.com> References: <20201114135044.724385-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All of the ARCH_MSTARV7 chips have an MPLL as the source for peripheral clocks so select MSTAR_MSC313_MPLL. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 576d1ab293c8..cd300eeedc20 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -4,6 +4,7 @@ menuconfig ARCH_MSTARV7 select ARM_GIC select ARM_HEAVY_MB select MST_IRQ + select MSTAR_MSC313_MPLL help Support for newer MStar/Sigmastar SoC families that are based on Armv7 cores like the Cortex A7 and share the same From patchwork Sat Nov 14 13:50:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11905611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67D67C64E90 for ; Sat, 14 Nov 2020 13:52:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 344CF22252 for ; Sat, 14 Nov 2020 13:52:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="mg0e+Lsq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726918AbgKNNwk (ORCPT ); Sat, 14 Nov 2020 08:52:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726913AbgKNNwc (ORCPT ); Sat, 14 Nov 2020 08:52:32 -0500 Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB2B4C061A47 for ; Sat, 14 Nov 2020 05:52:30 -0800 (PST) Received: by mail-pl1-x643.google.com with SMTP id cp9so5874955plb.1 for ; Sat, 14 Nov 2020 05:52:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7zw/uZzxvI3UePDC2yxEHCw/8K7dNDmlYTPIl068JGQ=; b=mg0e+Lsq9YBtl68lnopxGRDi8ylTs8lx0VoMPRqPwAEwR0QdW0KbXa1TdF8we1ikSe GVAzhcyNhOtFjqwg8nkvTrp8SZwsWGZuqVDcW58kHzOtub60XF2D7Il2NicDXmVumvK4 iHtllgespAnnBNAXFTOBu3U5C3BjVl1oQiszA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7zw/uZzxvI3UePDC2yxEHCw/8K7dNDmlYTPIl068JGQ=; b=f4WzGe9LQKjCXbI2JH0hzkg2GMKM+l8UQx6ocgAR7Gei4yrGIIDjV5g7srJXCjFzxu 8NckqpnhKthtUveyS6gaHGG24Rhjmwdh0MxkuR+mTyShA9LxsHjG6kCuMoJMjfIZedW1 1kr06TrniM2lPGWvEthuJFaUbrBGMpLsyxnfZfwlo9VlsLHCrJReR35HzVsYGImDcNw3 ooZE9WMtzqKArBJJLkJoJLHJLsH+JtJHq2p52BPPi8/PcrFdZVmaTTILCXHGedIrz2wP u6FnF3hvnuNyNeBpjham9WpY5jrL8zvhOVLSGwNOxTfxlEJZNtm3o/Z9/R8EsK4gLrnC mkUA== X-Gm-Message-State: AOAM5307zWVZitOd8CA+wke/cwyWmsWFBCjoAMjYIKIo4k90kOIIaspU wL3sZYeLrBKAtwxApIfoz9aIaMD7/mUgyA== X-Google-Smtp-Source: ABdhPJyDJ55HiTcpPgKtU/DqaqSzQFSOJX7ii1TD1oASOYYXg6/75aNAlX05C72x7GfTj7cjMhhM9g== X-Received: by 2002:a17:902:c113:b029:d6:e921:bfc7 with SMTP id 19-20020a170902c113b02900d6e921bfc7mr6082374pli.19.1605361950160; Sat, 14 Nov 2020 05:52:30 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id r205sm13008023pfr.25.2020.11.14.05.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 05:52:29 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 5/6] ARM: mstar: Add the external clocks to the base dsti Date: Sat, 14 Nov 2020 22:50:43 +0900 Message-Id: <20201114135044.724385-6-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201114135044.724385-1-daniel@0x0f.com> References: <20201114135044.724385-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All of the currently known MStar/SigmaStar ARMv7 SoCs have an "xtal" clock input that is usually 24MHz and an "RTC xtal" that is usually 32KHz. The xtal input has to be connected to something so it's enabled by default. The MSC313 and MSC313E do not bring the RTC clock input out to the pins so it's impossible to connect it. The SSC8336 does bring the input out to the pins but it's not always actually connected to something. The RTC node needs to always be present because in the future the nodes for the clock muxes will refer to it even if it's not usable. The RTC node is disabled by default and should be enabled at the board level if the RTC input is wired up. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 81369bc07f78..6749d421dbf4 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -46,6 +46,21 @@ pmu: pmu { interrupt-affinity = <&cpu0>; }; + clocks: clocks { + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + rtc_xtal: rtc_xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + status = "disabled"; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; From patchwork Sat Nov 14 13:50:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11905615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D71EAC5519F for ; Sat, 14 Nov 2020 13:52:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8233A22252 for ; Sat, 14 Nov 2020 13:52:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="GPsXkawF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbgKNNwh (ORCPT ); Sat, 14 Nov 2020 08:52:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726917AbgKNNwe (ORCPT ); Sat, 14 Nov 2020 08:52:34 -0500 Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D26ACC061A4A for ; Sat, 14 Nov 2020 05:52:32 -0800 (PST) Received: by mail-pj1-x1042.google.com with SMTP id b12so465068pjl.0 for ; Sat, 14 Nov 2020 05:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TmJn3hr+RLmmQX5ys3w8ADM69QUXZfzE0ScMjrcJoEw=; b=GPsXkawFTCiDfm+G3kS88/otci7zITPY/HBy1frTfqrJAhPeexLAqopi8TX6GAjVh/ vMFACaUFE5CcgE4QCFfAbWqgjJmIltVetaVuoxaI5n7j/iQMtTEGI7uFbXYkgAq0fm2O C0cGyoLTSOk6YX25cSks4LovwTWiCBrKv0CwE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TmJn3hr+RLmmQX5ys3w8ADM69QUXZfzE0ScMjrcJoEw=; b=tQmge0UqV8xzy5YMSfiUVlZD1g1Qr9LIlYW35ngG3ZhA0NxsU4YFxQ0ybK527aHWmd HAyAPFVMOMDfDaDfHpBub5MRbdtTn8WYMpewbaFxAuSJOSZmxiX0/IDrEXbe2Q/LdLk+ 5x6hP2DOCMBnqqEPFtKvAaw95Qnvpk5W6mgnXBimO1tYaMWaYDc6ka8yRy9RxuorZbdi ljDpkh2Z1o7FC9MGEQEc1DqmE1gRXWMV6sDIYGwrZsMUNMkdQQzQz9QZArXKvumCJtaa zbCD8STAWu7J66mFo76UUTPzeHAUqoz89K79v7gwiOVbar+3GVCZq73iLdT0OgZuRwk5 K+OQ== X-Gm-Message-State: AOAM533hldIIj+nwE9rHFpkFtABfk1SRPsJKM7YTs0XtkjZRtgjZRE5h LaHVfTT+7wZlEtamKHvSS1g9Ohd75FdqSA== X-Google-Smtp-Source: ABdhPJy/eSal4uffFJZ0hVxw0r5qNnxSAm+4AoDTcudEaAoHz5Js3Cpkohoc+aovNShf/PnXEoWXKg== X-Received: by 2002:a17:90b:368e:: with SMTP id mj14mr8034823pjb.109.1605361952265; Sat, 14 Nov 2020 05:52:32 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id r205sm13008023pfr.25.2020.11.14.05.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 05:52:31 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 6/6] ARM: mstar: Add mpll to base dtsi Date: Sat, 14 Nov 2020 22:50:44 +0900 Message-Id: <20201114135044.724385-7-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201114135044.724385-1-daniel@0x0f.com> References: <20201114135044.724385-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All of the currently known MStar/SigmaStar ARMv7 SoCs have at least one MPLL and it seems to always be at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 6749d421dbf4..07fc46c7b4d4 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { #address-cells = <1>; @@ -124,6 +125,17 @@ l3bridge: l3bridge@204400 { reg = <0x204400 0x200>; }; + mpll: mpll@206000 { + compatible = "mstar,msc313-mpll"; + #clock-cells = <1>; + reg = <0x206000 0x200>; + clocks = <&xtal>; + clock-output-names = "mpll", "mpll_div_2", + "mpll_div_3", "mpll_div_4", + "mpll_div_5", "mpll_div_6", + "mpll_div_7", "mpll_div_10"; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>;