From patchwork Thu Nov 19 01:05:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11916315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF9CAC6369E for ; Thu, 19 Nov 2020 01:06:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67CFE2468D for ; Thu, 19 Nov 2020 01:06:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="v70/1Z6J" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727145AbgKSBFz (ORCPT ); Wed, 18 Nov 2020 20:05:55 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58806 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726616AbgKSBFy (ORCPT ); Wed, 18 Nov 2020 20:05:54 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AJ15lrJ035171; Wed, 18 Nov 2020 19:05:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605747947; bh=UWoxl2yYZsVlDBS/IWm40lAm6V7kxSUa0dxqsHXyHQs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v70/1Z6JLPnhLYR/NYfVAqBaneBLEdhLuv6SaBLwYKtILQlX4z+3eR2Ws8hrTBnc5 faGXEe4+eKzJF0zYAlPejJQuyHcwgtm0XK/LthmHJVmdizyNQDDxseK8nzWH1tvSYf OUG6sWYRH9gwHMny6hRDgK3mKiWMnt5n4bARuQ4s= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AJ15l5V052384 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 18 Nov 2020 19:05:47 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 18 Nov 2020 19:05:46 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 18 Nov 2020 19:05:46 -0600 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AJ15kFk056335; Wed, 18 Nov 2020 19:05:46 -0600 Received: from localhost ([10.250.38.244]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 0AJ15kVO076056; Wed, 18 Nov 2020 19:05:46 -0600 From: Suman Anna To: Bjorn Andersson , Mathieu Poirier , Rob Herring CC: Lokesh Vutla , , , , , Suman Anna Subject: [PATCH 1/3] dt-bindings: remoteproc: k3-r5f: Update bindings for J7200 SoCs Date: Wed, 18 Nov 2020 19:05:29 -0600 Message-ID: <20201119010531.21083-2-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201119010531.21083-1-s-anna@ti.com> References: <20201119010531.21083-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org The TI K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with 2 R5F cores each, one in each of the MCU and MAIN voltage domains. These clusters are a revised IP version compared to those present on J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible info relevant to these R5F clusters/subsystems on K3 J7200 SoCs. Signed-off-by: Suman Anna --- .../devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml index 4069f0f5e8fa..d905d614502b 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -32,6 +32,7 @@ properties: enum: - ti,am654-r5fss - ti,j721e-r5fss + - ti,j7200-r5fss power-domains: description: | @@ -95,6 +96,7 @@ patternProperties: enum: - ti,am654-r5f - ti,j721e-r5f + - ti,j7200-r5f reg: items: From patchwork Thu Nov 19 01:05:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11916317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3163EC6379D for ; Thu, 19 Nov 2020 01:06:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA8F7246E1 for ; Thu, 19 Nov 2020 01:06:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BrNxKzRK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727196AbgKSBF6 (ORCPT ); Wed, 18 Nov 2020 20:05:58 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:56774 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726616AbgKSBF6 (ORCPT ); Wed, 18 Nov 2020 20:05:58 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AJ15qOo070018; Wed, 18 Nov 2020 19:05:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605747952; bh=5PHh617lCH6Ug2fKlt6PCR+qvi9MScqYVwoln/9DNHg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BrNxKzRK2gAgNeFnlbq8v6FmpQ3NE+Xw/AnMW0bUBxBbYrHma8XZF3shJV/rEZlQB 6w3Eaefncw7J6tfezlhwAJmDHrBsxkhe3Iv5EkHGtULn8qtuSvRKEUSfOSdIVPmU5E uq5L2Tung0bUszlRfQeEIzHC1Klm+VT5Y0nGJgB4= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AJ15qpR052456 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 18 Nov 2020 19:05:52 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 18 Nov 2020 19:05:52 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 18 Nov 2020 19:05:52 -0600 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AJ15qWP029382; Wed, 18 Nov 2020 19:05:52 -0600 Received: from localhost ([10.250.38.244]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 0AJ15qRa076072; Wed, 18 Nov 2020 19:05:52 -0600 From: Suman Anna To: Bjorn Andersson , Mathieu Poirier , Rob Herring CC: Lokesh Vutla , , , , , Suman Anna Subject: [PATCH 2/3] remoteproc: k3-r5: Extend support to R5F clusters on J7200 SoCs Date: Wed, 18 Nov 2020 19:05:30 -0600 Message-ID: <20201119010531.21083-3-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201119010531.21083-1-s-anna@ti.com> References: <20201119010531.21083-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The K3 J7200 SoCs only have two dual-core Arm R5F clusters/subsystems with 2 R5F cores each. One cluster is present within the MCU voltage domain (MCU_R5FSS0), while the other is present in the MAIN voltage domain (MAIN_R5FSS0). The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Extend the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles. Logic for the second feature is added in the next patch. The integration of these clusters is very much similar to J721E SoCs otherwise. Signed-off-by: Suman Anna --- drivers/remoteproc/ti_k3_r5_remoteproc.c | 52 +++++++++++++++++++++++- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/ti_k3_r5_remoteproc.c index 40fa7a4d2ec8..66a32dcdd7d0 100644 --- a/drivers/remoteproc/ti_k3_r5_remoteproc.c +++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c @@ -38,6 +38,8 @@ #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000 +/* Available from J7200 SoCs onwards */ +#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000 /* R5 TI-SCI Processor Control Flags */ #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 @@ -67,16 +69,26 @@ enum cluster_mode { CLUSTER_MODE_LOCKSTEP, }; +/** + * struct k3_r5_soc_data - match data to handle SoC variations + * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC + */ +struct k3_r5_soc_data { + bool tcm_ecc_autoinit; +}; + /** * struct k3_r5_cluster - K3 R5F Cluster structure * @dev: cached device pointer * @mode: Mode to configure the Cluster - Split or LockStep * @cores: list of R5 cores within the cluster + * @soc_data: SoC-specific feature data for a R5FSS */ struct k3_r5_cluster { struct device *dev; enum cluster_mode mode; struct list_head cores; + const struct k3_r5_soc_data *soc_data; }; /** @@ -362,8 +374,16 @@ static int k3_r5_rproc_prepare(struct rproc *rproc) struct k3_r5_cluster *cluster = kproc->cluster; struct k3_r5_core *core = kproc->core; struct device *dev = kproc->dev; + u32 ctrl = 0, cfg = 0, stat = 0; + u64 boot_vec = 0; + bool mem_init_dis; int ret; + ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat); + if (ret < 0) + return ret; + mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS); + ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP) ? k3_r5_lockstep_release(cluster) : k3_r5_split_release(core); if (ret) { @@ -372,6 +392,17 @@ static int k3_r5_rproc_prepare(struct rproc *rproc) return ret; } + /* + * Newer IP revisions like on J7200 SoCs support h/w auto-initialization + * of TCMs, so there is no need to perform the s/w memzero. This bit is + * configurable through System Firmware, the default value does perform + * auto-init, but account for it in case it is disabled + */ + if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) { + dev_dbg(dev, "leveraging h/w init for TCM memories\n"); + return 0; + } + /* * Zero out both TCMs unconditionally (access from v8 Arm core is not * affected by ATCM & BTCM enable configuration values) so that ECC @@ -1309,15 +1340,23 @@ static int k3_r5_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev_of_node(dev); struct k3_r5_cluster *cluster; + const struct k3_r5_soc_data *data; int ret; int num_cores; + data = of_device_get_match_data(&pdev->dev); + if (!data) { + dev_err(dev, "SoC-specific data is not defined\n"); + return -ENODEV; + } + cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL); if (!cluster) return -ENOMEM; cluster->dev = dev; cluster->mode = CLUSTER_MODE_LOCKSTEP; + cluster->soc_data = data; INIT_LIST_HEAD(&cluster->cores); ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode); @@ -1367,9 +1406,18 @@ static int k3_r5_probe(struct platform_device *pdev) return 0; } +static const struct k3_r5_soc_data am65_j721e_soc_data = { + .tcm_ecc_autoinit = false, +}; + +static const struct k3_r5_soc_data j7200_soc_data = { + .tcm_ecc_autoinit = true, +}; + static const struct of_device_id k3_r5_of_match[] = { - { .compatible = "ti,am654-r5fss", }, - { .compatible = "ti,j721e-r5fss", }, + { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, }, + { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, }, + { .compatible = "ti,j7200-r5fss", .data = &j7200_soc_data, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, k3_r5_of_match); From patchwork Thu Nov 19 01:05:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11916319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E76C64E69 for ; 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b=FKBKZ2YeAi/YH4CrD4mhe8aauk2jvuiKF3pAYFMmTzXOyFMNz1UebmZMw5Pc8ThgC RcYegxAJdoO8/Drh2UdOjwhJQ9jW85xo/rfD/UskVg7QMK21nQJHDmDjNkm6szB+Ux eGRP/VDqwsfmGwYLpPRPY7d7PC+nwVSY0J8HXjFA= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AJ15wpr018646 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 18 Nov 2020 19:05:58 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 18 Nov 2020 19:05:57 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 18 Nov 2020 19:05:57 -0600 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AJ15vSq082346; Wed, 18 Nov 2020 19:05:57 -0600 Received: from localhost ([10.250.38.244]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 0AJ15vW7076087; Wed, 18 Nov 2020 19:05:57 -0600 From: Suman Anna To: Bjorn Andersson , Mathieu Poirier , Rob Herring CC: Lokesh Vutla , , , , , Suman Anna Subject: [PATCH 3/3] remoteproc: k3-r5: Adjust TCM sizes in Split-mode on J7200 SoCs Date: Wed, 18 Nov 2020 19:05:31 -0600 Message-ID: <20201119010531.21083-4-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201119010531.21083-1-s-anna@ti.com> References: <20201119010531.21083-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org The J7200 SoCs have a revised R5FSS IP that adds a unique feature w.r.t TCM sizing. Each R5F core in a cluster typically has 32 KB each of ATCM and BTCM, with only the Core0 TCMs usable in LockStep mode. This revised IP however doubles the total available TCM in LockStep mode by making the Core1 TCM visible immediately after the corresponding Core0 TCM. The R5F DT nodes on the J7200 SoCs define double (64 KB) the normal TCM size (32 KB) for R5F Core0 for each of ATCM and BTCM to represent the above. This increased TCM memory is only usable in LockStep-mode, and has to be adjusted to the normal 32 KB size in Split mode. Enhance the TI K3 R5F remoteproc for this logic through a new function. The adjustment is a no-op on prior SoCs and relies on the correct DTS node sizes in LockStep-mode on applicable SoCs. Signed-off-by: Suman Anna Reviewed-by: Mathieu Poirier --- drivers/remoteproc/ti_k3_r5_remoteproc.c | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/ti_k3_r5_remoteproc.c index 66a32dcdd7d0..62b5a4c29456 100644 --- a/drivers/remoteproc/ti_k3_r5_remoteproc.c +++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c @@ -71,9 +71,11 @@ enum cluster_mode { /** * struct k3_r5_soc_data - match data to handle SoC variations + * @tcm_is_double: flag to denote the larger unified TCMs in certain modes * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC */ struct k3_r5_soc_data { + bool tcm_is_double; bool tcm_ecc_autoinit; }; @@ -886,6 +888,43 @@ static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc) of_reserved_mem_device_release(kproc->dev); } +/* + * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs, + * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both + * cores are usable in Split-mode, but only the Core0 TCMs can be used in + * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by + * leveraging the Core1 TCMs as well in certain modes where they would have + * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by + * making a Core1 TCM visible immediately after the corresponding Core0 TCM. + * The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the + * dts representation reflects this increased size on supported SoCs. The Core0 + * TCM sizes therefore have to be adjusted to only half the original size in + * Split mode. + */ +static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc) +{ + struct k3_r5_cluster *cluster = kproc->cluster; + struct k3_r5_core *core = kproc->core; + struct device *cdev = core->dev; + struct k3_r5_core *core0; + + if (cluster->mode == CLUSTER_MODE_LOCKSTEP || + !cluster->soc_data->tcm_is_double) + return; + + core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem); + if (core == core0) { + WARN_ON(core->mem[0].size != SZ_64K); + WARN_ON(core->mem[1].size != SZ_64K); + + core->mem[0].size /= 2; + core->mem[1].size /= 2; + + dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n", + core->mem[0].size, core->mem[1].size); + } +} + static int k3_r5_cluster_rproc_init(struct platform_device *pdev) { struct k3_r5_cluster *cluster = platform_get_drvdata(pdev); @@ -933,6 +972,8 @@ static int k3_r5_cluster_rproc_init(struct platform_device *pdev) goto err_config; } + k3_r5_adjust_tcm_sizes(kproc); + ret = k3_r5_reserved_mem_init(kproc); if (ret) { dev_err(dev, "reserved memory init failed, ret = %d\n", @@ -1407,10 +1448,12 @@ static int k3_r5_probe(struct platform_device *pdev) } static const struct k3_r5_soc_data am65_j721e_soc_data = { + .tcm_is_double = false, .tcm_ecc_autoinit = false, }; static const struct k3_r5_soc_data j7200_soc_data = { + .tcm_is_double = true, .tcm_ecc_autoinit = true, };