From patchwork Thu Nov 19 05:55:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11916491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2D39C6379D for ; Thu, 19 Nov 2020 05:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BD2624707 for ; Thu, 19 Nov 2020 05:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726252AbgKSF4D (ORCPT ); Thu, 19 Nov 2020 00:56:03 -0500 Received: from mga02.intel.com ([134.134.136.20]:15558 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725802AbgKSF4D (ORCPT ); Thu, 19 Nov 2020 00:56:03 -0500 IronPort-SDR: l9esvW2kW7Ix5KfB7j6CmjYZ0vySf5e2UMqAbm6WrDXyrrF5Y42q7egOwZ08wAZm4wWCbqdx1B PS3LXMgRnBJQ== X-IronPort-AV: E=McAfee;i="6000,8403,9809"; a="158271218" X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="158271218" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2020 21:56:02 -0800 IronPort-SDR: 1bCCA+NdNA2ugfiPUE/ENQRYXB7aH4UUYJubJYaBUuS7yYt+RkYHnv1B0XKC3HdSzC3PIpFdkk twdA1BwOXQXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="325857376" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga003.jf.intel.com with ESMTP; 18 Nov 2020 21:56:00 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v8 1/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC Date: Thu, 19 Nov 2020 13:55:49 +0800 Message-Id: <20201119055551.26493-2-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add QSPI controller support for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/Kconfig | 2 +- drivers/spi/spi-cadence-quadspi.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d2c976e55b8b..926da61eee5a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -203,7 +203,7 @@ config SPI_CADENCE config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || COMPILE_TEST) + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST) help Enable support for the Cadence Quad SPI Flash controller. diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 40938cf3806d..d7b10c46fa70 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "ti,am654-ospi", .data = &am654_ospi, }, + { + .compatible = "intel,lgm-qspi", + }, { /* end of table */ } }; From patchwork Thu Nov 19 05:55:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11916493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EB8DC2D0E4 for ; Thu, 19 Nov 2020 05:56:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0EC622227 for ; Thu, 19 Nov 2020 05:56:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726287AbgKSF4G (ORCPT ); Thu, 19 Nov 2020 00:56:06 -0500 Received: from mga01.intel.com ([192.55.52.88]:3800 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725802AbgKSF4G (ORCPT ); Thu, 19 Nov 2020 00:56:06 -0500 IronPort-SDR: p+7HTTdh4xmVgjg9Y3dzWBMtIc14P/zkf50gIet7MskIzV9/h1/y4WTxTzDTS8iUlRcY/H4VfQ pZvS64ZPxRTA== X-IronPort-AV: E=McAfee;i="6000,8403,9809"; a="189321995" X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="189321995" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2020 21:56:06 -0800 IronPort-SDR: NIHVA54biUQpFvy7sdiau2+F6e5Jwb4O9y/su962MifuStnvod73OwgXTFjM4oHJJmoYFlNpcD 1tvhIQEUad5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="401404952" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga001.jf.intel.com with ESMTP; 18 Nov 2020 21:56:03 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v8 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC Date: Thu, 19 Nov 2020 13:55:50 +0800 Message-Id: <20201119055551.26493-3-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use Direct Access Controller(DAC). This patch adds a quirk to disable the Direct Access Controller for data transfer instead it uses indirect data transfe DAC bit resets to 1 so there is no need to explicitly set it. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index d7b10c46fa70..d12b765e87be 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1101,10 +1101,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) writel(cqspi->fifo_depth * cqspi->fifo_width / 8, cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); - /* Enable Direct Access Controller */ - reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); - reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; - writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + /* Disable direct access controller */ + if (!cqspi->use_direct_mode) { + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + } cqspi_controller_enable(cqspi, 1); } @@ -1388,6 +1390,10 @@ static const struct cqspi_driver_platdata am654_ospi = { .quirks = CQSPI_NEEDS_WR_DELAY, }; +static const struct cqspi_driver_platdata intel_lgm_qspi = { + .quirks = CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1403,6 +1409,7 @@ static const struct of_device_id cqspi_dt_ids[] = { }, { .compatible = "intel,lgm-qspi", + .data = &intel_lgm_qspi, }, { /* end of table */ } }; From patchwork Thu Nov 19 05:55:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11916495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B434C63798 for ; Thu, 19 Nov 2020 05:56:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0BAC9238E6 for ; Thu, 19 Nov 2020 05:56:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726300AbgKSF4L (ORCPT ); Thu, 19 Nov 2020 00:56:11 -0500 Received: from mga04.intel.com ([192.55.52.120]:3690 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725802AbgKSF4K (ORCPT ); Thu, 19 Nov 2020 00:56:10 -0500 IronPort-SDR: Dn4PVlBKHxUhQ7nAXtQU0mgJzVMWjW4N35fMmf+2GrDV6KsjwcjRegk/RT9Dx9NedZY9tlFiuR aX/v3EpaEIMg== X-IronPort-AV: E=McAfee;i="6000,8403,9809"; a="168665372" X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="168665372" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2020 21:56:09 -0800 IronPort-SDR: 9uBxVasPUCKDhPaAGMzn6MMbAfroMvWRRlAJNKMORKZJLjhUcYfcGMzLzg2rdvJozCE4gS97oK vzcYGyCU3OXw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="544867340" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga005.jf.intel.com with ESMTP; 18 Nov 2020 21:56:06 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Date: Thu, 19 Nov 2020 13:55:51 +0800 Message-Id: <20201119055551.26493-4-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index d12b765e87be..337778f75d5d 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -38,6 +38,7 @@ /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1) struct cqspi_st; @@ -75,6 +76,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1049,6 +1051,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev, static int cqspi_of_get_pdata(struct cqspi_st *cqspi) { + const struct cqspi_driver_platdata *ddata; struct device *dev = &cqspi->pdev->dev; struct device_node *np = dev->of_node; @@ -1070,6 +1073,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + ddata = of_device_get_match_data(dev); + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) { + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) { + dev_err(dev, "couldn't determine number of cs\n"); + return -ENXIO; + } + } + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1302,6 +1313,9 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); @@ -1391,6 +1405,7 @@ static const struct cqspi_driver_platdata am654_ospi = { }; static const struct cqspi_driver_platdata intel_lgm_qspi = { + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT, .quirks = CQSPI_DISABLE_DAC_MODE, };