From patchwork Thu Nov 19 14:08:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11917517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C24AEC6369E for ; Thu, 19 Nov 2020 14:09:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FF79246D3 for ; Thu, 19 Nov 2020 14:09:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zt4PA7FG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727431AbgKSOJC (ORCPT ); Thu, 19 Nov 2020 09:09:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727410AbgKSOJB (ORCPT ); Thu, 19 Nov 2020 09:09:01 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2001BC0613CF for ; Thu, 19 Nov 2020 06:09:01 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id f11so8433763lfs.3 for ; Thu, 19 Nov 2020 06:09:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lEgF06r26Rcxa35r0APH5pRvcVW1Iw0xWvAo4CMMUy4=; b=zt4PA7FGZ/n/66SJI0xyxWUIqhYKC9i7I5QpC/gRFM0EGMWjCxwiHOmFr4tmVV3SuF 2jrlV4mvT2me5RWuLgvLBvUQzwe89EG6O0RgJVYXNBkPAZ84YTvTOHjh2FDArHQQl6kv tG2c6fswGWDvkmyckHjQX6lVkUy4NfdyFabm0QQ/njOBxk6hURn6RiuXuT7tNAXVjmd0 2Qo4RLHqmLPvwrzBkedysAVsn+6PhklqhvYcrWDRYUkCkY5x6nAay0XtzkDGQsJqr/SI h4n9FKpX0J9broTKAdiM5AQrXwxAWa1rgRzp67YLwHmzeipmOkFDdykmW02U4OtIBrra uoBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lEgF06r26Rcxa35r0APH5pRvcVW1Iw0xWvAo4CMMUy4=; b=jswZPPwPZY0V0O3C0SWLeq3cGZHuv7iAxBxWA+JhLyj5a7hgKX3U4a5oUV+FDpbVHU zU3WPRVRsFWgRxyb18+TWwsBXUNHePkQ/mDjibgIZFkCh///USFcwaAtEu3fTjO9P/xp Y/MrJ4M+zTwGVTZu1Mmk30Rdr/98j7pTIW+cIf6a82vlE3Jb0W9lmE8ichzKsCmnHmDU iAzB0zPPyA5UppK2DkuzG74co83QAs9RhbzuWHyw/LIZ7kG4jlzKcJzr4y6PDzxCPCtA +P34vL+nVfo7680WOICh4VqKrZYs5DbH7k/tZxUblv9Kod6UvdN6TvNeHkthzTi/MG5K 2gRA== X-Gm-Message-State: AOAM531OSyosjpMAq1iXSkKlm9ZcnatuNwv52ilAiiL1KZD6PqRxFlul AI9krnB5UYJbfPqglwdF/zKVDw== X-Google-Smtp-Source: ABdhPJxwB041b+gc0//i0TT066vYP1a7BkcSviQ6yguhzBXKfVwCvnyRGiZNGKrUSF17sFmSM8yx+A== X-Received: by 2002:a19:84c5:: with SMTP id g188mr6645527lfd.270.1605794938293; Thu, 19 Nov 2020 06:08:58 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h12sm4024706lfl.74.2020.11.19.06.08.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 06:08:57 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v2 1/6] dt-bindings: remoteproc: Add binding doc for PRU cores in the PRU-ICSS Date: Thu, 19 Nov 2020 15:08:45 +0100 Message-Id: <20201119140850.12268-2-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> References: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS or simply PRUSS) on various TI SoCs consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. The K3 AM65x amd J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG IP on AM65x SoCs has two PRU cores, two auxiliary custom PRU cores called Real Time Units (RTUs). The K3 AM65x SR2.0 and J721E SoCs have a revised version of the ICSSG IP, and include two additional custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs). This patch adds the bindings for these PRU cores. The binding covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; Keystone 2 architecture based 66AK2G SoC; and the K3 architecture based SoCs - AM65x and J721E. The Davinci based OMAPL138 SoCs will be covered in a future patch. Co-developed-by: Roger Quadros Signed-off-by: Roger Quadros Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v1->v2: - fix below yamllint warnings: ./Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml:37:6: [warning] wrong indentation: expected 6 but found 5 (indentation) ./Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml:92:2: [warning] wrong indentation: expected 2 but found 1 (indentation) --- .../bindings/remoteproc/ti,pru-rproc.yaml | 214 ++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml new file mode 100644 index 000000000000..63071eef1632 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Programmable Realtime Unit (PRU) cores + +maintainers: + - Suman Anna + +description: | + Each Programmable Real-Time Unit and Industrial Communication Subsystem + (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called + Programmable Real-Time Units (PRUs), each represented by a node. Each PRU + core has a dedicated Instruction RAM, Control and Debug register sets, and + use the Data RAMs present within the PRU-ICSS for code execution. + + The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary + PRU cores called RTUs with slightly different IP integration. The K3 SoCs + containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two + auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU + or Tx_PRU core can also be used independently like a PRU, or alongside a + corresponding PRU core to provide/implement auxiliary functionality/support. + + Each PRU, RTU or Tx_PRU core node should be defined as a child node of the + corresponding PRU-ICSS node. Each node can optionally be rendered inactive by + using the standard DT string property, "status". + + Please see the overall PRU-ICSS bindings document for additional details + including a complete example, + Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml + +properties: + compatible: + enum: + - ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only) + - ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only) + - ti,am5728-pru # for AM57xx SoC family + - ti,k2g-pru # for 66AK2G SoC family + - ti,am654-pru # for PRUs in K3 AM65x SoC family + - ti,am654-rtu # for RTUs in K3 AM65x SoC family + - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs + - ti,j721e-pru # for PRUs in K3 J721E SoC family + - ti,j721e-rtu # for RTUs in K3 J721E SoC family + - ti,j721e-tx-pru # for Tx_PRUs in K3 J721E SoC family + + reg: + items: + - description: Address and Size of the PRU Instruction RAM + - description: Address and Size of the PRU CTRL sub-module registers + - description: Address and Size of the PRU Debug sub-module registers + + reg-names: + items: + - const: iram + - const: control + - const: debug + + firmware-name: + description: | + Should contain the name of the default firmware image + file located on the firmware search path. + +if: + properties: + compatible: + enum: + - ti,am654-rtu + - ti,j721e-rtu +then: + properties: + $nodename: + pattern: "^rtu@[0-9a-f]+$" +else: + if: + properties: + compatible: + enum: + - ti,am654-tx-pru + - ti,j721e-tx-pru + then: + properties: + $nodename: + pattern: "^txpru@[0-9a-f]+" + else: + properties: + $nodename: + pattern: "^pru@[0-9a-f]+$" + +required: + - compatible + - reg + - reg-names + - firmware-name + +additionalProperties: false + +examples: + - | + /* AM33xx PRU-ICSS */ + pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ + compatible = "ti,sysc-pruss", "ti,sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x300000 0x80000>; + + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pru0: pru@34000 { + compatible = "ti,am3356-pru"; + reg = <0x34000 0x2000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@38000 { + compatible = "ti,am3356-pru"; + reg = <0x38000 0x2000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + }; + }; + + - | + /* AM65x SR2.0 ICSSG */ + #include + + icssg0: icssg@b000000 { + compatible = "ti,am654-icssg"; + reg = <0xb000000 0x80000>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000000 0x80000>; + + icssg0_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pru0_0: pru@34000 { + compatible = "ti,am654-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_0-fw"; + }; + + rtu0_0: rtu@4000 { + compatible = "ti,am654-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_0-fw"; + }; + + tx_pru0_0: txpru@a000 { + compatible = "ti,am654-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_0-fw"; + }; + + pru0_1: pru@38000 { + compatible = "ti,am654-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_1-fw"; + }; + + rtu0_1: rtu@6000 { + compatible = "ti,am654-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_1-fw"; + }; + + tx_pru0_1: txpru@c000 { + compatible = "ti,am654-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_1-fw"; + }; + }; From patchwork Thu Nov 19 14:08:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11917527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C395C8300C for ; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id h12sm4024706lfl.74.2020.11.19.06.08.58 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 06:08:59 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v2 2/6] remoteproc/pru: Add a PRU remoteproc driver Date: Thu, 19 Nov 2020 15:08:46 +0100 Message-Id: <20201119140850.12268-3-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> References: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit Subsystem (PRUSS) consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. This patch adds a remoteproc platform driver for managing the individual PRU RISC cores life cycle. The PRUs do not have a unified address space (have an Instruction RAM and a primary Data RAM at both 0x0). The PRU remoteproc driver therefore uses a custom remoteproc core ELF loader ops. The added .da_to_va ops is only used to provide translations for the PRU Data RAMs. This remoteproc driver does not have support for error recovery and system suspend/resume features. Different compatibles are used to allow providing scalability for instance-specific device data if needed. The driver uses a default firmware-name retrieved from device-tree for each PRU core, and the firmwares are expected to be present in the standard Linux firmware search paths. They can also be adjusted by userspace if required through the sysfs interface provided by the remoteproc core. The PRU remoteproc driver uses a client-driven boot methodology: it does _not_ support auto-boot so that the PRU load and boot is dictated by the corresponding client drivers for achieving various usecases. This allows flexibility for the client drivers or applications to set a firmware name (if needed) based on their desired functionality and boot the PRU. The sysfs bind and unbind attributes have also been suppressed so that the PRU devices cannot be unbound and thereby shutdown a PRU from underneath a PRU client driver. The driver currently supports the AM335x, AM437x, AM57xx and 66AK2G SoCs, and support for other TI SoCs will be added in subsequent patches. Co-developed-by: Andrew F. Davis Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v1->v2: - Use PRU_IRAM_ADDR_MASK definition instead of raw 0x3ffff. - Convert 'len' argument from int to size_t type in all *da_to_va. - Return 0 in case of missing .resource_table for pru_rproc_parse_fw() (move the logic from patch #3 where it was corrected). --- drivers/remoteproc/Kconfig | 12 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/pru_rproc.c | 435 +++++++++++++++++++++++++++++++++ 3 files changed, 448 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index d99548fb5dde..3e3865a7cd78 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -125,6 +125,18 @@ config KEYSTONE_REMOTEPROC It's safe to say N here if you're not interested in the Keystone DSPs or just want to use a bare minimum kernel. +config PRU_REMOTEPROC + tristate "TI PRU remoteproc support" + depends on TI_PRUSS + default TI_PRUSS + help + Support for TI PRU remote processors present within a PRU-ICSS + subsystem via the remote processor framework. + + Say Y or M here to support the Programmable Realtime Unit (PRU) + processors on various TI SoCs. It's safe to say N here if you're + not interested in the PRU or if you are unsure. + config QCOM_PIL_INFO tristate diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index da2ace4ec86c..bb26c9e4ef9c 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o +obj-$(CONFIG_PRU_REMOTEPROC) += pru_rproc.o obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c new file mode 100644 index 000000000000..b686f19f9b1a --- /dev/null +++ b/drivers/remoteproc/pru_rproc.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PRU-ICSS remoteproc driver for various TI SoCs + * + * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author(s): + * Suman Anna + * Andrew F. Davis + * Grzegorz Jaszczyk for Texas Instruments + */ + +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" +#include "remoteproc_elf_helpers.h" + +/* PRU_ICSS_PRU_CTRL registers */ +#define PRU_CTRL_CTRL 0x0000 +#define PRU_CTRL_STS 0x0004 + +/* CTRL register bit-fields */ +#define CTRL_CTRL_SOFT_RST_N BIT(0) +#define CTRL_CTRL_EN BIT(1) +#define CTRL_CTRL_SLEEPING BIT(2) +#define CTRL_CTRL_CTR_EN BIT(3) +#define CTRL_CTRL_SINGLE_STEP BIT(8) +#define CTRL_CTRL_RUNSTATE BIT(15) + +/* PRU Core IRAM address masks */ +#define PRU_IRAM_ADDR_MASK 0x3ffff +#define PRU0_IRAM_ADDR_MASK 0x34000 +#define PRU1_IRAM_ADDR_MASK 0x38000 + +/* PRU device addresses for various type of PRU RAMs */ +#define PRU_IRAM_DA 0 /* Instruction RAM */ +#define PRU_PDRAM_DA 0 /* Primary Data RAM */ +#define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ +#define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ + +/** + * enum pru_iomem - PRU core memory/register range identifiers + * + * @PRU_IOMEM_IRAM: PRU Instruction RAM range + * @PRU_IOMEM_CTRL: PRU Control register range + * @PRU_IOMEM_DEBUG: PRU Debug register range + * @PRU_IOMEM_MAX: just keep this one at the end + */ +enum pru_iomem { + PRU_IOMEM_IRAM = 0, + PRU_IOMEM_CTRL, + PRU_IOMEM_DEBUG, + PRU_IOMEM_MAX, +}; + +/** + * struct pru_rproc - PRU remoteproc structure + * @id: id of the PRU core within the PRUSS + * @dev: PRU core device pointer + * @pruss: back-reference to parent PRUSS structure + * @rproc: remoteproc pointer for this PRU core + * @mem_regions: data for each of the PRU memory regions + * @fw_name: name of firmware image used during loading + */ +struct pru_rproc { + int id; + struct device *dev; + struct pruss *pruss; + struct rproc *rproc; + struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; + const char *fw_name; +}; + +static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) +{ + return readl_relaxed(pru->mem_regions[PRU_IOMEM_CTRL].va + reg); +} + +static inline +void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) +{ + writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); +} + +static int pru_rproc_start(struct rproc *rproc) +{ + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + u32 val; + + dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", + pru->id, (rproc->bootaddr >> 2)); + + val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); + pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + + return 0; +} + +static int pru_rproc_stop(struct rproc *rproc) +{ + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + u32 val; + + dev_dbg(dev, "stopping PRU%d\n", pru->id); + + val = pru_control_read_reg(pru, PRU_CTRL_CTRL); + val &= ~CTRL_CTRL_EN; + pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + + return 0; +} + +/* + * Convert PRU device address (data spaces only) to kernel virtual address. + * + * Each PRU has access to all data memories within the PRUSS, accessible at + * different ranges. So, look through both its primary and secondary Data + * RAMs as well as any shared Data RAM to convert a PRU device address to + * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data + * RAM1 is primary Data RAM for PRU1. + */ +static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len) +{ + struct pruss_mem_region dram0, dram1, shrd_ram; + struct pruss *pruss = pru->pruss; + u32 offset; + void *va = NULL; + + if (len == 0) + return NULL; + + dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0]; + dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1]; + /* PRU1 has its local RAM addresses reversed */ + if (pru->id == 1) + swap(dram0, dram1); + shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2]; + + if (da >= PRU_PDRAM_DA && da + len <= PRU_PDRAM_DA + dram0.size) { + offset = da - PRU_PDRAM_DA; + va = (__force void *)(dram0.va + offset); + } else if (da >= PRU_SDRAM_DA && + da + len <= PRU_SDRAM_DA + dram1.size) { + offset = da - PRU_SDRAM_DA; + va = (__force void *)(dram1.va + offset); + } else if (da >= PRU_SHRDRAM_DA && + da + len <= PRU_SHRDRAM_DA + shrd_ram.size) { + offset = da - PRU_SHRDRAM_DA; + va = (__force void *)(shrd_ram.va + offset); + } + + return va; +} + +/* + * Convert PRU device address (instruction space) to kernel virtual address. + * + * A PRU does not have an unified address space. Each PRU has its very own + * private Instruction RAM, and its device address is identical to that of + * its primary Data RAM device address. + */ +static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len) +{ + u32 offset; + void *va = NULL; + + if (len == 0) + return NULL; + + if (da >= PRU_IRAM_DA && + da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) { + offset = da - PRU_IRAM_DA; + va = (__force void *)(pru->mem_regions[PRU_IOMEM_IRAM].va + + offset); + } + + return va; +} + +/* + * Provide address translations for only PRU Data RAMs through the remoteproc + * core for any PRU client drivers. The PRU Instruction RAM access is restricted + * only to the PRU loader code. + */ +static void *pru_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) +{ + struct pru_rproc *pru = rproc->priv; + + return pru_d_da_to_va(pru, da, len); +} + +/* PRU-specific address translator used by PRU loader. */ +static void *pru_da_to_va(struct rproc *rproc, u64 da, size_t len, bool is_iram) +{ + struct pru_rproc *pru = rproc->priv; + void *va; + + if (is_iram) + va = pru_i_da_to_va(pru, da, len); + else + va = pru_d_da_to_va(pru, da, len); + + return va; +} + +static struct rproc_ops pru_rproc_ops = { + .start = pru_rproc_start, + .stop = pru_rproc_stop, + .da_to_va = pru_rproc_da_to_va, +}; + +static int +pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) +{ + struct device *dev = &rproc->dev; + struct elf32_hdr *ehdr; + struct elf32_phdr *phdr; + int i, ret = 0; + const u8 *elf_data = fw->data; + + ehdr = (struct elf32_hdr *)elf_data; + phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff); + + /* go through the available ELF segments */ + for (i = 0; i < ehdr->e_phnum; i++, phdr++) { + u32 da = phdr->p_paddr; + u32 memsz = phdr->p_memsz; + u32 filesz = phdr->p_filesz; + u32 offset = phdr->p_offset; + bool is_iram; + void *ptr; + + if (phdr->p_type != PT_LOAD) + continue; + + dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", + phdr->p_type, da, memsz, filesz); + + if (filesz > memsz) { + dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n", + filesz, memsz); + ret = -EINVAL; + break; + } + + if (offset + filesz > fw->size) { + dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n", + offset + filesz, fw->size); + ret = -EINVAL; + break; + } + + /* grab the kernel address for this device address */ + is_iram = phdr->p_flags & PF_X; + ptr = pru_da_to_va(rproc, da, memsz, is_iram); + if (!ptr) { + dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); + ret = -EINVAL; + break; + } + + /* skip the memzero logic performed by remoteproc ELF loader */ + if (!phdr->p_filesz) + continue; + + memcpy(ptr, elf_data + phdr->p_offset, filesz); + } + + return ret; +} + +/* + * Use a custom parse_fw callback function for dealing with PRU firmware + * specific sections. + */ +static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) +{ + int ret; + + /* load optional rsc table */ + ret = rproc_elf_load_rsc_table(rproc, fw); + if (ret == -EINVAL) + dev_dbg(&rproc->dev, "no resource table found for this fw\n"); + else if (ret) + return ret; + + return 0; +} + +/* + * Compute PRU id based on the IRAM addresses. The PRU IRAMs are + * always at a particular offset within the PRUSS address space. + */ +static int pru_rproc_set_id(struct pru_rproc *pru) +{ + int ret = 0; + + switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { + case PRU0_IRAM_ADDR_MASK: + pru->id = 0; + break; + case PRU1_IRAM_ADDR_MASK: + pru->id = 1; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int pru_rproc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct platform_device *ppdev = to_platform_device(dev->parent); + struct pru_rproc *pru; + const char *fw_name; + struct rproc *rproc = NULL; + struct resource *res; + int i, ret; + const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; + + ret = of_property_read_string(np, "firmware-name", &fw_name); + if (ret) { + dev_err(dev, "unable to retrieve firmware-name %d\n", ret); + return ret; + } + + rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name, + sizeof(*pru)); + if (!rproc) { + dev_err(dev, "rproc_alloc failed\n"); + return -ENOMEM; + } + /* use a custom load function to deal with PRU-specific quirks */ + rproc->ops->load = pru_rproc_load_elf_segments; + + /* use a custom parse function to deal with PRU-specific resources */ + rproc->ops->parse_fw = pru_rproc_parse_fw; + + /* error recovery is not supported for PRUs */ + rproc->recovery_disabled = true; + + /* + * rproc_add will auto-boot the processor normally, but this is not + * desired with PRU client driven boot-flow methodology. A PRU + * application/client driver will boot the corresponding PRU + * remote-processor as part of its state machine either through the + * remoteproc sysfs interface or through the equivalent kernel API. + */ + rproc->auto_boot = false; + + pru = rproc->priv; + pru->dev = dev; + pru->pruss = platform_get_drvdata(ppdev); + pru->rproc = rproc; + pru->fw_name = fw_name; + + for (i = 0; i < ARRAY_SIZE(mem_names); i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + mem_names[i]); + pru->mem_regions[i].va = devm_ioremap_resource(dev, res); + if (IS_ERR(pru->mem_regions[i].va)) { + dev_err(dev, "failed to parse and map memory resource %d %s\n", + i, mem_names[i]); + ret = PTR_ERR(pru->mem_regions[i].va); + return ret; + } + pru->mem_regions[i].pa = res->start; + pru->mem_regions[i].size = resource_size(res); + + dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n", + mem_names[i], &pru->mem_regions[i].pa, + pru->mem_regions[i].size, pru->mem_regions[i].va); + } + + ret = pru_rproc_set_id(pru); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, rproc); + + ret = devm_rproc_add(dev, pru->rproc); + if (ret) { + dev_err(dev, "rproc_add failed: %d\n", ret); + return ret; + } + + dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); + + return 0; +} + +static int pru_rproc_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rproc *rproc = platform_get_drvdata(pdev); + + dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name); + + return 0; +} + +static const struct of_device_id pru_rproc_match[] = { + { .compatible = "ti,am3356-pru", }, + { .compatible = "ti,am4376-pru", }, + { .compatible = "ti,am5728-pru", }, + { .compatible = "ti,k2g-pru", }, + {}, +}; +MODULE_DEVICE_TABLE(of, pru_rproc_match); + +static struct platform_driver pru_rproc_driver = { + .driver = { + .name = "pru-rproc", + .of_match_table = pru_rproc_match, + .suppress_bind_attrs = true, + }, + .probe = pru_rproc_probe, + .remove = pru_rproc_remove, +}; +module_platform_driver(pru_rproc_driver); + +MODULE_AUTHOR("Suman Anna "); +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_AUTHOR("Grzegorz Jaszczyk "); +MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Nov 19 14:08:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11917519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84594C63798 for ; Thu, 19 Nov 2020 14:09:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2FB1224655 for ; Thu, 19 Nov 2020 14:09:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VQqiT+NM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727473AbgKSOJF (ORCPT ); Thu, 19 Nov 2020 09:09:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727468AbgKSOJE (ORCPT ); Thu, 19 Nov 2020 09:09:04 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C72C6C0617A7 for ; Thu, 19 Nov 2020 06:09:02 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id p12so6346920ljc.9 for ; Thu, 19 Nov 2020 06:09:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FsdTtJ0Z5HfS2nZYAe6Ixk3EYtj2SNbasyoCbnMMqyo=; b=VQqiT+NMwaVe045YES0fH6Nb9zRyHrjj70Yeu7mxLjYkCMmR2ikFGpZNignrI/OW4k f6KMdTF2bG+jPjl4B68DvmMGGXfhEnh8ZCWtEfsGfTjtge7fDREH/AW9jeY/IzLAMFLF cw3nyC858zFen6shUjRPAURXP7HsAfetE70/cy+rAPo5CbMfAFz6MDPL7sXaAaUJinmB g+hV6fDz1r9sWG1bs7kbdSOQ2GMB2McGyojj5cDLCsjDfuTz45JebuLwu/dc7S/dcuII Nfl1na9AGi/nz/pmCSvWaOOOMkfFowxvTpeKQtH2XN89Tk+bP8wg+iYTgSi5vuzGSkFG qqSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FsdTtJ0Z5HfS2nZYAe6Ixk3EYtj2SNbasyoCbnMMqyo=; b=CH8lC4Ynh44OuRiHzzv+GkOIedGiNVnusF3P2ycDp8fcJBxiWIXmqShSH/72uzdSzj Ow3jjbrR/57azVCD6oXdXXq7gHt0T6MQuihKKLflCprXd20g/nBEYDE42WQqYMW93vs8 KsbTMa8JfOC+X3bUKCst+nZ9JK3TuZ5DInU95IQn7gfIHkELbK/C2Sl2SW0cGdjqPJPn 7S0obpos2FX8OiMZnC9T7djiJNEeIUenBVra8enQGUOZGXxZpHElt2ttFcgh4DBQ6krt uGtaPzMlpx0M8tBX1JBgICYrO28TXW/r3uUowxWCLApEJMLOmihVJiJszKDGRQIe8Z89 0JwQ== X-Gm-Message-State: AOAM530vi7kBNQhDwj1uCJia9nCPdF1gQSMlN8Ux4y50ZCDZa6Z58GQE 4TbILrHaaDyQk3VIG79g6DovVA== X-Google-Smtp-Source: ABdhPJw/V773ktVNcdbt/3ucGGu4d+b/nB55UjlfHmDN3VEUW9RZ+3HSKCui8IEJKg/FpPeV1Q8qeA== X-Received: by 2002:a2e:8e7b:: with SMTP id t27mr6197740ljk.129.1605794941168; Thu, 19 Nov 2020 06:09:01 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h12sm4024706lfl.74.2020.11.19.06.08.59 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 06:09:00 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v2 3/6] remoteproc/pru: Add support for PRU specific interrupt configuration Date: Thu, 19 Nov 2020 15:08:47 +0100 Message-Id: <20201119140850.12268-4-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> References: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The firmware blob can contain optional ELF sections: .resource_table section and .pru_irq_map one. The second one contains the PRUSS interrupt mapping description, which needs to be setup before powering on the PRU core. To avoid RAM wastage this ELF section is not mapped to any ELF segment (by the firmware linker) and therefore is not loaded to PRU memory. The PRU interrupt configuration is handled within the PRUSS INTC irqchip driver and leverages the system events to interrupt channels and host interrupts mapping configuration. Relevant irq routing information is passed through a special .pru_irq_map ELF section (for interrupts routed to and used by PRU cores) or via the PRU application's device tree node (for interrupts routed to and used by the main CPU). The mappings are currently programmed during the booting/shutdown of the PRU. The interrupt configuration passed through .pru_irq_map ELF section is optional. It varies on specific firmware functionality and therefore have to be unwinded during PRU stop and performed again during PRU start. Co-developed-by: Suman Anna Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v1->v2: Address Suman comments: - Rework pru_rproc_find_interrupt_map() style: get rid of generic ELF helpers macros usage and stick with elf32_* related structs instead (in order to be consistent with pru_rproc_load_elf_segments() style). - Improve comments and dev_err msgs in pru_rproc_find_interrupt_map(). - Use u8 instead of ssize_t for evt_count. --- drivers/remoteproc/pru_rproc.c | 180 +++++++++++++++++++++++++++++++++ drivers/remoteproc/pru_rproc.h | 46 +++++++++ 2 files changed, 226 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.h diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index b686f19f9b1a..c68c3d6bfddd 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -11,13 +11,16 @@ */ #include +#include #include #include +#include #include #include #include "remoteproc_internal.h" #include "remoteproc_elf_helpers.h" +#include "pru_rproc.h" /* PRU_ICSS_PRU_CTRL registers */ #define PRU_CTRL_CTRL 0x0000 @@ -42,6 +45,8 @@ #define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ #define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ +#define MAX_PRU_SYS_EVENTS 160 + /** * enum pru_iomem - PRU core memory/register range identifiers * @@ -65,6 +70,10 @@ enum pru_iomem { * @rproc: remoteproc pointer for this PRU core * @mem_regions: data for each of the PRU memory regions * @fw_name: name of firmware image used during loading + * @mapped_irq: virtual interrupt numbers of created fw specific mapping + * @pru_interrupt_map: pointer to interrupt mapping description (firmware) + * @pru_interrupt_map_sz: pru_interrupt_map size + * @evt_count: number of mapped events */ struct pru_rproc { int id; @@ -73,6 +82,10 @@ struct pru_rproc { struct rproc *rproc; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; const char *fw_name; + int *mapped_irq; + struct pru_irq_rsc *pru_interrupt_map; + size_t pru_interrupt_map_sz; + u8 evt_count; }; static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) @@ -86,15 +99,107 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static void pru_dispose_irq_mapping(struct pru_rproc *pru) +{ + while (pru->evt_count--) { + if (pru->mapped_irq[pru->evt_count] > 0) + irq_dispose_mapping(pru->mapped_irq[pru->evt_count]); + } + + kfree(pru->mapped_irq); +} + +/* + * Parse the custom PRU interrupt map resource and configure the INTC + * appropriately. + */ +static int pru_handle_intrmap(struct rproc *rproc) +{ + struct device *dev = rproc->dev.parent; + struct pru_rproc *pru = rproc->priv; + struct pru_irq_rsc *rsc = pru->pru_interrupt_map; + struct irq_fwspec fwspec; + struct device_node *irq_parent; + int i, ret = 0; + + /* not having pru_interrupt_map is not an error */ + if (!rsc) + return 0; + + /* currently supporting only type 0 */ + if (rsc->type != 0) { + dev_err(dev, "unsupported rsc type: %d\n", rsc->type); + return -EINVAL; + } + + if (rsc->num_evts < 0 || rsc->num_evts > MAX_PRU_SYS_EVENTS) + return -EINVAL; + + if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) != + pru->pru_interrupt_map_sz) + return -EINVAL; + + pru->evt_count = rsc->num_evts; + pru->mapped_irq = kcalloc(pru->evt_count, sizeof(int), GFP_KERNEL); + if (!pru->mapped_irq) + return -ENOMEM; + + /* + * parse and fill in system event to interrupt channel and + * channel-to-host mapping + */ + irq_parent = of_irq_find_parent(pru->dev->of_node); + if (!irq_parent) { + kfree(pru->mapped_irq); + return -ENODEV; + } + + fwspec.fwnode = of_node_to_fwnode(irq_parent); + fwspec.param_count = 3; + for (i = 0; i < pru->evt_count; i++) { + fwspec.param[0] = rsc->pru_intc_map[i].event; + fwspec.param[1] = rsc->pru_intc_map[i].chnl; + fwspec.param[2] = rsc->pru_intc_map[i].host; + + dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", + i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); + + pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec); + if (pru->mapped_irq[i] < 0) { + dev_err(dev, "failed to get virq\n"); + ret = pru->mapped_irq[i]; + goto map_fail; + } + } + + return ret; + +map_fail: + pru_dispose_irq_mapping(pru); + + return ret; +} + static int pru_rproc_start(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; u32 val; + int ret; dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", pru->id, (rproc->bootaddr >> 2)); + ret = pru_handle_intrmap(rproc); + /* + * reset references to pru interrupt map - they will stop being valid + * after rproc_start returns + */ + pru->pru_interrupt_map = NULL; + pru->pru_interrupt_map_sz = 0; + if (ret) + return ret; + val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); pru_control_write_reg(pru, PRU_CTRL_CTRL, val); @@ -113,6 +218,10 @@ static int pru_rproc_stop(struct rproc *rproc) val &= ~CTRL_CTRL_EN; pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + /* dispose irq mapping - new firmware can provide new mapping */ + if (pru->mapped_irq) + pru_dispose_irq_mapping(pru); + return 0; } @@ -275,12 +384,70 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) return ret; } +static const void * +pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw) +{ + struct elf32_shdr *shdr, *name_table_shdr; + const char *name_table; + const u8 *elf_data = fw->data; + struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data; + u16 shnum = ehdr->e_shnum; + u16 shstrndx = ehdr->e_shstrndx; + int i; + + /* first, get the section header */ + shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff); + /* compute name table section header entry in shdr array */ + name_table_shdr = shdr + shstrndx; + /* finally, compute the name table section address in elf */ + name_table = elf_data + name_table_shdr->sh_offset; + + for (i = 0; i < shnum; i++, shdr++) { + u32 size = shdr->sh_size; + u32 offset = shdr->sh_offset; + u32 name = shdr->sh_name; + + if (strcmp(name_table + name, ".pru_irq_map")) + continue; + + /* make sure we have the entire irq map */ + if (offset + size > fw->size || offset + size < size) { + dev_err(dev, ".pru_irq_map section truncated\n"); + return ERR_PTR(-EINVAL); + } + + /* make sure irq map has at least the header */ + if (sizeof(struct pru_irq_rsc) > size) { + dev_err(dev, "header-less .pru_irq_map section\n"); + return ERR_PTR(-EINVAL); + } + + return shdr; + } + + dev_dbg(dev, "no .pru_irq_map section found for this fw\n"); + + return NULL; +} + /* * Use a custom parse_fw callback function for dealing with PRU firmware * specific sections. + * + * The firmware blob can contain optional ELF sections: .resource_table section + * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping + * description, which needs to be setup before powering on the PRU core. To + * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the + * firmware linker) and therefore is not loaded to PRU memory. */ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) { + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + const u8 *elf_data = fw->data; + const void *shdr; + u8 class = fw_elf_get_class(fw); + u64 sh_offset; int ret; /* load optional rsc table */ @@ -290,6 +457,19 @@ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) else if (ret) return ret; + /* find .pru_interrupt_map section, not having it is not an error */ + shdr = pru_rproc_find_interrupt_map(dev, fw); + if (IS_ERR(shdr)) + return PTR_ERR(shdr); + + if (!shdr) + return 0; + + /* preserve pointer to PRU interrupt map together with it size */ + sh_offset = elf_shdr_get_sh_offset(class, shdr); + pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset); + pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr); + return 0; } diff --git a/drivers/remoteproc/pru_rproc.h b/drivers/remoteproc/pru_rproc.h new file mode 100644 index 000000000000..8ee9c3171610 --- /dev/null +++ b/drivers/remoteproc/pru_rproc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * PRUSS Remote Processor specific types + * + * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#ifndef _PRU_RPROC_H_ +#define _PRU_RPROC_H_ + +/** + * struct pruss_int_map - PRU system events _to_ channel and host mapping + * @event: number of the system event + * @chnl: channel number assigned to a given @event + * @host: host number assigned to a given @chnl + * + * PRU system events are mapped to channels, and these channels are mapped + * to host interrupts. Events can be mapped to channels in a one-to-one or + * many-to-one ratio (multiple events per channel), and channels can be + * mapped to host interrupts in a one-to-one or many-to-one ratio (multiple + * channels per interrupt). + */ +struct pruss_int_map { + u8 event; + u8 chnl; + u8 host; +}; + +/** + * struct pru_irq_rsc - PRU firmware section header for IRQ data + * @type: resource type + * @num_evts: number of described events + * @pru_intc_map: PRU interrupt routing description + * + * The PRU firmware blob can contain optional .pru_irq_map ELF section, which + * provides the PRUSS interrupt mapping description. The pru_irq_rsc struct + * describes resource entry format. + */ +struct pru_irq_rsc { + u8 type; + u8 num_evts; + struct pruss_int_map pru_intc_map[]; +} __packed; + +#endif /* _PRU_RPROC_H_ */ From patchwork Thu Nov 19 14:08:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11917521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33FF3C6379D for ; Thu, 19 Nov 2020 14:09:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E49B1246D3 for ; Thu, 19 Nov 2020 14:09:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vBSuYvg1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727476AbgKSOJF (ORCPT ); Thu, 19 Nov 2020 09:09:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727473AbgKSOJE (ORCPT ); Thu, 19 Nov 2020 09:09:04 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 342E0C061A4C for ; Thu, 19 Nov 2020 06:09:04 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id f11so8434100lfs.3 for ; Thu, 19 Nov 2020 06:09:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n4GxPRhf1TIGU81EpUXbruLnn+BtpK1ExU2vHQeREY0=; b=vBSuYvg13KmMeZL1yU4f5RRFf2wzhxAAcTCsgZ4SjZGbB+CV44bCK567h0U9AC7EES 92cx325b0q4voNl5msMSWjJqd0bi+vhJZufqBc1ZtDrJ/w4cUAVL+fAPYVgiHOgP5TiF DdJfdiyh3vMa43X0A0m2pcaH9I43d7hIa5l55xIthcXsSJg/Le476tH4L6UXPVYu51Nr 9C3eyiHlR0Hj0l3TayZmFwkvdNmlOV34i2T3plBQQlcQLnxa2gp/zYEWQk5/DP6F9Xsp xrT/f1UjN2qmUa4JxIiqika4OtW3fb5LH+wYYb7ICQ64FtqnPZLvXABJcJTltJhbEuvo 41Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n4GxPRhf1TIGU81EpUXbruLnn+BtpK1ExU2vHQeREY0=; b=tlpVrdzufaau2hW0zbhjbj3TrY4AlqO7rQD/xbt8vTMQczE8XAfuep8qELQxJfkjNj vHderXKlFm2NpuFUpidDAVYRvIxwDiy7aniJ3wn1QNA72Rk1pIDkifFKSKvj5r3Nm/IH ylZkuTZVHFUzdcQKtZ9RhivBHVTfL0I8UlKNlVHja5osSpwPiS5/FVOrCDIttvOLD28o F0YfS1eMp94bvaf6FoL53Y+4LckOIVHjbPtCcwhAqcGVWp9C0WUYa0vdEO1nF0aRvGAu tas/e7I+tN3aXjC7S7qdoSln++fuQG1WCntd8egSzUcgiYaTbug2FFxJZSjk3sjffVdO jTug== X-Gm-Message-State: AOAM5324nm/G7040Z8tKPjzqa5FCh4wqsVDM5w2zbZ3Y8xxqRygV4W8w 3wmKg30ueMliV56mm0ZXJgN54Q== X-Google-Smtp-Source: ABdhPJyRn7A1RKV3RZMiI/5shJL442Wtsn6rGAWrt1d4D3IYdyuCRSB8OhszdrQHx0sgxe/oG82RhA== X-Received: by 2002:a19:e04:: with SMTP id 4mr5611671lfo.193.1605794942614; Thu, 19 Nov 2020 06:09:02 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h12sm4024706lfl.74.2020.11.19.06.09.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 06:09:01 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v2 4/6] remoteproc/pru: Add pru-specific debugfs support Date: Thu, 19 Nov 2020 15:08:48 +0100 Message-Id: <20201119140850.12268-5-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> References: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The remoteproc core creates certain standard debugfs entries, that does not give a whole lot of useful information for the PRUs. The PRU remoteproc driver is enhanced to add additional debugfs entries for PRU. These will be auto-cleaned up when the parent rproc debug directory is removed. The enhanced debugfs support adds two new entries: 'regs' and 'single_step'. The 'regs' dumps out the useful CTRL sub-module registers as well as each of the 32 GPREGs and CT_REGs registers. The GPREGs and CT_REGs though are printed only when the PRU is halted and accessible as per the IP design. The 'single_step' utilizes the single-step execution of the PRU cores. Writing a non-zero value performs a single step, and a zero value restores the PRU to execute in the same mode as the mode before the first single step. (note: if the PRU is halted because of a halt instruction, then no change occurs). Logic for setting the PC and jumping over a halt instruction shall be added in the future. Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- drivers/remoteproc/pru_rproc.c | 137 +++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index c68c3d6bfddd..d5f04d77ad54 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -25,6 +26,13 @@ /* PRU_ICSS_PRU_CTRL registers */ #define PRU_CTRL_CTRL 0x0000 #define PRU_CTRL_STS 0x0004 +#define PRU_CTRL_WAKEUP_EN 0x0008 +#define PRU_CTRL_CYCLE 0x000C +#define PRU_CTRL_STALL 0x0010 +#define PRU_CTRL_CTBIR0 0x0020 +#define PRU_CTRL_CTBIR1 0x0024 +#define PRU_CTRL_CTPPR0 0x0028 +#define PRU_CTRL_CTPPR1 0x002C /* CTRL register bit-fields */ #define CTRL_CTRL_SOFT_RST_N BIT(0) @@ -34,6 +42,10 @@ #define CTRL_CTRL_SINGLE_STEP BIT(8) #define CTRL_CTRL_RUNSTATE BIT(15) +/* PRU_ICSS_PRU_DEBUG registers */ +#define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) +#define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) + /* PRU Core IRAM address masks */ #define PRU_IRAM_ADDR_MASK 0x3ffff #define PRU0_IRAM_ADDR_MASK 0x34000 @@ -73,6 +85,8 @@ enum pru_iomem { * @mapped_irq: virtual interrupt numbers of created fw specific mapping * @pru_interrupt_map: pointer to interrupt mapping description (firmware) * @pru_interrupt_map_sz: pru_interrupt_map size + * @dbg_single_step: debug state variable to set PRU into single step mode + * @dbg_continuous: debug state variable to restore PRU execution mode * @evt_count: number of mapped events */ struct pru_rproc { @@ -85,6 +99,8 @@ struct pru_rproc { int *mapped_irq; struct pru_irq_rsc *pru_interrupt_map; size_t pru_interrupt_map_sz; + u32 dbg_single_step; + u32 dbg_continuous; u8 evt_count; }; @@ -99,6 +115,125 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg) +{ + return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg); +} + +static int regs_show(struct seq_file *s, void *data) +{ + struct rproc *rproc = s->private; + struct pru_rproc *pru = rproc->priv; + int i, nregs = 32; + u32 pru_sts; + int pru_is_running; + + seq_puts(s, "============== Control Registers ==============\n"); + seq_printf(s, "CTRL := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTRL)); + pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS); + seq_printf(s, "STS (PC) := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2); + seq_printf(s, "WAKEUP_EN := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN)); + seq_printf(s, "CYCLE := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CYCLE)); + seq_printf(s, "STALL := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_STALL)); + seq_printf(s, "CTBIR0 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTBIR0)); + seq_printf(s, "CTBIR1 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTBIR1)); + seq_printf(s, "CTPPR0 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTPPR0)); + seq_printf(s, "CTPPR1 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTPPR1)); + + seq_puts(s, "=============== Debug Registers ===============\n"); + pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) & + CTRL_CTRL_RUNSTATE; + if (pru_is_running) { + seq_puts(s, "PRU is executing, cannot print/access debug registers.\n"); + return 0; + } + + for (i = 0; i < nregs; i++) { + seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n", + i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)), + i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i))); + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(regs); + +/* + * Control PRU single-step mode + * + * This is a debug helper function used for controlling the single-step + * mode of the PRU. The PRU Debug registers are not accessible when the + * PRU is in RUNNING state. + * + * Writing a non-zero value sets the PRU into single-step mode irrespective + * of its previous state. The PRU mode is saved only on the first set into + * a single-step mode. Writing a zero value will restore the PRU into its + * original mode. + */ +static int pru_rproc_debug_ss_set(void *data, u64 val) +{ + struct rproc *rproc = data; + struct pru_rproc *pru = rproc->priv; + u32 reg_val; + + val = val ? 1 : 0; + if (!val && !pru->dbg_single_step) + return 0; + + reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL); + + if (val && !pru->dbg_single_step) + pru->dbg_continuous = reg_val; + + if (val) + reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN; + else + reg_val = pru->dbg_continuous; + + pru->dbg_single_step = val; + pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val); + + return 0; +} + +static int pru_rproc_debug_ss_get(void *data, u64 *val) +{ + struct rproc *rproc = data; + struct pru_rproc *pru = rproc->priv; + + *val = pru->dbg_single_step; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get, + pru_rproc_debug_ss_set, "%llu\n"); + +/* + * Create PRU-specific debugfs entries + * + * The entries are created only if the parent remoteproc debugfs directory + * exists, and will be cleaned up by the remoteproc core. + */ +static void pru_rproc_create_debug_entries(struct rproc *rproc) +{ + if (!rproc->dbg_dir) + return; + + debugfs_create_file("regs", 0400, rproc->dbg_dir, + rproc, ®s_fops); + debugfs_create_file("single_step", 0600, rproc->dbg_dir, + rproc, &pru_rproc_debug_ss_fops); +} + static void pru_dispose_irq_mapping(struct pru_rproc *pru) { while (pru->evt_count--) { @@ -573,6 +708,8 @@ static int pru_rproc_probe(struct platform_device *pdev) return ret; } + pru_rproc_create_debug_entries(rproc); + dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); return 0; From patchwork Thu Nov 19 14:08:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 11917523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5C2DC64E7A for ; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id h12sm4024706lfl.74.2020.11.19.06.09.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 06:09:03 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v2 5/6] remoteproc/pru: Add support for various PRU cores on K3 AM65x SoCs Date: Thu, 19 Nov 2020 15:08:49 +0100 Message-Id: <20201119140850.12268-6-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> References: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. Enhance the existing PRU remoteproc driver to support these new PRU, RTU and Tx PRU cores by using specific compatibles. The initial names for the firmware images for each PRU core are retrieved from DT nodes, and can be adjusted through sysfs if required. The PRU remoteproc driver has to be specifically modified to use a custom memcpy function within its ELF loader implementation for these new cores in order to overcome a limitation with copying data into each of the core's IRAM memories. These memory ports support only 4-byte writes, and any sub-word order byte writes clear out the remaining bytes other than the bytes being written within the containing word. The default ARM64 memcpy also cannot be used as it throws an exception when the preferred 8-byte copy operation is attempted. This choice is made by using a state flag that is set only on K3 SoCs. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v1->v2: - Update documentation of pru_rproc_memcpy() according to Suman comments. - Update documentation of is_k3 flag. --- drivers/remoteproc/pru_rproc.c | 140 ++++++++++++++++++++++++++++++--- 1 file changed, 131 insertions(+), 9 deletions(-) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index d5f04d77ad54..48c1c51e0d42 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -46,10 +46,14 @@ #define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) #define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) -/* PRU Core IRAM address masks */ +/* PRU/RTU/Tx_PRU Core IRAM address masks */ #define PRU_IRAM_ADDR_MASK 0x3ffff #define PRU0_IRAM_ADDR_MASK 0x34000 #define PRU1_IRAM_ADDR_MASK 0x38000 +#define RTU0_IRAM_ADDR_MASK 0x4000 +#define RTU1_IRAM_ADDR_MASK 0x6000 +#define TX_PRU0_IRAM_ADDR_MASK 0xa000 +#define TX_PRU1_IRAM_ADDR_MASK 0xc000 /* PRU device addresses for various type of PRU RAMs */ #define PRU_IRAM_DA 0 /* Instruction RAM */ @@ -74,12 +78,38 @@ enum pru_iomem { PRU_IOMEM_MAX, }; +/** + * enum pru_type - PRU core type identifier + * + * @PRU_TYPE_PRU: Programmable Real-time Unit + * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit + * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit + * @PRU_TYPE_MAX: just keep this one at the end + */ +enum pru_type { + PRU_TYPE_PRU = 0, + PRU_TYPE_RTU, + PRU_TYPE_TX_PRU, + PRU_TYPE_MAX, +}; + +/** + * struct pru_private_data - device data for a PRU core + * @type: type of the PRU core (PRU, RTU, Tx_PRU) + * @is_k3: flag used to identify the need for special load handling + */ +struct pru_private_data { + enum pru_type type; + unsigned int is_k3 : 1; +}; + /** * struct pru_rproc - PRU remoteproc structure * @id: id of the PRU core within the PRUSS * @dev: PRU core device pointer * @pruss: back-reference to parent PRUSS structure * @rproc: remoteproc pointer for this PRU core + * @data: PRU core specific data * @mem_regions: data for each of the PRU memory regions * @fw_name: name of firmware image used during loading * @mapped_irq: virtual interrupt numbers of created fw specific mapping @@ -94,6 +124,7 @@ struct pru_rproc { struct device *dev; struct pruss *pruss; struct rproc *rproc; + const struct pru_private_data *data; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; const char *fw_name; int *mapped_irq; @@ -319,11 +350,12 @@ static int pru_rproc_start(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; u32 val; int ret; - dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", - pru->id, (rproc->bootaddr >> 2)); + dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n", + names[pru->data->type], pru->id, (rproc->bootaddr >> 2)); ret = pru_handle_intrmap(rproc); /* @@ -345,9 +377,10 @@ static int pru_rproc_stop(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; u32 val; - dev_dbg(dev, "stopping PRU%d\n", pru->id); + dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id); val = pru_control_read_reg(pru, PRU_CTRL_CTRL); val &= ~CTRL_CTRL_EN; @@ -459,9 +492,52 @@ static struct rproc_ops pru_rproc_ops = { .da_to_va = pru_rproc_da_to_va, }; +/* + * Custom memory copy implementation for ICSSG PRU/RTU/Tx_PRU Cores + * + * The ICSSG PRU/RTU/Tx_PRU cores have a memory copying issue with IRAM + * memories, that is not seen on previous generation SoCs. The data is reflected + * properly in the IRAM memories only for integer (4-byte) copies. Any unaligned + * copies result in all the other pre-existing bytes zeroed out within that + * 4-byte boundary, thereby resulting in wrong text/code in the IRAMs. Also, the + * IRAM memory port interface does not allow any 8-byte copies (as commonly used + * by ARM64 memcpy implementation) and throws an exception. The DRAM memory + * ports do not show this behavior. + */ +static int pru_rproc_memcpy(void *dest, const void *src, size_t count) +{ + const int *s = src; + int *d = dest; + int size = count / 4; + int *tmp_src = NULL; + + /* + * TODO: relax limitation of 4-byte aligned dest addresses and copy + * sizes + */ + if ((long)dest % 4 || count % 4) + return -EINVAL; + + /* src offsets in ELF firmware image can be non-aligned */ + if ((long)src % 4) { + tmp_src = kmemdup(src, count, GFP_KERNEL); + if (!tmp_src) + return -ENOMEM; + s = tmp_src; + } + + while (size--) + *d++ = *s++; + + kfree(tmp_src); + + return 0; +} + static int pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) { + struct pru_rproc *pru = rproc->priv; struct device *dev = &rproc->dev; struct elf32_hdr *ehdr; struct elf32_phdr *phdr; @@ -513,7 +589,17 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) if (!phdr->p_filesz) continue; - memcpy(ptr, elf_data + phdr->p_offset, filesz); + if (pru->data->is_k3 && is_iram) { + ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset, + filesz); + if (ret) { + dev_err(dev, "PRU memory copy failed for da 0x%x memsz 0x%x\n", + da, memsz); + break; + } + } else { + memcpy(ptr, elf_data + phdr->p_offset, filesz); + } } return ret; @@ -617,9 +703,17 @@ static int pru_rproc_set_id(struct pru_rproc *pru) int ret = 0; switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { + case TX_PRU0_IRAM_ADDR_MASK: + fallthrough; + case RTU0_IRAM_ADDR_MASK: + fallthrough; case PRU0_IRAM_ADDR_MASK: pru->id = 0; break; + case TX_PRU1_IRAM_ADDR_MASK: + fallthrough; + case RTU1_IRAM_ADDR_MASK: + fallthrough; case PRU1_IRAM_ADDR_MASK: pru->id = 1; break; @@ -640,8 +734,13 @@ static int pru_rproc_probe(struct platform_device *pdev) struct rproc *rproc = NULL; struct resource *res; int i, ret; + const struct pru_private_data *data; const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; + data = of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + ret = of_property_read_string(np, "firmware-name", &fw_name); if (ret) { dev_err(dev, "unable to retrieve firmware-name %d\n", ret); @@ -674,6 +773,7 @@ static int pru_rproc_probe(struct platform_device *pdev) pru = rproc->priv; pru->dev = dev; + pru->data = data; pru->pruss = platform_get_drvdata(ppdev); pru->rproc = rproc; pru->fw_name = fw_name; @@ -725,11 +825,33 @@ static int pru_rproc_remove(struct platform_device *pdev) return 0; } +static const struct pru_private_data pru_data = { + .type = PRU_TYPE_PRU, +}; + +static const struct pru_private_data k3_pru_data = { + .type = PRU_TYPE_PRU, + .is_k3 = 1, +}; + +static const struct pru_private_data k3_rtu_data = { + .type = PRU_TYPE_RTU, + .is_k3 = 1, +}; + +static const struct pru_private_data k3_tx_pru_data = { + .type = PRU_TYPE_TX_PRU, + .is_k3 = 1, +}; + static const struct of_device_id pru_rproc_match[] = { - { .compatible = "ti,am3356-pru", }, - { .compatible = "ti,am4376-pru", }, - { .compatible = "ti,am5728-pru", }, - { .compatible = "ti,k2g-pru", }, + { .compatible = "ti,am3356-pru", .data = &pru_data }, + { .compatible = "ti,am4376-pru", .data = &pru_data }, + { .compatible = "ti,am5728-pru", .data = &pru_data }, + { .compatible = "ti,k2g-pru", .data = &pru_data }, + { .compatible = "ti,am654-pru", .data = &k3_pru_data }, + { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, + { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, {}, }; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id h12sm4024706lfl.74.2020.11.19.06.09.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 06:09:04 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v2 6/6] remoteproc/pru: Add support for various PRU cores on K3 J721E SoCs Date: Thu, 19 Nov 2020 15:08:50 +0100 Message-Id: <20201119140850.12268-7-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> References: <20201119140850.12268-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna The K3 J721E family of SoCs have a revised version of the AM65x ICSSG IP and contains two instances of this newer ICSSG IP. Each ICSSG processor subsystem contains 2 primary PRU cores, 2 auxiliary PRU cores called RTUs, and 2 new auxiliary cores called Transmit PRUs (Tx_PRUs). Enhance the existing PRU remoteproc driver to support these new PRU and RTU cores by using specific compatibles. The cores have the same memory copying limitations as on AM65x, so reuses the custom memcpy function within the driver's ELF loader implementation. The initial names for the firmware images for each PRU core are retrieved from DT nodes, and can be adjusted through sysfs if required. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- drivers/remoteproc/pru_rproc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 48c1c51e0d42..96f689283a8b 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -852,6 +852,9 @@ static const struct of_device_id pru_rproc_match[] = { { .compatible = "ti,am654-pru", .data = &k3_pru_data }, { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, + { .compatible = "ti,j721e-pru", .data = &k3_pru_data }, + { .compatible = "ti,j721e-rtu", .data = &k3_rtu_data }, + { .compatible = "ti,j721e-tx-pru", .data = &k3_tx_pru_data }, {}, }; MODULE_DEVICE_TABLE(of, pru_rproc_match);