From patchwork Thu Nov 19 17:04:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 11918391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23ECAC56201 for ; Thu, 19 Nov 2020 17:04:35 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8397621D7F for ; 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Thu, 19 Nov 2020 10:04:22 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:19 -0700 From: To: , , , , , , Subject: [PATCH 1/6] mbox: add polarfire soc system controller mailbox Date: Thu, 19 Nov 2020 17:04:19 +0000 Message-ID: <20201119170419.18272-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_120424_088090_D6BDEBCA X-CRM114-Status: GOOD ( 22.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox-mpfs.c | 296 +++++++++++++++++++++++++++++++++ 3 files changed, 310 insertions(+) create mode 100644 drivers/mailbox/mailbox-mpfs.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 05b1009e2820..4881a519683a 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -153,6 +153,18 @@ config MAILBOX_TEST Test client to help with testing new Controller driver implementations. +config MPFS_MBOX + tristate "MPFS Mailbox" + depends on HAS_IOMEM + depends on SOC_MICROCHIP_POLARFIRE + help + This driver adds support for the Polarfire SoC mailbox controller. + + To compile this driver as a module, choose M here. the + module will be called mailbox-mpfs. + + If unsure, say Y. + config QCOM_APCS_IPC tristate "Qualcomm APCS IPC driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 2e06e02b2e03..63f49b5bcc43 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -39,6 +39,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o +obj-$(CONFIG_MPFS_MBOX) += mailbox-mpfs.o + obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c new file mode 100644 index 000000000000..686ccd3317f9 --- /dev/null +++ b/drivers/mailbox/mailbox-mpfs.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip MPFS system controller/mailbox controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERVICES_CR_OFFSET 0x50u +#define SERVICES_SR_OFFSET 0x54u +#define MAILBOX_REG_OFFSET 0x800u +#define MSS_SYS_SUCCESS 0u +#define MSS_SYS_BUSY 0xefu +#define MSS_SYS_PARAM_ERR 0xffu +#define MSS_SYS_MAILBOX_DATA_OFFSET 0u + +/***************SCBCTRL SERVICES_CR register*************************/ + +#define SCBCTRL_SERVICESCR_REQ (0u) +#define SCBCTRL_SERVICESCR_REQ_MASK BIT(SCBCTRL_SERVICESCR_REQ) + +#define SCBCTRL_SERVICESCR_BUSY (1u) +#define SCBCTRL_SERVICESCR_BUSY_MASK BIT(SCBCTRL_SERVICESCR_BUSY) + +#define SCBCTRL_SERVICESCR_ABORT (2u) +#define SCBCTRL_SERVICESCR_ABORT_MASK BIT(SCBCTRL_SERVICESCR_ABORT) + +#define SCBCTRL_SERVICESCR_NOTIFY (3u) +#define SCBCTRL_SERVICESCR_NOTIFY_MASK BIT(SCBCTRL_SERVICESCR_NOTIFY) + +#define SCBCTRL_SERVICESCR_COMMAND (16u) +#define SCBCTRL_SERVICESCR_COMMAND_MASK (0xffffu << SCBCTRL_SERVICESCR_COMMAND) + +/***************SCBCTRL SERVICES_SR registers*************************/ + +#define SCBCTRL_SERVICESSR_REQ (0u) +#define SCBCTRL_SERVICESSR_REQ_MASK BIT(SCBCTRL_SERVICESSR_REQ) + +#define SCBCTRL_SERVICESSR_BUSY (1u) +#define SCBCTRL_SERVICESSR_BUSY_MASK BIT(SCBCTRL_SERVICESSR_BUSY) + +#define SCBCTRL_SERVICESSR_ABORT (2u) +#define SCBCTRL_SERVICESSR_ABORT_MASK BIT(SCBCTRL_SERVICESSR_ABORT) + +#define SCBCTRL_SERVICESSR_NOTIFY (3u) +#define SCBCTRL_SERVICESSR_NOTIFY_MASK BIT(SCBCTRL_SERVICESSR_NOTIFY) + +#define SCBCTRL_SERVICESSR_STATUS (16u) +#define SCBCTRL_SERVICESSR_STATUS_MASK (0xffffu << SCBCTRL_SERVICESSR_STATUS) + +struct mpfs_mbox { + struct mbox_controller controller; + struct device *dev; + int irq; + void __iomem *mailbox_base; + void __iomem *int_reg; + struct mbox_chan *chan; + u16 response_size; + u16 response_offset; +}; + +static int mpfs_mbox_busy(struct mpfs_mbox *mbox) +{ + u32 status; + + status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET); + + return status & SCBCTRL_SERVICESSR_BUSY_MASK; +} + +static struct mpfs_mbox *mbox_chan_to_mpfs_mbox(struct mbox_chan *chan) +{ + if (!chan || !chan->con_priv) + return NULL; + + return (struct mpfs_mbox *)chan->con_priv; +} + +static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data) +{ + u32 index; + u32 *word_buf; + u8 *byte_buf; + u8 byte_off; + u8 byte_index; + u32 mailbox_val = 0u; + u16 mb_offset; + u16 mbox_options_select; + u32 mbox_tx_trigger; + + struct mpfs_mss_msg *msg = data; + + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + + mb_offset = msg->mailbox_offset; + mbox->response_size = msg->response_size; + mbox->response_offset = msg->response_offset; + + mbox_options_select = ((mb_offset << 7u) | (msg->cmd_opcode & 0x7fu)); + mbox_tx_trigger = (((mbox_options_select << SCBCTRL_SERVICESCR_COMMAND) & + SCBCTRL_SERVICESCR_COMMAND_MASK) | + SCBCTRL_SERVICESCR_REQ_MASK | SCBCTRL_SERVICESSR_NOTIFY_MASK); + + if (mpfs_mbox_busy(mbox)) + return MSS_SYS_BUSY; + + /* Code for MSS_SYS_PARAM_ERR is not implemented with this version of driver. */ + + writel_relaxed(0x0U, mbox->int_reg); + + if (msg->cmd_data_size > 0u) { + byte_buf = (u8 *)(msg->cmd_data); + + for (index = 0u; index < (msg->cmd_data_size / 4u); index++) { + writel_relaxed(word_buf[index], + mbox->mailbox_base + MAILBOX_REG_OFFSET + index); + } + + if ((msg->cmd_data_size % 4u) > 0u) { + byte_off = (((msg->cmd_data_size / 4u) * 4u)); + byte_buf = (u8 *)(msg->cmd_data + byte_off); + + mailbox_val = readl_relaxed(mbox->mailbox_base + + MAILBOX_REG_OFFSET + index); + + for (byte_index = 0u; + byte_index < (msg->cmd_data_size % 4u); + byte_index++) { + mailbox_val &= ~(0xffu << (byte_index * 8u)); + mailbox_val |= (byte_buf[byte_index] + << (byte_index * 8u)); + } + + writel_relaxed(mailbox_val, + mbox->mailbox_base + MAILBOX_REG_OFFSET + index); + } + } + + writel_relaxed(mbox_tx_trigger, mbox->mailbox_base + SERVICES_CR_OFFSET); + + return MSS_SYS_SUCCESS; +} + +static inline int mpfs_mbox_pending(struct mpfs_mbox *mbox) +{ + u32 status; + + status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET); + + return !(status & SCBCTRL_SERVICESSR_BUSY_MASK); +} + +static void mpfs_mbox_rx_data(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + u32 *data; + u32 index; + u32 response_limit; + + data = devm_kzalloc(mbox->dev, sizeof(*data) * mbox->response_size, + GFP_ATOMIC); + + response_limit = (mbox->response_size) + (mbox->response_offset); + if (mpfs_mbox_pending(mbox) && mbox->response_size > 0U) { + for (index = (mbox->response_offset); index < response_limit; + index++) { + data[index - (mbox->response_offset)] = + readl_relaxed(mbox->mailbox_base + MAILBOX_REG_OFFSET + + index * 0x4); + } + } + + mbox_chan_received_data(chan, (void *)data); + devm_kfree(mbox->dev, data); +} + +static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data) +{ + struct mbox_chan *chan = (struct mbox_chan *)data; + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + + writel_relaxed(0x0U, mbox->int_reg); + + mpfs_mbox_rx_data(chan); + + mbox_chan_txdone(chan, 0); + return IRQ_HANDLED; +} + +static int mpfs_mbox_startup(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + int ret = 0; + + if (!mbox) + return -EINVAL; + ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, + "mpfs-mailbox", chan); + if (unlikely(ret)) { + dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", + ret); + return ret; + } + + return ret; +} + +static void mpfs_mbox_shutdown(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + + devm_free_irq(mbox->dev, mbox->irq, chan); +} + +static const struct mbox_chan_ops mpfs_mbox_ops = { + .send_data = mpfs_mbox_send_data, + .startup = mpfs_mbox_startup, + .shutdown = mpfs_mbox_shutdown, +}; + +static int mpfs_mbox_probe(struct platform_device *pdev) +{ + struct mpfs_mbox *mbox; + struct resource *regs; + struct mbox_chan *chans; + int ret; + + mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL); + if (!chans) + return -ENOMEM; + + mbox->mailbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); + if (IS_ERR(mbox->mailbox_base)) + return PTR_ERR(mbox->mailbox_base); + + mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s); + if (IS_ERR(mbox->int_reg)) + return PTR_ERR(mbox->int_reg); + + mbox->irq = platform_get_irq(pdev, 0); + + mbox->dev = &pdev->dev; + + chans[0].con_priv = mbox; + mbox->controller.dev = mbox->dev; + mbox->controller.num_chans = 1; + mbox->controller.chans = chans; + mbox->controller.ops = &mpfs_mbox_ops; + mbox->controller.txdone_irq = true; + + ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller); + if (ret) { + dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n"); + return -1; + } + dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n"); + + return 0; +} + +static const struct of_device_id mpfs_mbox_of_match[] = { + { + .compatible = "microchip,polarfire-soc-mailbox", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match); + +static struct platform_driver mpfs_mbox_driver = { + .driver = { + .name = "mpfs-mailbox", + .of_match_table = mpfs_mbox_of_match, + }, + .probe = mpfs_mbox_probe, +}; +module_platform_driver(mpfs_mbox_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS mailbox controller driver"); From patchwork Thu Nov 19 17:04:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 11918393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC282C56201 for ; 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19 Nov 2020 10:04:28 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 10:04:28 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:26 -0700 From: To: , , , , , , Subject: [PATCH 2/6] soc: add polarfire soc header file Date: Thu, 19 Nov 2020 17:04:25 +0000 Message-ID: <20201119170425.18365-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_120430_753568_F0561409 X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add header to support the Microchip PolarFire SoC MSS system controller mailbox. Signed-off-by: Conor Dooley --- include/soc/microchip/mpfs.h | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/soc/microchip/mpfs.h diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h new file mode 100644 index 000000000000..60311ab72b76 --- /dev/null +++ b/include/soc/microchip/mpfs.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Microchip MPFS mailbox + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#ifndef __SOC_MPFS_H__ +#define __SOC_MPFS_H__ + +#include +#include + +struct mpfs_sys_controller; + +struct mpfs_mss_msg { + u8 cmd_opcode; + u16 cmd_data_size; + u16 response_size; + u8 *cmd_data; + u16 mailbox_offset; + u16 response_offset; +}; + +#if IS_ENABLED(CONFIG_MPFS_SYS_CONTROLLER) + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes); + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node); + +#else + +static int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes) +{ + return -ENOSYS; +}; + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node) +{ + return NULL; +} + +#endif /* IS_ENABLED(CONFIG_MPFS_SYS_CONTROLLER) */ + +#endif /* __SOC_MPFS_H__ */ From patchwork Thu Nov 19 17:04:32 2020 Content-Type: text/plain; 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IronPort-SDR: twP0lV55qIj4uhBEJJoMmatuSRmMsmxrXTnt3O3D2EAn9mxIj4XcEMl86CYvpXyBD6YZglgWnw 8PTeaUlztTK0ObqGZkG2SNS6RWL3WQHo/AAaXVWhWYOrObCvChQU0mQmCYoMJSKBV4eJRuN0t3 5uqK3H246EfDXPVRrAd3aSzAWLPbw13alBfvuX/j23Phsc/DPfUHgheONd3E4OOrGEY6yPU0af OvKrAxuRWyArSGEb6+hmBOJ8pRN3sbrY7rKp6xZ0UMQp919/o833FZM9t0ZXfXEgIm+ofBOd9l osA= X-IronPort-AV: E=Sophos;i="5.78,353,1599548400"; d="scan'208";a="99698547" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Nov 2020 10:04:35 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 10:04:34 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:32 -0700 From: To: , , , , , , Subject: [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox Date: Thu, 19 Nov 2020 17:04:32 +0000 Message-ID: <20201119170432.18447-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_120437_318732_0CDA81B4 X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add device tree bindings for the MSS system controller mailbox on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../mailbox/microchip,mpfs-mailbox.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml new file mode 100644 index 000000000000..5d6ccaa13dc2 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS mss mailbox controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-mailbox # PolarFire + + reg: + items: + - description: mailbox data registers + - description: mailbox int registers + maxItems: 2 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupt-parent + - interrupts + - "#mbox-cells" + +unevaluatedProperties: false +additionalProperties: false + +examples: + - | + mailbox@37020000 { + compatible = "microchip,polarfire-soc-mailbox"; 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Thu, 19 Nov 2020 10:04:40 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:37 -0700 From: To: , , , , , , Subject: [PATCH 4/6] soc: add polarfire soc system controller Date: Thu, 19 Nov 2020 17:04:37 +0000 Message-ID: <20201119170437.18519-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_120443_314446_C658E5FF X-CRM114-Status: GOOD ( 20.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/microchip/Kconfig | 10 ++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs_sys_controller.c | 136 ++++++++++++++++++++ 5 files changed, 149 insertions(+) create mode 100644 drivers/soc/microchip/Kconfig create mode 100644 drivers/soc/microchip/Makefile create mode 100644 drivers/soc/microchip/mpfs_sys_controller.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..22cb097bcbdc 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/microchip/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..fb084cf2d12e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ +obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/ obj-y += mediatek/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig new file mode 100644 index 000000000000..8fdba8b5eae3 --- /dev/null +++ b/drivers/soc/microchip/Kconfig @@ -0,0 +1,10 @@ +config MPFS_SYS_CONTROLLER + tristate "MPFS_SYS_CONTROLLER" + depends on MPFS_MBOX + help + This driver adds support for the Polarfire SoC system controller. + + To compile this driver as a module, choose M here. the + module will be called mpfs_system_controller. + + If unsure, say Y. diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile new file mode 100644 index 000000000000..23b1f42a37db --- /dev/null +++ b/drivers/soc/microchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MPFS_SYS_CONTROLLER) += mpfs_sys_controller.o diff --git a/drivers/soc/microchip/mpfs_sys_controller.c b/drivers/soc/microchip/mpfs_sys_controller.c new file mode 100644 index 000000000000..0074ae529a2e --- /dev/null +++ b/drivers/soc/microchip/mpfs_sys_controller.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip MPFS system controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(transaction_lock); + +struct mpfs_sys_controller { + struct mbox_client client; + struct mbox_chan *chan; + struct completion c; + u32 enabled; + void *response; + u16 response_size_bytes; +}; + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes) +{ + int ret; + + mpfs_client->response = response; + mpfs_client->response_size_bytes = response_size_bytes; + + mutex_lock_interruptible(&transaction_lock); + + reinit_completion(&mpfs_client->c); + + ret = mbox_send_message(mpfs_client->chan, msg); + + if (ret >= 0U) { + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) { + ret = 0U; + } else { + ret = -ETIMEDOUT; + WARN_ONCE(1, "MPFS sys controller transaction timeout"); + } + } else { + dev_err(mpfs_client->client.dev, + "mpfs sys controller transaction returned %d\r\n", ret); + } + + mutex_unlock(&transaction_lock); + + return ret; +} +EXPORT_SYMBOL(mpfs_blocking_transaction); + +static void rx_callback(struct mbox_client *client, void *msg) +{ + struct mpfs_sys_controller *mpfs_client = + container_of(client, struct mpfs_sys_controller, client); + + memcpy(mpfs_client->response, (u8 *)msg, + mpfs_client->response_size_bytes); + + complete(&mpfs_client->c); +} + +static int mpfs_sys_controller_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_sys_controller *mpfs_client; + + mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL); + if (!mpfs_client) + return -ENOMEM; + + mpfs_client->client.dev = dev; + mpfs_client->client.rx_callback = rx_callback; + mpfs_client->client.tx_block = 1U; + + mpfs_client->chan = mbox_request_channel_byname(&mpfs_client->client, + "mbox-mpfs"); + if (IS_ERR(mpfs_client->chan)) { + int ret = PTR_ERR(mpfs_client->chan); + + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get mbox channel: %d\n", ret); + return ret; + } + + init_completion(&mpfs_client->c); + + platform_set_drvdata(pdev, mpfs_client); + + dev_info(&pdev->dev, "Registered MPFS system controller driver\n"); + + return 0; +} + +struct mpfs_sys_controller * +mpfs_sys_controller_get(struct device_node *mss_node) +{ + struct platform_device *pdev = of_find_device_by_node(mss_node); + + if (!pdev) + return NULL; + + return platform_get_drvdata(pdev); +} +EXPORT_SYMBOL(mpfs_sys_controller_get); + +static const struct of_device_id mpfs_sys_controller_of_match[] = { + { + .compatible = "microchip,polarfire-soc-sys-controller", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match); + +static struct platform_driver mpfs_sys_controller_driver = { + .driver = { + .name = "mpfs-sys-controller", + .of_match_table = mpfs_sys_controller_of_match, + }, + .probe = mpfs_sys_controller_probe, +}; +module_platform_driver(mpfs_sys_controller_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS system controller driver"); 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Thu, 19 Nov 2020 10:04:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:42 -0700 From: To: , , , , , , Subject: [PATCH 5/6] dt-bindings: add bindings for polarfire soc system controller Date: Thu, 19 Nov 2020 17:04:41 +0000 Message-ID: <20201119170441.18706-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_120445_582604_F0C7F14B X-CRM114-Status: GOOD ( 11.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add device tree bindings for the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../microchip,mpfs_sys_controller.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml new file mode 100644 index 000000000000..a1c5bba5068c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs_sys_controller.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS system controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-sys-controller # PolarFire + + mbox-names: + maxItems: 1 + description: name of the mailbox controller device node + + mboxes: + maxItems: 1 + description: | + phandle and index of the mailbox controller device node. It must be 0 (hardware supports only one channel). + + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +required: + - compatible + - mbox-names + - "#address-cells" + - "#size-cells" + - "mboxes" + +unevaluatedProperties: false +additionalProperties: false + +examples: + - | + syscontroller@37020000 { + compatible = "microchip,polarfire-soc-sys-controller"; + #address-cells = <1>; + #size-cells = <1>; + mbox-names = "mbox-mpfs"; + mboxes = <&mbox 0>; + }; From patchwork Thu Nov 19 17:04:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 11918401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45CD5C56201 for ; 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19 Nov 2020 10:04:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 10:04:48 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:46 -0700 From: To: , , , , , , Subject: [PATCH 6/6] MAINTAINERS: add microchip polarfire soc support Date: Thu, 19 Nov 2020 17:04:45 +0000 Message-ID: <20201119170445.18795-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_120452_018699_763A1AC7 X-CRM114-Status: UNSURE ( 7.38 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC directory Signed-off-by: Conor Dooley --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3da6d8c154e4..2965daaa80e9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15000,6 +15000,15 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT +M: Lewis Hanly +M: Cyril Jean +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/mailbox/mailbox-mpfs.c +F: drivers/soc/microchip/ +F: include/soc/microchip/mpfs.h + RNBD BLOCK DRIVERS M: Danil Kipnis M: Jack Wang