From patchwork Tue Nov 6 16:47:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lis, Tomasz" X-Patchwork-Id: 10670825 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 011E31751 for ; Tue, 6 Nov 2018 16:47:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E45192852E for ; Tue, 6 Nov 2018 16:47:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D87172A2B8; Tue, 6 Nov 2018 16:47:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 94F522A25B for ; Tue, 6 Nov 2018 16:47:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04FAB6E3B8; Tue, 6 Nov 2018 16:47:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id CF1596E3B8 for ; Tue, 6 Nov 2018 16:47:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2018 08:47:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,472,1534834800"; d="scan'208";a="271819186" Received: from szara.igk.intel.com ([172.28.178.192]) by orsmga005.jf.intel.com with ESMTP; 06 Nov 2018 08:47:28 -0800 From: Tomasz Lis To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Nov 2018 17:47:26 +0100 Message-Id: <1541522847-29479-1-git-send-email-tomasz.lis@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH v5 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The MOCS tables are going to be very similar across platforms. To reduce the amount of copied code, this patch rips the common part and puts it into a definition valid for all gen9 platforms. v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE to MOCS_ENTRIES. (Joonas) Signed-off-by: Tomasz Lis Suggested-by: Lucas De Marchi Reviewed-by: Lucas De Marchi Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Daniele Ceraolo Spurio Cc: Lucas De Marchi --- drivers/gpu/drm/i915/intel_mocs.c | 86 ++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 77e9871..8d08a7b 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -96,71 +96,57 @@ struct drm_i915_mocs_table { * may only be updated incrementally by adding entries at the * end. */ -static const struct drm_i915_mocs_entry skylake_mocs_table[] = { - [I915_MOCS_UNCACHED] = { - /* 0x00000009 */ - .control_value = LE_CACHEABILITY(LE_UC) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - - /* 0x0010 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), - }, - [I915_MOCS_PTE] = { - /* 0x00000038 */ - .control_value = LE_CACHEABILITY(LE_PAGETABLE) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + +#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \ + (LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \ + LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \ + LE_PFM(pfm) | LE_SCF(scf)) + +#define MOCS_L3CC_VALUE(esc, scc, l3cc) \ + (L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc)) + +#define GEN9_MOCS_ENTRIES \ + [I915_MOCS_UNCACHED] = { \ + /* 0x00000009 */ \ + .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC, \ + 0, 0, 0, 0, 0, 0), \ + /* 0x0010 */ \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [I915_MOCS_PTE] = { \ + /* 0x00000038 */ \ + .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC_ELLC, \ + 3, 0, 0, 0, 0, 0), \ + /* 0x0030 */ \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ }, + +static const struct drm_i915_mocs_entry skylake_mocs_table[] = { + GEN9_MOCS_ENTRIES [I915_MOCS_CACHED] = { /* 0x0000003b */ - .control_value = LE_CACHEABILITY(LE_WB) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC_ELLC, + 3, 0, 0, 0, 0, 0), /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), }, }; /* NOTE: the LE_TGT_CACHE is not used on Broxton */ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { - [I915_MOCS_UNCACHED] = { - /* 0x00000009 */ - .control_value = LE_CACHEABILITY(LE_UC) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - - /* 0x0010 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), - }, - [I915_MOCS_PTE] = { - /* 0x00000038 */ - .control_value = LE_CACHEABILITY(LE_PAGETABLE) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - - /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), - }, + GEN9_MOCS_ENTRIES [I915_MOCS_CACHED] = { /* 0x00000039 */ - .control_value = LE_CACHEABILITY(LE_UC) | - LE_TGT_CACHE(LE_TC_LLC_ELLC) | - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | - LE_PFM(0) | LE_SCF(0), - + .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC, + 3, 0, 0, 0, 0, 0), /* 0x0030 */ - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), }, }; +#undef MOCS_CONTROL_VALUE +#undef MOCS_L3CC_VALUE + /** * get_mocs_settings() * @dev_priv: i915 device. From patchwork Tue Nov 6 16:47:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lis, Tomasz" X-Patchwork-Id: 10670827 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 371BF13BF for ; Tue, 6 Nov 2018 16:47:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 269CE2852E for ; Tue, 6 Nov 2018 16:47:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A48F2A2B8; Tue, 6 Nov 2018 16:47:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 638FF2852E for ; Tue, 6 Nov 2018 16:47:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D9A36E3C1; Tue, 6 Nov 2018 16:47:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6ADEE6E3C1 for ; Tue, 6 Nov 2018 16:47:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2018 08:47:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,472,1534834800"; d="scan'208";a="271819190" Received: from szara.igk.intel.com ([172.28.178.192]) by orsmga005.jf.intel.com with ESMTP; 06 Nov 2018 08:47:30 -0800 From: Tomasz Lis To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Nov 2018 17:47:27 +0100 Message-Id: <1541522847-29479-2-git-send-email-tomasz.lis@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541522847-29479-1-git-send-email-tomasz.lis@intel.com> References: <1541522847-29479-1-git-send-email-tomasz.lis@intel.com> Subject: [Intel-gfx] [PATCH v5 2/2] drm/i915/icl: Define MOCS table for Icelake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Adam Cetnerowski , Piotr Rozenfeld , Lucas De Marchi , Anuj Phogat , Mika Kuoppala MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The table has been unified across OSes to minimize virtualization overhead. The MOCS table is now published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Meaning of each entry is now explained in bspec, and user mode clients are expected to know what each entry means. The 3 entries used for previous platforms are still compatible with their legacy definitions, but that is not guaranteed to be true for future platforms. v2: Fixed SCC values, improved commit comment (Daniele) v3: Improved MOCS table comment (Daniele) v4: Moved new entries below gen9 ones. Put common entries into definition to be used in multiple arrays. (Lucas) v5: Made defines for or-ing flags. Renamed macros from MOCS_TABLE to MOCS_ENTRIES. Switched LE_CoS to upper case. (Joonas) BSpec: 34007 BSpec: 560 Signed-off-by: Tomasz Lis Reviewed-by: Daniele Ceraolo Spurio (v4) Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Mika Kuoppala Cc: Daniele Ceraolo Spurio Cc: Zhenyu Wang Cc: Zhi A Wang Cc: Anuj Phogat Cc: Adam Cetnerowski Cc: Piotr Rozenfeld Cc: Lucas De Marchi --- drivers/gpu/drm/i915/intel_mocs.c | 206 +++++++++++++++++++++++++++++++++++--- 1 file changed, 192 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 8d08a7b..030a61d 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -44,6 +44,8 @@ struct drm_i915_mocs_table { #define LE_SCC(value) ((value) << 8) #define LE_PFM(value) ((value) << 11) #define LE_SCF(value) ((value) << 14) +#define LE_COS(value) ((value) << 15) +#define LE_SSE(value) ((value) << 17) /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) ((value) << 0) @@ -80,21 +82,21 @@ struct drm_i915_mocs_table { * LNCFCMOCS0 - LNCFCMOCS32 registers. * * These tables are intended to be kept reasonably consistent across - * platforms. However some of the fields are not applicable to all of - * them. + * HW platforms, and for ICL+, be identical across OSes. To achieve + * that, for Icelake and above, list of entries is published as part + * of bspec. * * Entries not part of the following tables are undefined as far as - * userspace is concerned and shouldn't be relied upon. For the time - * being they will be implicitly initialized to the strictest caching - * configuration (uncached) to guarantee forwards compatibility with - * userspace programs written against more recent kernels providing - * additional MOCS entries. + * userspace is concerned and shouldn't be relied upon. * - * NOTE: These tables MUST start with being uncached and the length - * MUST be less than 63 as the last two registers are reserved - * by the hardware. These tables are part of the kernel ABI and - * may only be updated incrementally by adding entries at the - * end. + * The last two entries are reserved by the hardware. For ICL+ they + * should be initialized according to bspec and never used, for older + * platforms they should never be written to. + * + * NOTE: These tables are part of bspec and defined as part of hardware + * interface for ICL+. For older platforms, they are part of kernel + * ABI. It is expected that existing entries will remain constant + * and the tables will only be updated by adding new entries. */ #define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \ @@ -147,6 +149,179 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { #undef MOCS_CONTROL_VALUE #undef MOCS_L3CC_VALUE +#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf, cos, sse) \ + (LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \ + LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \ + LE_PFM(pfm) | LE_SCF(scf) | LE_COS(cos) | LE_SSE(sse)) + +#define MOCS_L3CC_VALUE(esc, scc, l3cc) \ + (L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc)) + +#define GEN11_MOCS_ENTRIES \ + [0] = { \ + /* Base - Uncached (Deprecated) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \ + 0, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [1] = { \ + /* Base - L3 + LeCC:PAT (Deprecated) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC, \ + 0, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [2] = { \ + /* Base - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [3] = { \ + /* Base - Uncached */ \ + .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \ + 0, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [4] = { \ + /* Base - L3 */ \ + .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \ + 0, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [5] = { \ + /* Base - LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [6] = { \ + /* Age 0 - LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 1, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [7] = { \ + /* Age 0 - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 1, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [8] = { \ + /* Age: Don't Chg. - LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 2, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [9] = { \ + /* Age: Don't Chg. - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 2, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [10] = { \ + /* No AOM - LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 1, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [11] = { \ + /* No AOM - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 1, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [12] = { \ + /* No AOM; Age 0 - LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 1, 1, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [13] = { \ + /* No AOM; Age 0 - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 1, 1, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [14] = { \ + /* No AOM; Age:DC - LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 2, 1, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [15] = { \ + /* No AOM; Age:DC - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 2, 1, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [18] = { \ + /* Self-Snoop - L3 + LLC */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 0, 0, 0, 0, 3), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [19] = { \ + /* Skip Caching - L3 + LLC(12.5%) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 7, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [20] = { \ + /* Skip Caching - L3 + LLC(25%) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 3, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [21] = { \ + /* Skip Caching - L3 + LLC(50%) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 1, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [22] = { \ + /* Skip Caching - L3 + LLC(75%) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 1, 3, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [23] = { \ + /* Skip Caching - L3 + LLC(87.5%) */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 1, 7, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \ + }, \ + [62] = { \ + /* HW Reserved - SW program but never use */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, \ + [63] = { \ + /* HW Reserved - SW program but never use */ \ + .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \ + 3, 0, 0, 0, 0, 0, 0, 0), \ + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \ + }, + +static const struct drm_i915_mocs_entry icelake_mocs_table[] = { + GEN11_MOCS_ENTRIES + [16] = { + /* Reserved - For future use */ + .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE, + 0, 0, 0, 0, 0, 0, 0, 0), + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_DIRECT), + }, + [17] = { + /* Reserved - For future use */ + .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE, + 0, 0, 0, 0, 0, 0, 0, 0), + .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_DIRECT), + }, +}; + +#undef MOCS_CONTROL_VALUE +#undef MOCS_L3CC_VALUE + /** * get_mocs_settings() * @dev_priv: i915 device. @@ -164,8 +339,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, { bool result = false; - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || - IS_ICELAKE(dev_priv)) { + if (IS_ICELAKE(dev_priv)) { + table->size = ARRAY_SIZE(icelake_mocs_table); + table->table = icelake_mocs_table; + result = true; + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true;